README.md
1# cpuid
2Package cpuid provides information about the CPU running the current program.
3
4CPU features are detected on startup, and kept for fast access through the life of the application.
5Currently x86 / x64 (AMD64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
6
7You can access the CPU information by accessing the shared CPU variable of the cpuid library.
8
9Package home: https://github.com/klauspost/cpuid
10
11[![GoDoc][1]][2] [![Build Status][3]][4]
12
13[1]: https://godoc.org/github.com/klauspost/cpuid?status.svg
14[2]: https://godoc.org/github.com/klauspost/cpuid
15[3]: https://travis-ci.org/klauspost/cpuid.svg
16[4]: https://travis-ci.org/klauspost/cpuid
17
18# features
19## CPU Instructions
20* **CMOV** (i686 CMOV)
21* **NX** (NX (No-Execute) bit)
22* **AMD3DNOW** (AMD 3DNOW)
23* **AMD3DNOWEXT** (AMD 3DNowExt)
24* **MMX** (standard MMX)
25* **MMXEXT** (SSE integer functions or AMD MMX ext)
26* **SSE** (SSE functions)
27* **SSE2** (P4 SSE functions)
28* **SSE3** (Prescott SSE3 functions)
29* **SSSE3** (Conroe SSSE3 functions)
30* **SSE4** (Penryn SSE4.1 functions)
31* **SSE4A** (AMD Barcelona microarchitecture SSE4a instructions)
32* **SSE42** (Nehalem SSE4.2 functions)
33* **AVX** (AVX functions)
34* **AVX2** (AVX2 functions)
35* **FMA3** (Intel FMA 3)
36* **FMA4** (Bulldozer FMA4 functions)
37* **XOP** (Bulldozer XOP functions)
38* **F16C** (Half-precision floating-point conversion)
39* **BMI1** (Bit Manipulation Instruction Set 1)
40* **BMI2** (Bit Manipulation Instruction Set 2)
41* **TBM** (AMD Trailing Bit Manipulation)
42* **LZCNT** (LZCNT instruction)
43* **POPCNT** (POPCNT instruction)
44* **AESNI** (Advanced Encryption Standard New Instructions)
45* **CLMUL** (Carry-less Multiplication)
46* **HTT** (Hyperthreading (enabled))
47* **HLE** (Hardware Lock Elision)
48* **RTM** (Restricted Transactional Memory)
49* **RDRAND** (RDRAND instruction is available)
50* **RDSEED** (RDSEED instruction is available)
51* **ADX** (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
52* **SHA** (Intel SHA Extensions)
53* **AVX512F** (AVX-512 Foundation)
54* **AVX512DQ** (AVX-512 Doubleword and Quadword Instructions)
55* **AVX512IFMA** (AVX-512 Integer Fused Multiply-Add Instructions)
56* **AVX512PF** (AVX-512 Prefetch Instructions)
57* **AVX512ER** (AVX-512 Exponential and Reciprocal Instructions)
58* **AVX512CD** (AVX-512 Conflict Detection Instructions)
59* **AVX512BW** (AVX-512 Byte and Word Instructions)
60* **AVX512VL** (AVX-512 Vector Length Extensions)
61* **AVX512VBMI** (AVX-512 Vector Bit Manipulation Instructions)
62* **AVX512VBMI2** (AVX-512 Vector Bit Manipulation Instructions, Version 2)
63* **AVX512VNNI** (AVX-512 Vector Neural Network Instructions)
64* **AVX512VPOPCNTDQ** (AVX-512 Vector Population Count Doubleword and Quadword)
65* **GFNI** (Galois Field New Instructions)
66* **VAES** (Vector AES)
67* **AVX512BITALG** (AVX-512 Bit Algorithms)
68* **VPCLMULQDQ** (Carry-Less Multiplication Quadword)
69* **AVX512BF16** (AVX-512 BFLOAT16 Instructions)
70* **AVX512VP2INTERSECT** (AVX-512 Intersect for D/Q)
71* **MPX** (Intel MPX (Memory Protection Extensions))
72* **ERMS** (Enhanced REP MOVSB/STOSB)
73* **RDTSCP** (RDTSCP Instruction)
74* **CX16** (CMPXCHG16B Instruction)
75* **SGX** (Software Guard Extensions, with activation details)
76* **VMX** (Virtual Machine Extensions)
77
78## Performance
79* **RDTSCP()** Returns current cycle count. Can be used for benchmarking.
80* **SSE2SLOW** (SSE2 is supported, but usually not faster)
81* **SSE3SLOW** (SSE3 is supported, but usually not faster)
82* **ATOM** (Atom processor, some SSSE3 instructions are slower)
83* **Cache line** (Probable size of a cache line).
84* **L1, L2, L3 Cache size** on newer Intel/AMD CPUs.
85
86## Cpu Vendor/VM
87* **Intel**
88* **AMD**
89* **VIA**
90* **Transmeta**
91* **NSC**
92* **KVM** (Kernel-based Virtual Machine)
93* **MSVM** (Microsoft Hyper-V or Windows Virtual PC)
94* **VMware**
95* **XenHVM**
96* **Bhyve**
97* **Hygon**
98
99# installing
100
101```go get github.com/klauspost/cpuid```
102
103# example
104
105```Go
106package main
107
108import (
109 "fmt"
110 "github.com/klauspost/cpuid"
111)
112
113func main() {
114 // Print basic CPU information:
115 fmt.Println("Name:", cpuid.CPU.BrandName)
116 fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
117 fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
118 fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
119 fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
120 fmt.Println("Features:", cpuid.CPU.Features)
121 fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
122 fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
123 fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
124 fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
125 fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")
126
127 // Test if we have a specific feature:
128 if cpuid.CPU.SSE() {
129 fmt.Println("We have Streaming SIMD Extensions")
130 }
131}
132```
133
134Sample output:
135```
136>go run main.go
137Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
138PhysicalCores: 2
139ThreadsPerCore: 2
140LogicalCores: 4
141Family 6 Model: 42
142Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
143Cacheline bytes: 64
144We have Streaming SIMD Extensions
145```
146
147# private package
148
149In the "private" folder you can find an autogenerated version of the library you can include in your own packages.
150
151For this purpose all exports are removed, and functions and constants are lowercased.
152
153This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.
154
155# license
156
157This code is published under an MIT license. See LICENSE file for more information.
158
