1 /*
2 * Driver for CL-GD5480.
3 * Itai Nahshon.
4 *
5 * Support for the CL-GD7548: David Monniaux
6 *
7 * This is mainly a cut & paste from the MGA driver.
8 * Original autors and contributors list include:
9 * Radoslaw Kapitan, Andrew Vanderstock, Dirk Hohndel,
10 * David Dawes, Andrew E. Mileski, Leonard N. Zubkoff,
11 * Guy DESBIEF
12 */
13
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17
18 /* All drivers should typically include these */
19 #include "xf86.h"
20 #include "xf86_OSproc.h"
21
22 /* All drivers need this */
23
24 /* Everything using inb/outb, etc needs "compiler.h" */
25 #include "compiler.h"
26
27 /* Drivers that need to access the PCI config space directly need this */
28 #include "xf86Pci.h"
29
30 /* All drivers using the vgahw module need this */
31 /* This driver needs to be modified to not use vgaHW for multihead operation */
32 #include "vgaHW.h"
33
34 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 6
35 #include "xf86RAC.h"
36 #include "xf86Resources.h"
37 #endif
38
39 /* All drivers initialising the SW cursor need this */
40 #include "mipointer.h"
41
42 #include "micmap.h"
43
44 /* Needed by the Shadow Framebuffer */
45 #include "shadowfb.h"
46
47 /* Note: can HWCUR64 be set even though the hw cursor is disabled for
48 want of memory ? */
49
50 /* Framebuffer memory manager */
51 #include "xf86fbman.h"
52
53 #if HAVE_XF4BPP
54 #include "xf4bpp.h"
55 #endif
56 #if HAVE_XF1BPP
57 #include "xf1bpp.h"
58 #endif
59
60 #include "fb.h"
61
62
63 #include "xf86DDC.h"
64 #include "xf86int10.h"
65
66 #include "cir.h"
67 #define _ALP_PRIVATE_
68 #include "alp.h"
69
70 #include "xf86xv.h"
71 #include <X11/extensions/Xv.h>
72
73 #ifdef ALPPROBEI2C
74 /* For debugging... should go away. */
75 static void AlpProbeI2C(int scrnIndex);
76 #endif
77
78 /*
79 * Forward definitions for the functions that make up the driver.
80 */
81
82 /* Mandatory functions */
83
84 Bool AlpPreInit(ScrnInfoPtr pScrn, int flags);
85 Bool AlpScreenInit(SCREEN_INIT_ARGS_DECL);
86 Bool AlpEnterVT(VT_FUNC_ARGS_DECL);
87 void AlpLeaveVT(VT_FUNC_ARGS_DECL);
88 static Bool AlpCloseScreen(CLOSE_SCREEN_ARGS_DECL);
89 static Bool AlpSaveScreen(ScreenPtr pScreen, int mode);
90
91 /* Required if the driver supports mode switching */
92 Bool AlpSwitchMode(SWITCH_MODE_ARGS_DECL);
93 /* Required if the driver supports moving the viewport */
94 void AlpAdjustFrame(ADJUST_FRAME_ARGS_DECL);
95
96 /* Optional functions */
97 void AlpFreeScreen(FREE_SCREEN_ARGS_DECL);
98 ModeStatus AlpValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
99 Bool verbose, int flags);
100 /* Internally used functions */
101 static void AlpSave(ScrnInfoPtr pScrn);
102 static void AlpRestore(ScrnInfoPtr pScrn);
103 static Bool AlpModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
104
105 static void AlpProbeLCD(ScrnInfoPtr pScrn);
106
107 static void AlpSetClock(CirPtr pCir, vgaHWPtr hwp, int freq);
108
109 static void AlpOffscreenAccelInit(ScrnInfoPtr pScrn);
110
111 static void AlpDisplayPowerManagementSet(ScrnInfoPtr pScrn,
112 int PowerManagementMode, int flags);
113
114 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
115 static void PC98CIRRUS755xEnable(ScrnInfoPtr pScrn);
116 static void PC98CIRRUS755xDisable(ScrnInfoPtr pScrn);
117 #endif
118
119 /*
120 * This is intentionally screen-independent. It indicates the binding
121 * choice made in the first PreInit.
122 */
123 static int pix24bpp = 0;
124
125 typedef enum {
126 OPTION_HW_CURSOR,
127 OPTION_PCI_RETRY,
128 OPTION_NOACCEL,
129 OPTION_MMIO,
130 OPTION_ROTATE,
131 OPTION_SHADOW_FB,
132 OPTION_MEMCFG1,
133 OPTION_MEMCFG2
134 } CirOpts;
135
136 static const OptionInfoRec CirOptions[] = {
137 { OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE },
138 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
139 { OPTION_MMIO, "MMIO", OPTV_BOOLEAN, {0}, FALSE },
140 { OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE },
141 { OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
142 { OPTION_MEMCFG1, "MemCFG1", OPTV_INTEGER, {0}, -1 },
143 { OPTION_MEMCFG2, "MemCFG2", OPTV_INTEGER, {0}, -1 },
144 { -1, NULL, OPTV_NONE, {0}, FALSE }
145 };
146
147 /* 1/4bpp 8bpp 15/16bpp 24bpp 32bpp
148 static int unsupp_MaxClocks[] = { 0, 0, 0, 0, 0 }; */
149 static int gd5430_MaxClocks[] = { 85500, 85500, 50000, 28500, 0 };
150 static int gd5446_MaxClocks[] = { 135100, 135100, 85500, 85500, 0 };
151 static int gd5480_MaxClocks[] = { 135100, 200000, 200000, 135100, 135100 };
152 static int gd7548_MaxClocks[] = { 80100, 80100, 80100, 80100, 80100 };
153 static int gd7555_MaxClocks[] = { 80100, 80100, 80100, 80100, 80100 };
154 static int gd7556_MaxClocks[] = { 80100, 80100, 80100, 80100, 80100 };
155
156 #ifdef XFree86LOADER
157
158 #define ALP_MAJOR_VERSION 1
159 #define ALP_MINOR_VERSION 0
160 #define ALP_PATCHLEVEL 0
161
162 static XF86ModuleVersionInfo alpVersRec =
163 {
164 "cirrus_alpine",
165 MODULEVENDORSTRING,
166 MODINFOSTRING1,
167 MODINFOSTRING2,
168 XORG_VERSION_CURRENT,
169 ALP_MAJOR_VERSION, ALP_MINOR_VERSION, ALP_PATCHLEVEL,
170 ABI_CLASS_VIDEODRV, /* This is a video driver */
171 ABI_VIDEODRV_VERSION,
172 MOD_CLASS_NONE,
173 {0,0,0,0}
174 };
175
176 /*
177 * This is the module init data.
178 * Its name has to be the driver name followed by ModuleData.
179 */
180 _X_EXPORT XF86ModuleData cirrus_alpineModuleData = {
181 &alpVersRec,
182 NULL,
183 NULL
184 };
185
186 #endif /* XFree86LOADER */
187
188 _X_EXPORT const OptionInfoRec *
AlpAvailableOptions(int chipid)189 AlpAvailableOptions(int chipid)
190 {
191 return CirOptions;
192 }
193
194 _X_EXPORT ScrnInfoPtr
AlpProbe(int entity)195 AlpProbe(int entity)
196 {
197 ScrnInfoPtr pScrn = NULL;
198
199 if ((pScrn = xf86ConfigPciEntity(pScrn, 0, entity, CIRPciChipsets,
200 NULL,NULL, NULL, NULL, NULL))) {
201 pScrn->PreInit = AlpPreInit;
202 pScrn->ScreenInit = AlpScreenInit;
203 pScrn->SwitchMode = AlpSwitchMode;
204 pScrn->AdjustFrame = AlpAdjustFrame;
205 pScrn->EnterVT = AlpEnterVT;
206 pScrn->LeaveVT = AlpLeaveVT;
207 pScrn->FreeScreen = AlpFreeScreen;
208 pScrn->ValidMode = AlpValidMode;
209 }
210
211 return pScrn;
212 }
213
214
215 static Bool
AlpGetRec(ScrnInfoPtr pScrn)216 AlpGetRec(ScrnInfoPtr pScrn)
217 {
218 #ifdef ALP_DEBUG
219 ErrorF("AlpGetRec\n");
220 #endif
221 if (pScrn->driverPrivate != NULL)
222 return TRUE;
223
224 pScrn->driverPrivate = xnfcalloc(sizeof(CirRec), 1);
225 ((CirPtr)pScrn->driverPrivate)->chip.alp = xnfcalloc(sizeof(AlpRec),1);
226
227 #ifdef ALP_DEBUG
228 ErrorF("AlpGetRec 0x%x\n", CIRPTR(pScrn));
229 #endif
230 return TRUE;
231 }
232
233 static void
AlpFreeRec(ScrnInfoPtr pScrn)234 AlpFreeRec(ScrnInfoPtr pScrn)
235 {
236 if (pScrn->driverPrivate == NULL)
237 return;
238 free(pScrn->driverPrivate);
239 pScrn->driverPrivate = NULL;
240 }
241
242
243 /*
244 * AlpCountRAM --
245 *
246 * Counts amount of installed RAM
247 *
248 * XXX Can use options to configure memory on non-primary cards.
249 */
250 static int
AlpCountRam(ScrnInfoPtr pScrn)251 AlpCountRam(ScrnInfoPtr pScrn)
252 {
253 CirPtr pCir = CIRPTR(pScrn);
254 vgaHWPtr hwp = VGAHWPTR(pScrn);
255 MessageType from;
256 int videoram = 0;
257
258 /* Map the Alp memory and MMIO areas */
259 pCir->FbMapSize = 1024*1024; /* XX temp */
260 if (!pCir->IoMapSize)
261 pCir->IoMapSize = 0x4000; /* 16K for moment */
262 if (!CirMapMem(pCir, pScrn->scrnIndex))
263 return 0;
264
265 /* The 754x supports MMIO for the BitBlt engine but
266 not for the VGA registers */
267 switch (pCir->Chipset)
268 {
269 case PCI_CHIP_GD7548:
270 break;
271 default:
272 if (pCir->UseMMIO)
273 vgaHWSetMmioFuncs(hwp, pCir->IOBase, -0x3C0);
274 }
275
276 if (pCir->chip.alp->sr0f != (CARD32)-1) {
277 from = X_CONFIG;
278 hwp->writeSeq(hwp, 0x0F, pCir->chip.alp->sr0f);
279 } else {
280 from = X_PROBED;
281 pCir->chip.alp->sr0f = hwp->readSeq(hwp, 0x0F);
282 }
283 xf86DrvMsg(pScrn->scrnIndex, from, "Memory Config reg 1 is 0x%02X\n",
284 (unsigned int)pCir->chip.alp->sr0f);
285
286 switch (pCir->Chipset) {
287 case PCI_CHIP_GD5430:
288 /* case PCI_CHIP_GD5440: */
289 switch (pCir->chip.alp->sr0f & 0x18) {
290 case 0x08:
291 videoram = 512;
292 break;
293 case 0x10:
294 videoram = 1024;
295 break;
296 case 0x18:
297 videoram = 2048;
298 break;
299 }
300 break;
301
302 case PCI_CHIP_GD5434_4:
303 case PCI_CHIP_GD5434_8:
304 case PCI_CHIP_GD5436:
305 switch (pCir->chip.alp->sr0f & 0x18) {
306 case 0x10:
307 videoram = 1024;
308 break;
309 case 0x18:
310 videoram = 2048;
311 if (pCir->chip.alp->sr0f & 0x80)
312 videoram = 4096;
313 break;
314 }
315
316 case PCI_CHIP_GD5446:
317 videoram = 1024;
318
319 if (pCir->chip.alp->sr17 != (CARD32)-1) {
320 from = X_CONFIG;
321 hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
322 } else {
323 from = X_PROBED;
324 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
325 }
326 xf86DrvMsg(pScrn->scrnIndex, from, "Memory Config reg 2 is 0x%02X\n",
327 (unsigned int)pCir->chip.alp->sr17);
328
329 if ((pCir->chip.alp->sr0f & 0x18) == 0x18) {
330 if (pCir->chip.alp->sr0f & 0x80) {
331 if (pCir->chip.alp->sr17 & 0x80)
332 videoram = 2048;
333 else if (pCir->chip.alp->sr17 & 0x02)
334 videoram = 3072;
335 else
336 videoram = 4096;
337 } else {
338 if ((pCir->chip.alp->sr17 & 80) == 0)
339 videoram = 2048;
340 }
341 }
342 break;
343
344 case PCI_CHIP_GD5480:
345 if (pCir->chip.alp->sr17 != (CARD32)-1) {
346 from = X_CONFIG;
347 hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
348 } else {
349 from = X_PROBED;
350 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
351 }
352 xf86DrvMsg(pScrn->scrnIndex, from, "Memory Config reg 2 is 0x%02X\n",
353 (unsigned int)pCir->chip.alp->sr17);
354 videoram = 1024;
355 if ((pCir->chip.alp->sr0f & 0x18) == 0x18) { /* 2 or 4 MB */
356 videoram = 2048;
357 if (pCir->chip.alp->sr0f & 0x80) /* Second bank enable */
358 videoram = 4096;
359 }
360 if (pCir->chip.alp->sr17 & 0x80)
361 videoram <<= 1;
362 break;
363
364 case PCI_CHIP_GD7548:
365 videoram = 1024;
366 switch (pCir->chip.alp->sr0f & 0x90) {
367 case 0x10:
368 /* TODO: 2 256K X 16 DRAMs (1024) or 4 512K X 8 DRAMs (2048)? */
369 break;
370 case 0x90:
371 videoram <<= 1;
372 break;
373 }
374 break;
375
376 case PCI_CHIP_GD7555:
377 case PCI_CHIP_GD7556:
378 videoram = 2048; /* for PC-9821 La13 etc. */
379 break;
380 }
381
382 /* UNMap the Alp memory and MMIO areas */
383 if (!CirUnmapMem(pCir, pScrn->scrnIndex))
384 return 0;
385 vgaHWSetStdFuncs(hwp);
386
387 return videoram;
388 }
389
390
391 /*
392 * GetAccelPitchValues -
393 *
394 * This function returns a list of display width (pitch) values that can
395 * be used in accelerated mode.
396 */
397 static int *
GetAccelPitchValues(ScrnInfoPtr pScrn)398 GetAccelPitchValues(ScrnInfoPtr pScrn)
399 {
400 int *linePitches = NULL;
401 int i, n = 0;
402 int max_pitch;
403
404 CirPtr pCir = CIRPTR(pScrn);
405
406 /* XXX ajv - 512, 576, and 1536 may not be supported
407 line pitches. see sdk pp 4-59 for more
408 details. Why anyone would want less than 640 is
409 bizarre. (maybe lots of pixels tall?) */
410
411 /* The only line pitches the accelerator supports */
412 #if 1
413 int accelWidths[] = { 640, 768, 800, 960, 1024, 1152, 1280,
414 1600, 1920, 2048, 0 };
415 #else
416 int accelWidths[] = { 512, 576, 640, 768, 800, 960, 1024, 1152,
417 1280, 1536, 1600, 1920, 2048, 0 };
418 #endif
419
420 switch (pCir->Chipset) {
421 case PCI_CHIP_GD5436:
422 case PCI_CHIP_GD5446:
423 max_pitch = 0x1ff << 3;
424 break;
425
426 default:
427 /* FIXME max_pitch for other chipsets? */
428 max_pitch = (pScrn->bitsPerPixel / 8) * 2048;
429 break;
430 }
431
432 for (i = 0; accelWidths[i] != 0; i++) {
433 if ((accelWidths[i] % pCir->Rounding == 0)
434 && ((accelWidths[i] * pScrn->bitsPerPixel / 8) <= max_pitch)) {
435 n++;
436 linePitches = xnfrealloc(linePitches, n * sizeof(int));
437 linePitches[n - 1] = accelWidths[i];
438 }
439 }
440 /* Mark the end of the list */
441 if (n > 0) {
442 linePitches = xnfrealloc(linePitches, (n + 1) * sizeof(int));
443 linePitches[n] = 0;
444 }
445 return linePitches;
446 }
447
448
449 /* Mandatory */
450 Bool
AlpPreInit(ScrnInfoPtr pScrn,int flags)451 AlpPreInit(ScrnInfoPtr pScrn, int flags)
452 {
453 CirPtr pCir;
454 vgaHWPtr hwp;
455 MessageType from, from1;
456 int i;
457 int defaultdepth;
458 int depth_flags;
459 ClockRangePtr clockRanges;
460 const char *s;
461 xf86Int10InfoPtr pInt = NULL;
462
463 if (flags & PROBE_DETECT) {
464 cirProbeDDC( pScrn, xf86GetEntityInfo(pScrn->entityList[0])->index );
465 return TRUE;
466 }
467
468 #ifdef ALP_DEBUG
469 ErrorF("AlpPreInit\n");
470 #endif
471
472 /* Check the number of entities, and fail if it isn't one. */
473 if (pScrn->numEntities != 1)
474 return FALSE;
475
476 if (!xf86LoadSubModule(pScrn, "vgahw"))
477 return FALSE;
478
479 /*
480 * Allocate a vgaHWRec
481 */
482 if (!vgaHWGetHWRec(pScrn))
483 return FALSE;
484 hwp = VGAHWPTR(pScrn);
485 vgaHWSetStdFuncs(hwp);
486 vgaHWGetIOBase(hwp);
487
488 /* Allocate the AlpRec driverPrivate */
489 if (!AlpGetRec(pScrn))
490 return FALSE;
491
492 pCir = CIRPTR(pScrn);
493 pCir->pScrn = pScrn;
494
495 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
496 pCir->PIOReg = hwp->PIOOffset + 0x3CE;
497 #else
498 pCir->PIOReg = 0x3CE;
499 #endif
500
501 /* Get the entity, and make sure it is PCI. */
502 pCir->pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
503 if (pCir->pEnt->location.type != BUS_PCI) {
504 free(pCir->pEnt);
505 return FALSE;
506 }
507
508 pCir->Chipset = pCir->pEnt->chipset;
509 /* Find the PCI info for this screen */
510 pCir->PciInfo = xf86GetPciInfoForEntity(pCir->pEnt->index);
511 #ifndef XSERVER_LIBPCIACCESS
512 pCir->PciTag = pciTag(PCI_DEV_BUS(pCir->PciInfo),
513 PCI_DEV_DEV(pCir->PciInfo),
514 PCI_DEV_FUNC(pCir->PciInfo));
515 #endif
516
517 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
518 if (!xf86IsPc98())
519 #endif
520 if (xf86LoadSubModule(pScrn, "int10"))
521 {
522 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n");
523 pInt = xf86InitInt10(pCir->pEnt->index);
524 xf86FreeInt10(pInt);
525 /*
526 * This is a hack: We restore the PCI base regs as some Colorgraphic
527 * BIOSes tend to mess them up
528 */
529
530 PCI_WRITE_LONG(pCir->PciInfo, PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM), 0x10);
531 PCI_WRITE_LONG(pCir->PciInfo, PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM), 0x14);
532 }
533
534 /* Set pScrn->monitor */
535 pScrn->monitor = pScrn->confScreen->monitor;
536
537 /* 32bpp only works on 5480 and 7548 */
538 depth_flags = Support24bppFb;
539 if (pCir->Chipset == PCI_CHIP_GD5480 || pCir->Chipset ==PCI_CHIP_GD7548)
540 depth_flags |= Support32bppFb |
541 SupportConvert32to24 |
542 PreferConvert32to24;
543
544 /* use 16bpp in virt and on XenSource */
545 #ifndef PCI_CHIP_QEMU
546 #define PCI_CHIP_QEMU 0x1af4
547 #endif
548 #define PCI_CHIP_XENSOURCE 0x5853
549 if (((pCir->PciInfo->subvendor_id & 0xffff) == PCI_CHIP_QEMU) ||
550 ((pCir->PciInfo->subvendor_id & 0xffff) == PCI_CHIP_XENSOURCE))
551 defaultdepth = 16;
552 else
553 defaultdepth = 24;
554
555 /*
556 * The first thing we should figure out is the depth, bpp, etc.
557 * We support both 24bpp and 32bpp layouts, so indicate that.
558 */
559 if (!xf86SetDepthBpp(pScrn, 0, 0, defaultdepth, depth_flags)) {
560 return FALSE;
561 } else {
562 /* Check that the returned depth is one we support */
563 switch (pScrn->depth) {
564 case 1:
565 case 4:
566 case 8:
567 case 15:
568 case 16:
569 case 24:
570 /* OK */
571 break;
572 default:
573 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
574 "Given depth (%d) is not supported by this driver\n",
575 pScrn->depth);
576 return FALSE;
577 }
578 }
579 xf86PrintDepthBpp(pScrn);
580
581 /* Get the depth24 pixmap format */
582 if (pScrn->depth == 24 && pix24bpp == 0)
583 pix24bpp = xf86GetBppFromDepth(pScrn, 24);
584
585 /*
586 * This must happen after pScrn->display has been set because
587 * xf86SetWeight references it.
588 */
589 if (pScrn->depth > 8) {
590 /* The defaults are OK for us */
591 rgb zeros = {0, 0, 0};
592
593 if (!xf86SetWeight(pScrn, zeros, zeros)) {
594 return FALSE;
595 } else {
596 /* XXX check that weight returned is supported */
597 ;
598 }
599 }
600
601 if (!xf86SetDefaultVisual(pScrn, -1)) {
602 return FALSE;
603 }
604 /* Collect all of the relevant option flags (fill in pScrn->options) */
605 xf86CollectOptions(pScrn, NULL);
606
607 /* Process the options */
608 if (!(pCir->Options = malloc(sizeof(CirOptions))))
609 return FALSE;
610 memcpy(pCir->Options, CirOptions, sizeof(CirOptions));
611 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pCir->Options);
612
613 if (!xf86IsPrimaryPci(pCir->PciInfo)
614 && !(pInt || (xf86IsOptionSet(pCir->Options,OPTION_MEMCFG1)
615 && xf86IsOptionSet(pCir->Options,OPTION_MEMCFG2))))
616 return FALSE;
617
618 if (pScrn->depth == 8)
619 pScrn->rgbBits = 6;
620
621 from = X_DEFAULT;
622 pCir->HWCursor = FALSE;
623
624 switch (pCir->Chipset) {
625 case PCI_CHIP_GD7555:
626 case PCI_CHIP_GD7556:
627 pCir->HWCursor = TRUE;
628 break;
629 default:
630 break;
631 }
632
633 if (xf86GetOptValBool(pCir->Options, OPTION_HW_CURSOR, &pCir->HWCursor))
634 from = X_CONFIG;
635
636 xf86DrvMsg(pScrn->scrnIndex, from, "Using %s cursor\n",
637 pCir->HWCursor ? "HW" : "SW");
638 if (xf86ReturnOptValBool(pCir->Options, OPTION_NOACCEL, FALSE)) {
639 pCir->NoAccel = TRUE;
640 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration disabled\n");
641 }
642 if(pScrn->bitsPerPixel < 8) {
643 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
644 "Cannot use accelerations in less than 8 bpp\n");
645 pCir->NoAccel = TRUE;
646 }
647
648 /*
649 * Set the ChipRev, allowing config file entries to
650 * override.
651 */
652 if (pCir->pEnt->device->chipRev >= 0) {
653 pCir->ChipRev = pCir->pEnt->device->chipRev;
654 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
655 pCir->ChipRev);
656 } else {
657 pCir->ChipRev = PCI_DEV_REVISION(pCir->PciInfo);
658 }
659
660 /* Find the frame buffer base address */
661 if (pCir->pEnt->device->MemBase != 0) {
662 if (!xf86CheckPciMemBase(pCir->PciInfo, pCir->pEnt->device->MemBase)) {
663 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
664 "MemBase 0x%08lX doesn't match any PCI base register.\n",
665 pCir->pEnt->device->MemBase);
666 return FALSE;
667 }
668 pCir->FbAddress = pCir->pEnt->device->MemBase;
669 from = X_CONFIG;
670 } else {
671 if (PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM) != 0) {
672 /* 5446B and 5480 use mask of 0xfe000000.
673 5446A uses 0xff000000. */
674 pCir->FbAddress = PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM) & 0xff000000;
675 from = X_PROBED;
676 } else {
677 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
678 "No valid FB address in PCI config space\n");
679 AlpFreeRec(pScrn);
680 return FALSE;
681 }
682 }
683 xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
684 (unsigned long)pCir->FbAddress);
685
686 if (pCir->pEnt->device->IOBase != 0) {
687 /* Require that the config file value matches one of the PCI values. */
688 if (!xf86CheckPciMemBase(pCir->PciInfo, pCir->pEnt->device->IOBase)) {
689 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
690 "IOBase 0x%08lX doesn't match any PCI base register.\n",
691 pCir->pEnt->device->IOBase);
692 return FALSE;
693 }
694 pCir->IOAddress = pCir->pEnt->device->IOBase;
695 from = X_CONFIG;
696 } else {
697 if (PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM) != 0) {
698 pCir->IOAddress = PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM) & 0xfffff000;
699 pCir->IoMapSize = PCI_REGION_SIZE(pCir->PciInfo, 1);
700 from = X_PROBED;
701 } else {
702 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
703 "No valid MMIO address in PCI config space\n");
704 /* 5446 rev A do not use a separate MMIO segment */
705 /* We do not really need that YET. */
706 }
707 }
708
709 /* User options can override the MMIO default */
710 #if 0
711 /* Will we ever support MMIO on 5446A or older? */
712 if (xf86ReturnOptValBool(pCir->Options, OPTION_MMIO, FALSE)) {
713 pCir->UseMMIO = TRUE;
714 from = X_CONFIG;
715 }
716 #endif
717 if (!xf86ReturnOptValBool(pCir->Options, OPTION_MMIO, TRUE)) {
718 pCir->UseMMIO = FALSE;
719 from1 = X_CONFIG;
720 } else if (pCir->IOAddress) {
721 /* Default to MMIO if we have a separate IOAddress and
722 not in monochrome mode (IO 0x3Bx is not relocated!) */
723 if (pScrn->bitsPerPixel != 1) {
724 pCir->UseMMIO = TRUE;
725 from1 = X_PROBED;
726 } else {
727 pCir->UseMMIO = FALSE;
728 from1 = X_PROBED;
729 }
730 } else {
731 pCir->UseMMIO = FALSE;
732 from1 = X_PROBED;
733 }
734
735 if (pCir->UseMMIO) {
736 xf86DrvMsg(pScrn->scrnIndex, from1, "Using MMIO\n");
737 xf86DrvMsg(pScrn->scrnIndex, from, "MMIO registers at 0x%lX\n",
738 (unsigned long)pCir->IOAddress);
739 } else
740 xf86DrvMsg(pScrn->scrnIndex, from1, "Not Using MMIO\n");
741
742 #ifndef XSERVER_LIBPCIACCESS
743 /*
744 * XXX Check if this is correct
745 */
746 if (!pCir->UseMMIO) {
747 pScrn->racIoFlags = RAC_COLORMAP | RAC_CURSOR | RAC_VIEWPORT | RAC_FB;
748 xf86SetOperatingState(resVgaMem, pCir->pEnt->index, ResUnusedOpr);
749 } else {
750 xf86SetOperatingState(resVga, pCir->pEnt->index, ResUnusedOpr);
751 }
752
753 /* Register the PCI-assigned resources. */
754 if (xf86RegisterResources(pCir->pEnt->index, NULL, ResExclusive)) {
755 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
756 "xf86RegisterResources() found resource conflicts\n");
757 return FALSE;
758 }
759 #endif
760
761 if (!xf86LoadSubModule(pScrn, "i2c")) {
762 AlpFreeRec(pScrn);
763 return FALSE;
764 }
765
766 if (!xf86LoadSubModule(pScrn, "ddc")) {
767 AlpFreeRec(pScrn);
768 return FALSE;
769 }
770
771 if(!AlpI2CInit(pScrn)) {
772 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
773 "I2C initialization failed\n");
774 }
775 else
776 xf86SetDDCproperties(pScrn,xf86PrintEDID(
777 xf86DoEDID_DDC2(XF86_SCRN_ARG(pScrn),pCir->I2CPtr1)));
778
779 #ifdef XSERVER_LIBPCIACCESS
780 #ifndef PCI_CHIP_QEMU
781 #define PCI_CHIP_QEMU 0x1af4
782 #endif
783 if (!pScrn->monitor->DDC &&
784 ((pCir->PciInfo->subvendor_id & 0xffff) == PCI_CHIP_QEMU)) {
785 pCir->NoAccel = TRUE;
786 }
787 #endif
788
789 /* Probe the possible LCD display */
790 AlpProbeLCD(pScrn);
791
792 #ifdef CIRPROBEI2C
793 CirProbeI2C(pScrn->scrnIndex);
794 #endif
795
796 /* The gamma fields must be initialised when using the new cmap code */
797 if (pScrn->depth > 1) {
798 Gamma zeros = {0.0, 0.0, 0.0};
799
800 if (!xf86SetGamma(pScrn, zeros))
801 return FALSE;
802 }
803
804 /* XXX If UseMMIO == TRUE and for any reason we cannot do MMIO,
805 abort here */
806
807 if (xf86GetOptValBool(pCir->Options,
808 OPTION_SHADOW_FB,&pCir->shadowFB))
809 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowFB %s.\n",
810 pCir->shadowFB ? "enabled" : "disabled");
811
812 if ((s = xf86GetOptValString(pCir->Options, OPTION_ROTATE))) {
813 if(!xf86NameCmp(s, "CW")) {
814 /* accel is disabled below for shadowFB */
815 pCir->shadowFB = TRUE;
816 pCir->rotate = 1;
817 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
818 "Rotating screen clockwise - acceleration disabled\n");
819 } else if(!xf86NameCmp(s, "CCW")) {
820 pCir->shadowFB = TRUE;
821 pCir->rotate = -1;
822 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rotating screen"
823 "counter clockwise - acceleration disabled\n");
824 } else {
825 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "\"%s\" is not a valid"
826 "value for Option \"Rotate\"\n", s);
827 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
828 "Valid options are \"CW\" or \"CCW\"\n");
829 }
830 }
831 if (pCir->shadowFB && (pScrn->depth < 8)) {
832 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
833 "shadowFB not supported at this depth.\n");
834 pCir->shadowFB = FALSE;
835 pCir->rotate = 0;
836 }
837
838 if (pCir->shadowFB && !pCir->NoAccel) {
839 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
840 "HW acceleration not supported with \"shadowFB\".\n");
841 pCir->NoAccel = TRUE;
842 }
843
844 if (pCir->rotate && pCir->HWCursor) {
845 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
846 "HW cursor not supported with \"rotate\".\n");
847 pCir->HWCursor = FALSE;
848 }
849
850 /* XXX We do not know yet how to configure memory on this card.
851 Use options MemCFG1 and MemCFG2 to set registers SR0F and
852 SR17 before trying to count ram size. */
853
854 pCir->chip.alp->sr0f = (CARD32)-1;
855 pCir->chip.alp->sr17 = (CARD32)-1;
856
857 (void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG1, (unsigned long *)&pCir->chip.alp->sr0f);
858 (void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG2, (unsigned long *)&pCir->chip.alp->sr17);
859 /*
860 * If the user has specified the amount of memory in the XF86Config
861 * file, we respect that setting.
862 */
863 if (pCir->pEnt->device->videoRam != 0) {
864 pScrn->videoRam = pCir->pEnt->device->videoRam;
865 pCir->IoMapSize = 0x4000; /* 16K for moment */
866 from = X_CONFIG;
867 } else {
868 pScrn->videoRam = AlpCountRam(pScrn);
869 from = X_PROBED;
870 }
871 xf86DrvMsg(pScrn->scrnIndex, from, "VideoRAM: %d kByte\n", pScrn->videoRam);
872
873 pCir->FbMapSize = pScrn->videoRam * 1024;
874
875 /* properties */
876 pCir->properties = 0;
877
878 if ((pCir->chip.alp->sr0f & 0x18) > 0x8)
879 pCir->properties |= HWCUR64;
880
881 switch (pCir->Chipset) {
882 case PCI_CHIP_GD7548:
883 pCir->properties |= HWCUR64;
884 pCir->properties |= ACCEL_AUTOSTART;
885 break;
886 case PCI_CHIP_GD5436:
887 case PCI_CHIP_GD5480:
888 pCir->properties |= ACCEL_AUTOSTART;
889 break;
890 default:
891 break;
892 }
893
894 /* We use a programmable clock */
895 pScrn->progClock = TRUE;
896
897 /* XXX Set HW cursor use */
898
899 /* Set the min pixel clock */
900 pCir->MinClock = 12000; /* XXX Guess, need to check this */
901 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %d MHz\n",
902 pCir->MinClock / 1000);
903 /*
904 * If the user has specified ramdac speed in the XF86Config
905 * file, we respect that setting.
906 */
907 if (pCir->pEnt->device->dacSpeeds[0]) {
908 ErrorF("Do not specily a Clocks line for Cirrus chips\n");
909 return FALSE;
910 } else {
911 int speed;
912 int *p = NULL;
913 switch (pCir->Chipset) {
914 case PCI_CHIP_GD5430:
915 case PCI_CHIP_GD5434_4:
916 case PCI_CHIP_GD5434_8:
917 /* case PCI_CHIP_GD5440: */
918 p = gd5430_MaxClocks;
919 break;
920 case PCI_CHIP_GD5436:
921 case PCI_CHIP_GD5446:
922 p = gd5446_MaxClocks;
923 break;
924 case PCI_CHIP_GD5480:
925 p = gd5480_MaxClocks;
926 break;
927 case PCI_CHIP_GD7548:
928 p = gd7548_MaxClocks;
929 break;
930 case PCI_CHIP_GD7555:
931 p = gd7555_MaxClocks;
932 break;
933 case PCI_CHIP_GD7556:
934 p = gd7556_MaxClocks;
935 break;
936 }
937 if (!p)
938 return FALSE;
939 switch(pScrn->bitsPerPixel) {
940 case 1:
941 case 4:
942 speed = p[0];
943 break;
944 case 8:
945 speed = p[1];
946 break;
947 case 15:
948 case 16:
949 speed = p[2];
950 break;
951 case 24:
952 speed = p[3];
953 break;
954 case 32:
955 speed = p[4];
956 break;
957 default:
958 /* Should not get here */
959 speed = 0;
960 break;
961 }
962 pCir->MaxClock = speed;
963 from = X_PROBED;
964 }
965 xf86DrvMsg(pScrn->scrnIndex, from, "Max pixel clock is %d MHz\n",
966 pCir->MaxClock / 1000);
967
968 /*
969 * Setup the ClockRanges, which describe what clock ranges are available,
970 * and what sort of modes they can be used for.
971 */
972 clockRanges = xnfcalloc(sizeof(ClockRange), 1);
973 clockRanges->next = NULL;
974 clockRanges->minClock = pCir->MinClock;
975 clockRanges->maxClock = pCir->MaxClock;
976 clockRanges->clockIndex = -1; /* programmable */
977 clockRanges->interlaceAllowed = FALSE; /* XXX check this */
978 clockRanges->doubleScanAllowed = FALSE; /* XXX check this */
979 clockRanges->doubleScanAllowed = FALSE; /* XXX check this */
980 clockRanges->doubleScanAllowed = FALSE; /* XXX check this */
981 clockRanges->ClockMulFactor = 1;
982 clockRanges->ClockDivFactor = 1;
983 clockRanges->PrivFlags = 0;
984
985 switch (pCir->Chipset)
986 {
987 case PCI_CHIP_GD7548:
988 pCir->Rounding = 1;
989 break;
990
991 default:
992 pCir->Rounding = 128 >> pCir->BppShift;
993 }
994
995 #if 0
996 if (pCir->Chipset != PCI_CHIP_GD5446 &&
997 pCir->Chipset != PCI_CHIP_GD5480) {
998 /* XXX Kludge */
999 pCir->NoAccel = TRUE;
1000 }
1001 #endif
1002
1003 /*
1004 * xf86ValidateModes will check that the mode HTotal and VTotal values
1005 * don't exceed the chipset's limit if pScrn->maxHValue and
1006 * pScrn->maxVValue are set. Since our AlpValidMode() already takes
1007 * care of this, we don't worry about setting them here.
1008 */
1009
1010 /* Select valid modes from those available */
1011 if (pCir->NoAccel) {
1012 /*
1013 * XXX Assuming min pitch 256, max 2048
1014 * XXX Assuming min height 128, max 2048
1015 */
1016 i = xf86ValidateModes(pScrn, pScrn->monitor->Modes,
1017 pScrn->display->modes, clockRanges,
1018 NULL, 256, 2048,
1019 pCir->Rounding * pScrn->bitsPerPixel, 128, 2048,
1020 pScrn->display->virtualX,
1021 pScrn->display->virtualY,
1022 pCir->FbMapSize,
1023 LOOKUP_BEST_REFRESH);
1024 } else {
1025 /*
1026 * XXX Assuming min height 128, max 2048
1027 */
1028 i = xf86ValidateModes(pScrn, pScrn->monitor->Modes,
1029 pScrn->display->modes, clockRanges,
1030 GetAccelPitchValues(pScrn), 0, 0,
1031 pCir->Rounding * pScrn->bitsPerPixel, 128, 2048,
1032 pScrn->display->virtualX,
1033 pScrn->display->virtualY,
1034 pCir->FbMapSize,
1035 LOOKUP_BEST_REFRESH);
1036 }
1037 if (i == -1) {
1038 AlpFreeRec(pScrn);
1039 return FALSE;
1040 }
1041
1042 /* Prune the modes marked as invalid */
1043 xf86PruneDriverModes(pScrn);
1044
1045 if (i == 0 || pScrn->modes == NULL) {
1046 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n");
1047 AlpFreeRec(pScrn);
1048 return FALSE;
1049 }
1050
1051 /*
1052 * Set the CRTC parameters for all of the modes based on the type
1053 * of mode, and the chipset's interlace requirements.
1054 *
1055 * Calling this is required if the mode->Crtc* values are used by the
1056 * driver and if the driver doesn't provide code to set them. They
1057 * are not pre-initialised at all.
1058 */
1059 xf86SetCrtcForModes(pScrn, INTERLACE_HALVE_V);
1060
1061 /* Set the current mode to the first in the list */
1062 pScrn->currentMode = pScrn->modes;
1063
1064 /* Print the list of modes being used */
1065 xf86PrintModes(pScrn);
1066
1067 /* Set display resolution */
1068 xf86SetDpi(pScrn, 0, 0);
1069
1070 /* Load bpp-specific modules */
1071 switch (pScrn->bitsPerPixel) {
1072 #ifdef HAVE_XF1BPP
1073 case 1:
1074 if (xf86LoadSubModule(pScrn, "xf1bpp") == NULL) {
1075 AlpFreeRec(pScrn);
1076 return FALSE;
1077 }
1078 break;
1079 #endif
1080 #ifdef HAVE_XF4BPP
1081 case 4:
1082 if (xf86LoadSubModule(pScrn, "xf4bpp") == NULL) {
1083 AlpFreeRec(pScrn);
1084 return FALSE;
1085 }
1086 break;
1087 #endif
1088 case 8:
1089 case 16:
1090 case 24:
1091 case 32:
1092 if (xf86LoadSubModule(pScrn, "fb") == NULL) {
1093 AlpFreeRec(pScrn);
1094 return FALSE;
1095 }
1096 break;
1097 }
1098
1099 /* Load XAA if needed */
1100 if (!pCir->NoAccel) {
1101 #ifdef HAVE_XAA_H
1102 if (!xf86LoadSubModule(pScrn, "xaa"))
1103 #else
1104 if (1)
1105 #endif
1106 {
1107 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1108 "Falling back to shadowfb\n");
1109 pCir->NoAccel = TRUE;
1110 pCir->shadowFB = TRUE;
1111 }
1112 }
1113
1114
1115 /* Load ramdac if needed */
1116 if (pCir->HWCursor) {
1117 if (!xf86LoadSubModule(pScrn, "ramdac")) {
1118 AlpFreeRec(pScrn);
1119 return FALSE;
1120 }
1121 }
1122
1123 if (pCir->shadowFB) {
1124 if (!xf86LoadSubModule(pScrn, "shadowfb")) {
1125 AlpFreeRec(pScrn);
1126 return FALSE;
1127 }
1128 }
1129
1130 return TRUE;
1131 }
1132
1133 /*
1134 * This function saves the video state.
1135 */
1136 static void
AlpSave(ScrnInfoPtr pScrn)1137 AlpSave(ScrnInfoPtr pScrn)
1138 {
1139 CirPtr pCir = CIRPTR(pScrn);
1140 vgaHWPtr hwp = VGAHWPTR(pScrn);
1141
1142 #ifdef ALP_DEBUG
1143 ErrorF("AlpSave\n");
1144 #endif
1145 vgaHWSave(pScrn, &VGAHWPTR(pScrn)->SavedReg, VGA_SR_ALL);
1146
1147 pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1148 pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1149 pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1150 pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1151 pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1152 pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1153 pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1154 pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1155 pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1156 pCir->chip.alp->ModeReg.ExtVga[SR21] = pCir->chip.alp->SavedReg.ExtVga[SR21] = hwp->readSeq(hwp, 0x21);
1157 pCir->chip.alp->ModeReg.ExtVga[SR2D] = pCir->chip.alp->SavedReg.ExtVga[SR2D] = hwp->readSeq(hwp, 0x2D);
1158 pCir->chip.alp->ModeReg.ExtVga[GR17] = pCir->chip.alp->SavedReg.ExtVga[GR17] = hwp->readGr(hwp, 0x17);
1159 pCir->chip.alp->ModeReg.ExtVga[GR18] = pCir->chip.alp->SavedReg.ExtVga[GR18] = hwp->readGr(hwp, 0x18);
1160 /* The first 4 reads are for the pixel mask register. After 4 times that
1161 this register is accessed in succession reading/writing this address
1162 accesses the HDR. */
1163 hwp->readDacMask(hwp);
1164 hwp->readDacMask(hwp);
1165 hwp->readDacMask(hwp);
1166 hwp->readDacMask(hwp);
1167 pCir->chip.alp->ModeReg.ExtVga[HDR] = pCir->chip.alp->SavedReg.ExtVga[HDR] = hwp->readDacMask(hwp);
1168 }
1169
1170 /* XXX */
1171 static void
AlpFix1bppColorMap(ScrnInfoPtr pScrn)1172 AlpFix1bppColorMap(ScrnInfoPtr pScrn)
1173 {
1174 vgaHWPtr hwp = VGAHWPTR(pScrn);
1175 /* In 1 bpp we have color 0 at LUT 0 and color 1 at LUT 0x3f.
1176 This makes white and black look right (otherwise they were both
1177 black. I'm sure there's a better way to do that, just lazy to
1178 search the docs. */
1179
1180 hwp->writeDacWriteAddr(hwp, 0x00);
1181 hwp->writeDacData(hwp, 0x00); hwp->writeDacData(hwp, 0x00); hwp->writeDacData(hwp, 0x00);
1182 hwp->writeDacWriteAddr(hwp, 0x3F);
1183 hwp->writeDacData(hwp, 0x3F); hwp->writeDacData(hwp, 0x3F); hwp->writeDacData(hwp, 0x3F);
1184 }
1185
1186 static void
alpRestore(vgaHWPtr hwp,AlpRegPtr cirReg)1187 alpRestore(vgaHWPtr hwp, AlpRegPtr cirReg)
1188 {
1189 hwp->writeCrtc(hwp, 0x1A, cirReg->ExtVga[CR1A]);
1190 hwp->writeCrtc(hwp, 0x1B, cirReg->ExtVga[CR1B]);
1191 hwp->writeCrtc(hwp, 0x1D, cirReg->ExtVga[CR1D]);
1192 hwp->writeSeq(hwp, 0x07, cirReg->ExtVga[SR07]);
1193 hwp->writeSeq(hwp, 0x0E, cirReg->ExtVga[SR0E]);
1194 hwp->writeSeq(hwp, 0x12, cirReg->ExtVga[SR12]);
1195 hwp->writeSeq(hwp, 0x13, cirReg->ExtVga[SR13]);
1196 hwp->writeSeq(hwp, 0x17, cirReg->ExtVga[SR17]);
1197 hwp->writeSeq(hwp, 0x1E, cirReg->ExtVga[SR1E]);
1198 hwp->writeSeq(hwp, 0x21, cirReg->ExtVga[SR21]);
1199 hwp->writeSeq(hwp, 0x2D, cirReg->ExtVga[SR2D]);
1200 hwp->writeGr(hwp, 0x17, cirReg->ExtVga[GR17]);
1201 hwp->writeGr(hwp, 0x18, cirReg->ExtVga[GR18]);
1202 /* The first 4 reads are for the pixel mask register. After 4 times that
1203 this register is accessed in succession reading/writing this address
1204 accesses the HDR. */
1205 hwp->readDacMask(hwp);
1206 hwp->readDacMask(hwp);
1207 hwp->readDacMask(hwp);
1208 hwp->readDacMask(hwp);
1209 hwp->writeDacMask(hwp, cirReg->ExtVga[HDR ]);
1210 }
1211
1212
1213 /*
1214 * Initialise a new mode. This is currently still using the old
1215 * "initialise struct, restore/write struct to HW" model. That could
1216 * be changed.
1217 * Why?? (EE)
1218 */
1219
1220 static Bool
AlpModeInit(ScrnInfoPtr pScrn,DisplayModePtr mode)1221 AlpModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
1222 {
1223 vgaHWPtr hwp;
1224 CirPtr pCir;
1225 int depthcode;
1226 int width;
1227 Bool HDiv2 = FALSE, VDiv2 = FALSE;
1228
1229 #ifdef ALP_DEBUG
1230 ErrorF("AlpModeInit %d bpp, %d %d %d %d %d %d %d %d %d\n",
1231 pScrn->bitsPerPixel,
1232 mode->Clock,
1233 mode->HDisplay,
1234 mode->HSyncStart,
1235 mode->HSyncEnd,
1236 mode->HTotal,
1237 mode->VDisplay,
1238 mode->VSyncStart,
1239 mode->VSyncEnd,
1240 mode->VTotal);
1241
1242 ErrorF("AlpModeInit: depth %d bits\n", pScrn->depth);
1243 #endif
1244
1245 pCir = CIRPTR(pScrn);
1246 hwp = VGAHWPTR(pScrn);
1247 vgaHWUnlock(hwp);
1248
1249 pCir->pitch = pScrn->displayWidth * pScrn->bitsPerPixel >> 3;
1250
1251 depthcode = pScrn->depth;
1252 if (pScrn->bitsPerPixel == 32)
1253 depthcode = 32;
1254
1255 if ((pCir->Chipset == PCI_CHIP_GD5480 && mode->Clock > 135100) ||
1256 (pCir->Chipset == PCI_CHIP_GD5446 && mode->Clock > 85500)) {
1257 /* The actual DAC register value is set later. */
1258 /* The CRTC is clocked at VCLK / 2, so we must half the */
1259 /* horizontal timings. */
1260 if (!mode->CrtcHAdjusted) {
1261 mode->CrtcHDisplay >>= 1;
1262 mode->CrtcHSyncStart >>= 1;
1263 mode->CrtcHTotal >>= 1;
1264 mode->CrtcHSyncEnd >>= 1;
1265 mode->SynthClock >>= 1;
1266 mode->CrtcHAdjusted = TRUE;
1267 }
1268 depthcode += 64;
1269 HDiv2 = TRUE;
1270 }
1271
1272 if (mode->VTotal >= 1024 && !(mode->Flags & V_INTERLACE)) {
1273 /* For non-interlaced vertical timing >= 1024, the vertical timings */
1274 /* are divided by 2 and VGA CRTC 0x17 bit 2 is set. */
1275 if (!mode->CrtcVAdjusted) {
1276 mode->CrtcVDisplay >>= 1;
1277 mode->CrtcVSyncStart >>= 1;
1278 mode->CrtcVSyncEnd >>= 1;
1279 mode->CrtcVTotal >>= 1;
1280 mode->CrtcVAdjusted = TRUE;
1281 }
1282 VDiv2 = TRUE;
1283 }
1284
1285 /* Initialise the ModeReg values */
1286 if (!vgaHWInit(pScrn, mode))
1287 return FALSE;
1288 pScrn->vtSema = TRUE;
1289
1290 /* Turn off HW cursor, gamma correction, overscan color protect. */
1291 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1292 if ((pCir->properties & HWCUR64) == HWCUR64)
1293 {
1294 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0x4;
1295 switch (pCir->Chipset)
1296 {
1297 case PCI_CHIP_GD7548:
1298 pCir->chip.alp->ModeReg.ExtVga[SR21] |= 0x10;
1299 break;
1300 }
1301
1302 }
1303 else
1304 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1305
1306
1307 if(VDiv2)
1308 hwp->ModeReg.CRTC[0x17] |= 0x04;
1309
1310 #ifdef ALP_DEBUG
1311 ErrorF("SynthClock = %d\n", mode->SynthClock);
1312 #endif
1313
1314 /* Disable DCLK pin driver, interrupts. */
1315 pCir->chip.alp->ModeReg.ExtVga[GR17] |= 0x08;
1316 pCir->chip.alp->ModeReg.ExtVga[GR17] &= ~0x04;
1317
1318 pCir->chip.alp->ModeReg.ExtVga[HDR] = 0;
1319 /* Enable linear mode and high-res packed pixel mode */
1320 pCir->chip.alp->ModeReg.ExtVga[SR07] &= 0xe0;
1321 #ifdef ALP_DEBUG
1322 ErrorF("depthcode = %d\n", depthcode);
1323 #endif
1324
1325 if (pScrn->bitsPerPixel == 1) {
1326 hwp->IOBase = 0x3B0;
1327 hwp->ModeReg.MiscOutReg &= ~0x01;
1328 } else {
1329 hwp->IOBase = 0x3D0;
1330 hwp->ModeReg.MiscOutReg |= 0x01;
1331 }
1332
1333 switch (depthcode) {
1334 case 1:
1335 case 4:
1336 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x10;
1337 break;
1338 case 8:
1339 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x11;
1340 break;
1341 case 64+8:
1342 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1343 break;
1344 case 15:
1345 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1346 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC0;
1347 break;
1348 case 64+15:
1349 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1350 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC0;
1351 break;
1352 case 16:
1353 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1354 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC1;
1355 break;
1356 case 64+16:
1357 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1358 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC1;
1359 break;
1360 case 24:
1361 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x15;
1362 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC5;
1363 break;
1364 case 32:
1365 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1366 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC5;
1367 break;
1368 default:
1369 ErrorF("X11: Internal error: AlpModeInit: Cannot Initialize display to requested mode\n");
1370 #ifdef ALP_DEBUG
1371 ErrorF("AlpModeInit returning FALSE on depthcode %d\n", depthcode);
1372 #endif
1373 return FALSE;
1374 }
1375 if (HDiv2)
1376 pCir->chip.alp->ModeReg.ExtVga[GR18] |= 0x20;
1377 else
1378 pCir->chip.alp->ModeReg.ExtVga[GR18] &= ~0x20;
1379
1380
1381 /* Some extra init stuff */
1382 switch (pCir->Chipset)
1383 {
1384 case PCI_CHIP_GD7548:
1385 /* Do we use MMIO ?
1386 If we do and we are on a 7548, we need to tell the board
1387 that we want MMIO. */
1388 if (pCir->UseMMIO)
1389 {
1390 pCir->chip.alp->ModeReg.ExtVga[SR17] =
1391 (pCir->chip.alp->ModeReg.ExtVga[SR17] & ~0x40) | 4;
1392 ErrorF("UseMMIO: SR17=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1393 }
1394 #ifdef ALP_SETUP
1395 ErrorF("SR2D=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1396 #endif
1397 pCir->chip.alp->ModeReg.ExtVga[SR2D] |= 0xC0;
1398 break;
1399 }
1400
1401 /* No support for interlace (yet) */
1402 pCir->chip.alp->ModeReg.ExtVga[CR1A] = 0x00;
1403
1404 width = pScrn->displayWidth * pScrn->bitsPerPixel / 8;
1405 if (pScrn->bitsPerPixel == 1)
1406 width <<= 2;
1407 hwp->ModeReg.CRTC[0x13] = width >> 3;
1408 /* Offset extension (see CR13) */
1409 pCir->chip.alp->ModeReg.ExtVga[CR1B] &= 0xAF;
1410 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+4)) & 0x10;
1411 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+3)) & 0x40;
1412 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= 0x22;
1413
1414 /* Programme the registers */
1415 vgaHWProtect(pScrn, TRUE);
1416 hwp->writeMiscOut(hwp, hwp->ModeReg.MiscOutReg);
1417 alpRestore(hwp,&pCir->chip.alp->ModeReg);
1418 AlpSetClock(pCir, hwp, mode->SynthClock);
1419
1420 vgaHWRestore(pScrn, &hwp->ModeReg, VGA_SR_MODE | VGA_SR_CMAP);
1421
1422 /* XXX */
1423 if (pScrn->bitsPerPixel == 1)
1424 AlpFix1bppColorMap(pScrn);
1425
1426 vgaHWProtect(pScrn, FALSE);
1427
1428 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
1429 if (xf86IsPc98())
1430 PC98CIRRUS755xEnable(pScrn);
1431 #endif
1432
1433 return TRUE;
1434 }
1435
1436 /*
1437 * Restore the initial (text) mode.
1438 */
1439 static void
AlpRestore(ScrnInfoPtr pScrn)1440 AlpRestore(ScrnInfoPtr pScrn)
1441 {
1442 vgaHWPtr hwp;
1443 vgaRegPtr vgaReg;
1444 CirPtr pCir;
1445 AlpRegPtr alpReg;
1446
1447 #ifdef ALP_DEBUG
1448 ErrorF("AlpRestore\n");
1449 #endif
1450
1451 hwp = VGAHWPTR(pScrn);
1452 pCir = CIRPTR(pScrn);
1453 vgaReg = &hwp->SavedReg;
1454 alpReg = &pCir->chip.alp->SavedReg;
1455
1456 vgaHWProtect(pScrn, TRUE);
1457
1458 alpRestore(hwp,alpReg);
1459
1460 vgaHWRestore(pScrn, vgaReg, VGA_SR_ALL);
1461 vgaHWProtect(pScrn, FALSE);
1462 }
1463
1464 /* Mandatory */
1465
1466 /* This gets called at the start of each server generation */
1467
1468 Bool
AlpScreenInit(SCREEN_INIT_ARGS_DECL)1469 AlpScreenInit(SCREEN_INIT_ARGS_DECL)
1470 {
1471 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1472 vgaHWPtr hwp;
1473 CirPtr pCir;
1474 int i, ret;
1475 int init_picture = 0;
1476 VisualPtr visual;
1477 int displayWidth,width,height;
1478 unsigned char * FbBase = NULL;
1479 int cursor_size = 0;
1480
1481 #ifdef ALP_DEBUG
1482 ErrorF("AlpScreenInit\n");
1483 #endif
1484
1485 hwp = VGAHWPTR(pScrn);
1486 pCir = CIRPTR(pScrn);
1487
1488 /* Map the VGA memory when the primary video */
1489 if (!vgaHWMapMem(pScrn))
1490 return FALSE;
1491
1492 /* Map the Alp memory and MMIO areas */
1493 if (!CirMapMem(pCir, pScrn->scrnIndex))
1494 return FALSE;
1495
1496 /* The 754x supports MMIO for the BitBlt engine but
1497 not for the VGA registers */
1498 switch (pCir->Chipset)
1499 {
1500 case PCI_CHIP_GD7548:
1501 break;
1502 default:
1503 if(pCir->UseMMIO)
1504 vgaHWSetMmioFuncs(hwp, pCir->IOBase, -0x3C0);
1505 }
1506
1507 vgaHWGetIOBase(hwp);
1508
1509 /* Save the current state */
1510 AlpSave(pScrn);
1511
1512 /* Initialise the first mode */
1513 if (!AlpModeInit(pScrn, pScrn->currentMode))
1514 return FALSE;
1515
1516 /* Make things beautiful */
1517 AlpSaveScreen(pScreen, SCREEN_SAVER_ON);
1518
1519 /* Set the viewport */
1520 AlpAdjustFrame(ADJUST_FRAME_ARGS(pScrn, pScrn->frameX0, pScrn->frameY0));
1521
1522 /*
1523 * The next step is to setup the screen's visuals, and initialise the
1524 * framebuffer code. In cases where the framebuffer's default
1525 * choices for things like visual layouts and bits per RGB are OK,
1526 * this may be as simple as calling the framebuffer's ScreenInit()
1527 * function. If not, the visuals will need to be setup before calling
1528 * a fb ScreenInit() function and fixed up after.
1529 *
1530 */
1531
1532 /*
1533 * Reset the visual list.
1534 */
1535 miClearVisualTypes();
1536
1537 /* Setup the visuals we support. */
1538
1539 if (!miSetVisualTypes(pScrn->depth,
1540 miGetDefaultVisualMask(pScrn->depth),
1541 pScrn->rgbBits, pScrn->defaultVisual))
1542 return FALSE;
1543
1544 miSetPixmapDepths ();
1545
1546 displayWidth = pScrn->displayWidth;
1547 if (pCir->rotate) {
1548 height = pScrn->virtualX;
1549 width = pScrn->virtualY;
1550 } else {
1551 width = pScrn->virtualX;
1552 height = pScrn->virtualY;
1553 }
1554
1555 if(pCir->shadowFB) {
1556 pCir->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
1557 pCir->ShadowPtr = malloc(pCir->ShadowPitch * height);
1558 displayWidth = pCir->ShadowPitch / (pScrn->bitsPerPixel >> 3);
1559 FbBase = pCir->ShadowPtr;
1560 } else {
1561 pCir->ShadowPtr = NULL;
1562 FbBase = pCir->FbBase;
1563 }
1564
1565 /*
1566 * Call the framebuffer layer's ScreenInit function, and fill in other
1567 * pScreen fields.
1568 */
1569
1570 switch (pScrn->bitsPerPixel) {
1571 #ifdef HAVE_XF1BPP
1572 case 1:
1573 ret = xf1bppScreenInit(pScreen, FbBase,
1574 width, height,
1575 pScrn->xDpi, pScrn->yDpi,
1576 displayWidth);
1577 break;
1578 #endif
1579 #ifdef HAVE_XF4BPP
1580 case 4:
1581 ret = xf4bppScreenInit(pScreen, FbBase,
1582 width, height,
1583 pScrn->xDpi, pScrn->yDpi,
1584 displayWidth);
1585 break;
1586 #endif
1587 case 8:
1588 case 16:
1589 case 24:
1590 case 32:
1591 ret = fbScreenInit(pScreen, FbBase,
1592 width,height,
1593 pScrn->xDpi, pScrn->yDpi,
1594 displayWidth,pScrn->bitsPerPixel);
1595 init_picture = 1;
1596 break;
1597 default:
1598 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1599 "X11: Internal error: invalid bpp (%d) in AlpScreenInit\n",
1600 pScrn->bitsPerPixel);
1601 ret = FALSE;
1602 break;
1603 }
1604 if (!ret)
1605 return FALSE;
1606
1607 #ifdef ALP_DEBUG
1608 ErrorF("AlpScreenInit after depth dependent init\n");
1609 #endif
1610
1611 /* Override the default mask/offset settings */
1612 if (pScrn->bitsPerPixel > 8) {
1613 for (i = 0; i < pScreen->numVisuals; i++) {
1614 visual = &pScreen->visuals[i];
1615 if ((visual->class | DynamicClass) == DirectColor) {
1616 visual->offsetRed = pScrn->offset.red;
1617 visual->offsetGreen = pScrn->offset.green;
1618 visual->offsetBlue = pScrn->offset.blue;
1619 visual->redMask = pScrn->mask.red;
1620 visual->greenMask = pScrn->mask.green;
1621 visual->blueMask = pScrn->mask.blue;
1622 }
1623 }
1624 }
1625
1626 /* must be after RGB ordering fixed */
1627 if (init_picture)
1628 fbPictureInit (pScreen, 0, 0);
1629
1630 /*
1631 * Set initial black & white colourmap indices.
1632 */
1633 xf86SetBlackWhitePixels(pScreen);
1634
1635 /*
1636 Allocation of off-screen memory to various stuff
1637 (hardware cursor, 8x8 mono pattern...)
1638 Allocation goes top-down in memory, since the cursor
1639 *must* be in the last videoram locations
1640 */
1641 pCir->offscreen_offset = pScrn->videoRam*1024;
1642 pCir->offscreen_size = pScrn->videoRam * 1024 - pScrn->virtualY *
1643 (BitmapBytePad(pScrn->displayWidth * pScrn->bitsPerPixel));
1644
1645 #ifdef ALP_DEBUG
1646 ErrorF("offscreen_offset=%d, offscreen_size=%d\n",
1647 pCir->offscreen_offset, pCir->offscreen_size);
1648 #endif
1649
1650 /* Initialise cursor functions */
1651 if (pCir->HWCursor) { /* Initialize HW cursor layer */
1652
1653 if ((pCir->properties & HWCUR64)
1654 && (pCir->offscreen_size >= 64*8*2)) {
1655 cursor_size = 64;
1656 pCir->offscreen_size -= 64*8*2;
1657 pCir->offscreen_offset -= 64*8*2;
1658 } else if (pCir->offscreen_size >= 32*4*2) {
1659 cursor_size = 32;
1660 pCir->offscreen_size -= 32*8*2;
1661 pCir->offscreen_offset -= 32*8*2;
1662 }
1663 }
1664
1665 if (!pCir->NoAccel) { /* Initialize XAA functions */
1666 AlpOffscreenAccelInit(pScrn);
1667 #ifdef HAVE_XAA_H
1668 if (!(pCir->UseMMIO ? AlpXAAInitMMIO(pScreen) :
1669 AlpXAAInit(pScreen)))
1670 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1671 "Could not initialize XAA\n");
1672 #endif
1673 }
1674
1675 #if 1
1676 pCir->DGAModeInit = AlpModeInit;
1677 if (!CirDGAInit(pScreen))
1678 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1679 "DGA initialization failed\n");
1680 #endif
1681 xf86SetSilkenMouse(pScreen);
1682
1683 /* Initialise cursor functions */
1684 miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
1685
1686 if (pCir->HWCursor) {
1687 if (!AlpHWCursorInit(pScreen, cursor_size))
1688 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1689 "Hardware cursor initialization failed\n");
1690 #ifdef ALP_DEBUG
1691 ErrorF("AlpHWCursorInit() complete\n");
1692 #endif
1693 }
1694
1695 if (pCir->shadowFB) {
1696 RefreshAreaFuncPtr refreshArea = cirRefreshArea;
1697
1698 if(pCir->rotate) {
1699 if (!pCir->PointerMoved) {
1700 pCir->PointerMoved = pScrn->PointerMoved;
1701 pScrn->PointerMoved = cirPointerMoved;
1702 }
1703
1704 switch(pScrn->bitsPerPixel) {
1705 case 8: refreshArea = cirRefreshArea8; break;
1706 case 16: refreshArea = cirRefreshArea16; break;
1707 case 24: refreshArea = cirRefreshArea24; break;
1708 case 32: refreshArea = cirRefreshArea32; break;
1709 }
1710 }
1711
1712 ShadowFBInit(pScreen, refreshArea);
1713 }
1714
1715 /* Initialise default colourmap */
1716 if (!miCreateDefColormap(pScreen))
1717 return FALSE;
1718
1719 if (pScrn->bitsPerPixel > 1 && pScrn->bitsPerPixel <= 8)
1720 vgaHWHandleColormaps(pScreen);
1721
1722 xf86DPMSInit(pScreen, AlpDisplayPowerManagementSet, 0);
1723
1724 pScrn->memPhysBase = pCir->FbAddress;
1725 pScrn->fbOffset = 0;
1726
1727 {
1728 XF86VideoAdaptorPtr *ptr;
1729 int n;
1730
1731 n = xf86XVListGenericAdaptors(pScrn,&ptr);
1732 if (n)
1733 xf86XVScreenInit(pScreen, ptr, n);
1734 }
1735
1736 /*
1737 * Wrap the CloseScreen vector and set SaveScreen.
1738 */
1739 pScreen->SaveScreen = AlpSaveScreen;
1740 pCir->CloseScreen = pScreen->CloseScreen;
1741 pScreen->CloseScreen = AlpCloseScreen;
1742
1743 /* Report any unused options (only for the first generation) */
1744 if (serverGeneration == 1)
1745 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
1746
1747 /* Done */
1748 return TRUE;
1749 }
1750
1751
1752 /* Usually mandatory */
1753 Bool
AlpSwitchMode(SWITCH_MODE_ARGS_DECL)1754 AlpSwitchMode(SWITCH_MODE_ARGS_DECL)
1755 {
1756 SCRN_INFO_PTR(arg);
1757 return AlpModeInit(pScrn, mode);
1758 }
1759
1760
1761 /*
1762 * This function is used to initialize the Start Address - the first
1763 * displayed location in the video memory.
1764 */
1765 /* Usually mandatory */
1766 void
AlpAdjustFrame(ADJUST_FRAME_ARGS_DECL)1767 AlpAdjustFrame(ADJUST_FRAME_ARGS_DECL)
1768 {
1769 SCRN_INFO_PTR(arg);
1770 int Base, tmp;
1771 vgaHWPtr hwp;
1772
1773 hwp = VGAHWPTR(pScrn);
1774
1775 Base = ((y * pScrn->displayWidth + x) / 8);
1776 if (pScrn->bitsPerPixel != 1)
1777 Base *= (pScrn->bitsPerPixel/4);
1778
1779 #ifdef ALP_DEBUG
1780 ErrorF("AlpAdjustFrame %d %d 0x%x %d %x\n", x, y, flags, Base, Base);
1781 #endif
1782
1783 if ((Base & ~0x000FFFFF) != 0) {
1784 ErrorF("X11: Internal error: AlpAdjustFrame: cannot handle overflow\n");
1785 return;
1786 }
1787
1788 hwp->writeCrtc(hwp, 0x0C, (Base >> 8) & 0xff);
1789 hwp->writeCrtc(hwp, 0x0D, Base & 0xff);
1790 tmp = hwp->readCrtc(hwp, 0x1B);
1791 tmp &= 0xF2;
1792 tmp |= (Base >> 16) & 0x01;
1793 tmp |= (Base >> 15) & 0x0C;
1794 hwp->writeCrtc(hwp, 0x1B, tmp);
1795 tmp = hwp->readCrtc(hwp, 0x1D);
1796 tmp &= 0x7F;
1797 tmp |= (Base >> 12) & 0x80;
1798 hwp->writeCrtc(hwp, 0x1D, tmp);
1799 }
1800
1801 /*
1802 * This is called when VT switching back to the X server. Its job is
1803 * to reinitialise the video mode.
1804 *
1805 * We may wish to unmap video/MMIO memory too.
1806 */
1807
1808 /* Mandatory */
1809 Bool
AlpEnterVT(VT_FUNC_ARGS_DECL)1810 AlpEnterVT(VT_FUNC_ARGS_DECL)
1811 {
1812 SCRN_INFO_PTR(arg);
1813 CirPtr pCir = CIRPTR(pScrn);
1814 Bool ret;
1815
1816 #ifdef ALP_DEBUG
1817 ErrorF("AlpEnterVT\n");
1818 #endif
1819
1820 /* Should we re-save the text mode on each VT enter? */
1821 if (!(ret = AlpModeInit(pScrn, pScrn->currentMode)))
1822 return FALSE;
1823
1824 if (!pCir->NoAccel)
1825 pCir->InitAccel(pScrn);
1826
1827 return ret;
1828 }
1829
1830
1831 /*
1832 * This is called when VT switching away from the X server. Its job is
1833 * to restore the previous (text) mode.
1834 *
1835 * We may wish to remap video/MMIO memory too.
1836 */
1837
1838 /* Mandatory */
1839 void
AlpLeaveVT(VT_FUNC_ARGS_DECL)1840 AlpLeaveVT(VT_FUNC_ARGS_DECL)
1841 {
1842 SCRN_INFO_PTR(arg);
1843 vgaHWPtr hwp = VGAHWPTR(pScrn);
1844 #ifdef ALP_DEBUG
1845 ErrorF("AlpLeaveVT\n");
1846 #endif
1847
1848 AlpRestore(pScrn);
1849 vgaHWLock(hwp);
1850
1851 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
1852 if (xf86IsPc98())
1853 PC98CIRRUS755xDisable(pScrn);
1854 #endif
1855 }
1856
1857
1858 /*
1859 * This is called at the end of each server generation. It restores the
1860 * original (text) mode. It should also unmap the video memory, and free
1861 * any per-generation data allocated by the driver. It should finish
1862 * by unwrapping and calling the saved CloseScreen function.
1863 */
1864
1865 /* Mandatory */
1866 static Bool
AlpCloseScreen(CLOSE_SCREEN_ARGS_DECL)1867 AlpCloseScreen(CLOSE_SCREEN_ARGS_DECL)
1868 {
1869 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1870 vgaHWPtr hwp = VGAHWPTR(pScrn);
1871 CirPtr pCir = CIRPTR(pScrn);
1872
1873 if(pScrn->vtSema) {
1874 AlpRestore(pScrn);
1875 vgaHWLock(hwp);
1876 CirUnmapMem(pCir, pScrn->scrnIndex);
1877 }
1878
1879 #ifdef HAVE_XAA_H
1880 if (pCir->AccelInfoRec)
1881 XAADestroyInfoRec(pCir->AccelInfoRec);
1882 pCir->AccelInfoRec = NULL;
1883 #endif
1884 if (pCir->CursorInfoRec)
1885 xf86DestroyCursorInfoRec(pCir->CursorInfoRec);
1886 pCir->CursorInfoRec = NULL;
1887 if (pCir->DGAModes)
1888 free(pCir->DGAModes);
1889 pCir->DGAnumModes = 0;
1890 pCir->DGAModes = NULL;
1891
1892 pScrn->vtSema = FALSE;
1893
1894 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
1895 if (xf86IsPc98())
1896 PC98CIRRUS755xDisable(pScrn);
1897 #endif
1898
1899 pScreen->CloseScreen = pCir->CloseScreen;
1900 return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS);
1901 }
1902
1903
1904 /* Free up any persistent data structures */
1905
1906 /* Optional */
1907 void
AlpFreeScreen(FREE_SCREEN_ARGS_DECL)1908 AlpFreeScreen(FREE_SCREEN_ARGS_DECL)
1909 {
1910 SCRN_INFO_PTR(arg);
1911 #ifdef ALP_DEBUG
1912 ErrorF("AlpFreeScreen\n");
1913 #endif
1914 /*
1915 * This only gets called when a screen is being deleted. It does not
1916 * get called routinely at the end of a server generation.
1917 */
1918 if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
1919 vgaHWFreeHWRec(pScrn);
1920 AlpFreeRec(pScrn);
1921 }
1922
1923
1924 /* Checks if a mode is suitable for the selected chipset. */
1925
1926 /* Optional */
1927 ModeStatus
AlpValidMode(SCRN_ARG_TYPE arg,DisplayModePtr mode,Bool verbose,int flags)1928 AlpValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, Bool verbose, int flags)
1929 {
1930 int lace;
1931
1932 lace = 1 + ((mode->Flags & V_INTERLACE) != 0);
1933
1934 if ((mode->CrtcHDisplay <= 2048) &&
1935 (mode->CrtcHSyncStart <= 4096) &&
1936 (mode->CrtcHSyncEnd <= 4096) &&
1937 (mode->CrtcHTotal <= 4096) &&
1938 (mode->CrtcVDisplay <= 2048 * lace) &&
1939 (mode->CrtcVSyncStart <= 4096 * lace) &&
1940 (mode->CrtcVSyncEnd <= 4096 * lace) &&
1941 (mode->CrtcVTotal <= 4096 * lace)) {
1942 return(MODE_OK);
1943 } else {
1944 return(MODE_BAD);
1945 }
1946 }
1947
1948 /* Do screen blanking */
1949
1950 /* Mandatory */
1951 static Bool
AlpSaveScreen(ScreenPtr pScreen,int mode)1952 AlpSaveScreen(ScreenPtr pScreen, int mode)
1953 {
1954 return vgaHWSaveScreen(pScreen, mode);
1955 }
1956
1957 /*
1958 * Set the clock to the requested frequency. If the MCLK is very close
1959 * to the requested frequency, it sets a flag so that the MCLK can be used
1960 * as VCLK. However this flag is not yet acted upon.
1961 */
1962 static void
AlpSetClock(CirPtr pCir,vgaHWPtr hwp,int freq)1963 AlpSetClock(CirPtr pCir, vgaHWPtr hwp, int freq)
1964 {
1965 int num, den, ffreq;
1966 CARD8 tmp;
1967
1968 #ifdef ALP_DEBUG
1969 ErrorF("AlpSetClock freq=%d.%03dMHz\n", freq / 1000, freq % 1000);
1970 #endif
1971
1972 ffreq = freq;
1973 if (!CirrusFindClock(&ffreq, pCir->MaxClock, &num, &den))
1974 return;
1975
1976 #ifdef ALP_DEBUG
1977 ErrorF("AlpSetClock: nom=%x den=%x ffreq=%d.%03dMHz\n",
1978 num, den, ffreq / 1000, ffreq % 1000);
1979 #endif
1980 /* So - how do we use MCLK here for the VCLK ? */
1981
1982 /* Set VCLK3. */
1983 tmp = hwp->readSeq(hwp, 0x0E);
1984 hwp->writeSeq(hwp, 0x0E, (tmp & 0x80) | num);
1985 hwp->writeSeq(hwp, 0x1E, den);
1986 }
1987
1988 /*
1989 * AlpDisplayPowerManagementSet --
1990 *
1991 * Sets VESA Display Power Management Signaling (DPMS) Mode.
1992 */
1993 static void
AlpDisplayPowerManagementSet(ScrnInfoPtr pScrn,int PowerManagementMode,int flags)1994 AlpDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
1995 int flags)
1996 {
1997 unsigned char sr01, gr0e;
1998 vgaHWPtr hwp;
1999
2000 #ifdef ALP_DEBUG
2001 ErrorF("AlpDisplayPowerManagementSet\n");
2002 #endif
2003
2004 hwp = VGAHWPTR(pScrn);
2005
2006 #ifdef ALP_DEBUG
2007 ErrorF("AlpDisplayPowerManagementSet: %d\n", PowerManagementMode);
2008 #endif
2009
2010 switch (PowerManagementMode) {
2011 case DPMSModeOn:
2012 /* Screen: On; HSync: On, VSync: On */
2013 sr01 = 0x00;
2014 gr0e = 0x00;
2015 break;
2016 case DPMSModeStandby:
2017 /* Screen: Off; HSync: Off, VSync: On */
2018 sr01 = 0x20;
2019 gr0e = 0x02;
2020 break;
2021 case DPMSModeSuspend:
2022 /* Screen: Off; HSync: On, VSync: Off */
2023 sr01 = 0x20;
2024 gr0e = 0x04;
2025 break;
2026 case DPMSModeOff:
2027 /* Screen: Off; HSync: Off, VSync: Off */
2028 sr01 = 0x20;
2029 gr0e = 0x06;
2030 break;
2031 default:
2032 return;
2033 }
2034
2035 sr01 |= hwp->readSeq(hwp, 0x01) & ~0x20;
2036 hwp->writeSeq(hwp, 0x01, sr01);
2037 gr0e |= hwp->readGr(hwp, 0x0E) & ~0x06;
2038 hwp->writeGr(hwp, 0x0E, gr0e);
2039 }
2040
2041 #ifdef ALPPROBEI2C
AlpProbeI2C(int scrnIndex)2042 static void AlpProbeI2C(int scrnIndex)
2043 {
2044 int i;
2045 I2CBusPtr b;
2046
2047 b = xf86I2CFindBus(scrnIndex, "I2C bus 1");
2048 if (b == NULL)
2049 ErrorF("Could not find I2C bus \"%s\"\n", "I2C bus 1");
2050 else {
2051 for (i = 2; i < 256; i += 2)
2052 if (xf86I2CProbeAddress(b, i))
2053 ErrorF("Found device 0x%02x on bus \"%s\"\n", i, b->BusName);
2054 }
2055 b = xf86I2CFindBus(scrnIndex, "I2C bus 2");
2056 if (b == NULL)
2057 ErrorF("Could not find I2C bus \"%s\"\n", "I2C bus 2");
2058 else {
2059 for (i = 2; i < 256; i += 2)
2060 if (xf86I2CProbeAddress(b, i))
2061 ErrorF("Found device 0x%02x on bus \"%s\"\n", i, b->BusName);
2062 }
2063 }
2064 #endif
2065
2066 static void
AlpProbeLCD(ScrnInfoPtr pScrn)2067 AlpProbeLCD(ScrnInfoPtr pScrn)
2068 {
2069 CirPtr pCir = CIRPTR(pScrn);
2070 AlpPtr pAlp = ALPPTR(pCir);
2071
2072 vgaHWPtr hwp = VGAHWPTR(pScrn);
2073 CARD8 lcdCrtl;
2074
2075 static const char* lcd_type_names[] =
2076 {
2077 "none",
2078 "dual-scan monochrome",
2079 "unknown",
2080 "DSTN (dual scan color)",
2081 "TFT (active matrix)"
2082 };
2083
2084
2085 pAlp->lcdType = LCD_NONE;
2086
2087 switch (pCir->Chipset) {
2088 case PCI_CHIP_GD7548:
2089 switch (hwp->readCrtc(hwp, 0x2C) >> 6) {
2090 case 0: pAlp->lcdType = LCD_DUAL_MONO; break;
2091 case 1: pAlp->lcdType = LCD_UNKNOWN; break;
2092 case 2: pAlp->lcdType = LCD_DSTN; break;
2093 case 3: pAlp->lcdType = LCD_TFT; break;
2094 }
2095
2096 /* Enable LCD control registers instead of normal CRTC registers */
2097 lcdCrtl = hwp->readCrtc(hwp, 0x2D);
2098 hwp->writeCrtc(hwp, 0x2D, lcdCrtl | 0x80);
2099
2100 switch ((hwp->readCrtc(hwp, 0x9) >> 2) & 3) {
2101 case 0:
2102 pAlp->lcdWidth = 640;
2103 pAlp->lcdHeight = 480;
2104 break;
2105
2106 case 1:
2107 pAlp->lcdWidth = 800;
2108 pAlp->lcdHeight = 600;
2109 break;
2110
2111 case 2:
2112 pAlp->lcdWidth = 1024;
2113 pAlp->lcdHeight = 768;
2114 break;
2115
2116 case 3:
2117 pAlp->lcdWidth = 0;
2118 pAlp->lcdHeight = 0;
2119 break;
2120 }
2121
2122 /* Disable LCD control registers */
2123 hwp->writeCrtc(hwp, 0x2D, lcdCrtl);
2124 break;
2125 }
2126
2127 if (pAlp->lcdType != LCD_NONE) {
2128 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
2129 "LCD display: %dx%d %s\n",
2130 pAlp->lcdWidth, pAlp->lcdHeight,
2131 lcd_type_names[pAlp->lcdType]);
2132 }
2133 }
2134
2135 static void
AlpOffscreenAccelInit(ScrnInfoPtr pScrn)2136 AlpOffscreenAccelInit(ScrnInfoPtr pScrn)
2137 {
2138 CirPtr pCir = CIRPTR(pScrn);
2139 AlpPtr pAlp = ALPPTR(pCir);
2140
2141 if (pCir->offscreen_size >= 8 && pCir->Chipset == PCI_CHIP_GD7548) {
2142 pCir->offscreen_offset -= 8;
2143 pCir->offscreen_size -= 8;
2144 pAlp->monoPattern8x8 = pCir->offscreen_offset;
2145 #ifdef ALP_DEBUG
2146 ErrorF("monoPattern8x8=%d\n", pAlp->monoPattern8x8);
2147 #endif
2148 } else pAlp->monoPattern8x8 = 0;
2149
2150 {
2151 /* TODO: probably not correct if rotated */
2152 BoxRec box;
2153 box.x1=0;
2154 box.y1=0;
2155 box.x2=pScrn->virtualX;
2156 box.y2= pCir->offscreen_offset / pCir->pitch;
2157 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2158 "Using %d lines for offscreen memory\n",
2159 box.y2 - pScrn->virtualY);
2160 }
2161 }
2162
2163 #if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 12
2164 static void
PC98CIRRUS755xEnable(ScrnInfoPtr pScrn)2165 PC98CIRRUS755xEnable(ScrnInfoPtr pScrn) /* enter_aile() */
2166 {
2167 unsigned int index,data;
2168 vgaHWPtr hwp = VGAHWPTR(pScrn);
2169
2170 outb(0xfac, 0x02);
2171
2172 outb(0x68, 0x0e);
2173 outb(0x6a, 0x07);
2174 outb(0x6a, 0x8f);
2175 outb(0x6a, 0x06);
2176
2177 outw(VGA_SEQ_INDEX, 0x1206); /* unlock cirrus special */
2178
2179 index = hwp->IOBase + VGA_CRTC_INDEX_OFFSET;
2180 data = hwp->IOBase + VGA_CRTC_DATA_OFFSET;
2181 outb(index, 0x3c);
2182 outb(data, inb(data) & 0xef);
2183 outb(index, 0x1a);
2184 outb(data, inb(data) & 0xf3);
2185 }
2186
2187 static void
PC98CIRRUS755xDisable(ScrnInfoPtr pScrn)2188 PC98CIRRUS755xDisable(ScrnInfoPtr pScrn) /* leave_aile() */
2189 {
2190 unsigned int index,data;
2191 vgaHWPtr hwp = VGAHWPTR(pScrn);
2192
2193 outw(VGA_SEQ_INDEX, 0x1206); /* unlock cirrus special */
2194
2195 index = hwp->IOBase + VGA_CRTC_INDEX_OFFSET;
2196 data = hwp->IOBase + VGA_CRTC_DATA_OFFSET;
2197 outb(index, 0x3c);
2198 outb(data, 0x71);
2199 outb(index, 0x1a);
2200 outb(data, inb(data) | 0x0c);
2201
2202 outb(0xfac,0x00);
2203
2204 outb(0x68, 0x0f);
2205 outb(0x6a, 0x07);
2206 outb(0x6a, 0x8e);
2207 outb(0x6a, 0x21);
2208 outb(0x6a, 0x69);
2209 outb(0x6a, 0x06);
2210 }
2211 #endif
2212