1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /* local prototypes */
28 static int ata_serverworks_chipinit(device_t dev);
29 static int ata_serverworks_allocate(device_t dev);
30 static void ata_serverworks_tf_read(struct ata_request *request);
31 static void ata_serverworks_tf_write(struct ata_request *request);
32 static void ata_serverworks_setmode(device_t dev, int mode);
33
34 /* misc defines */
35 #define SWKS_33 0
36 #define SWKS_66 1
37 #define SWKS_100 2
38 #define SWKS_MIO 3
39
40 /*
41 * ServerWorks chipset support functions
42 */
43 int
ata_serverworks_ident(device_t dev)44 ata_serverworks_ident(device_t dev)
45 {
46 struct ata_pci_controller *ctlr = device_get_softc(dev);
47 static const struct ata_chip_id ids[] =
48 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_UDMA2, "ROSB4" },
49 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
50 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
51 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
52 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
53 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
54 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
55 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
56 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
57 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
58 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
59 { 0, 0, 0, 0, 0, 0}};
60
61 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
62 return ENXIO;
63
64 if (!(ctlr->chip = ata_match_chip(dev, ids)))
65 return ENXIO;
66
67 ata_set_desc(dev);
68 ctlr->chipinit = ata_serverworks_chipinit;
69 return 0;
70 }
71
72 static int
ata_serverworks_chipinit(device_t dev)73 ata_serverworks_chipinit(device_t dev)
74 {
75 struct ata_pci_controller *ctlr = device_get_softc(dev);
76
77 if (ata_setup_interrupt(dev, ata_generic_intr))
78 return ENXIO;
79
80 if (ctlr->chip->cfg1 == SWKS_MIO) {
81 ctlr->r_type2 = SYS_RES_MEMORY;
82 ctlr->r_rid2 = PCIR_BAR(5);
83 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
84 &ctlr->r_rid2, RF_ACTIVE))){
85 ata_teardown_interrupt(dev);
86 return ENXIO;
87 }
88
89 ctlr->channels = ctlr->chip->cfg2;
90 ctlr->allocate = ata_serverworks_allocate;
91 ctlr->setmode = ata_sata_setmode;
92 return 0;
93 }
94 else if (ctlr->chip->cfg1 == SWKS_33) {
95 device_t *children;
96 int nchildren, i;
97
98 /* locate the ISA part in the southbridge and enable UDMA33 */
99 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
100 for (i = 0; i < nchildren; i++) {
101 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
102 pci_write_config(children[i], 0x64,
103 (pci_read_config(children[i], 0x64, 4) &
104 ~0x00002000) | 0x00004000, 4);
105 break;
106 }
107 }
108 kfree(children, M_TEMP);
109 }
110 }
111 else {
112 pci_write_config(dev, 0x5a,
113 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
114 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1);
115 }
116 ctlr->setmode = ata_serverworks_setmode;
117 return 0;
118 }
119
120 static int
ata_serverworks_allocate(device_t dev)121 ata_serverworks_allocate(device_t dev)
122 {
123 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
124 struct ata_channel *ch = device_get_softc(dev);
125 int ch_offset;
126 int i;
127
128 ch_offset = ch->unit * 0x100;
129
130 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
131 ch->r_io[i].res = ctlr->r_res2;
132
133 /* setup ATA registers */
134 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
135 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
136 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
137 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
138 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
139 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
140 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
141 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
142 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
143 ata_default_registers(dev);
144
145 /* setup DMA registers */
146 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
147 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
148 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
149
150 /* setup SATA registers */
151 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
152 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
153 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
154
155 ch->flags |= ATA_NO_SLAVE;
156 ata_pci_hw(dev);
157 ch->hw.tf_read = ata_serverworks_tf_read;
158 ch->hw.tf_write = ata_serverworks_tf_write;
159
160 /* chip does not reliably do 64K DMA transfers */
161 if (ch->dma)
162 ch->dma->max_iosize = 64 * DEV_BSIZE;
163
164 return 0;
165 }
166
167 static void
ata_serverworks_tf_read(struct ata_request * request)168 ata_serverworks_tf_read(struct ata_request *request)
169 {
170 struct ata_channel *ch = device_get_softc(request->parent);
171 struct ata_device *atadev = device_get_softc(request->dev);
172
173 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
174 u_int16_t temp;
175
176 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
177 temp = ATA_IDX_INW(ch, ATA_SECTOR);
178 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
179 ((u_int64_t)(temp & 0xff00) << 24);
180 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
181 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
182 ((u_int64_t)(temp & 0xff00) << 32);
183 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
184 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
185 ((u_int64_t)(temp & 0xff00) << 40);
186 }
187 else {
188 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
189 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
190 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
191 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
192 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
193 }
194 }
195
196 static void
ata_serverworks_tf_write(struct ata_request * request)197 ata_serverworks_tf_write(struct ata_request *request)
198 {
199 struct ata_channel *ch = device_get_softc(request->parent);
200 struct ata_device *atadev = device_get_softc(request->dev);
201
202 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
203 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
204 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
205 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
206 (request->u.ata.lba & 0x00ff));
207 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
208 ((request->u.ata.lba >> 8) & 0x00ff));
209 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
210 ((request->u.ata.lba >> 16) & 0x00ff));
211 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit));
212 }
213 else {
214 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
215 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
216 if (atadev->flags & ATA_D_USE_CHS) {
217 int heads, sectors;
218
219 if (atadev->param.atavalid & ATA_FLAG_54_58) {
220 heads = atadev->param.current_heads;
221 sectors = atadev->param.current_sectors;
222 }
223 else {
224 heads = atadev->param.heads;
225 sectors = atadev->param.sectors;
226 }
227
228 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
229 ATA_IDX_OUTW(ch, ATA_CYL_LSB,
230 (request->u.ata.lba / (sectors * heads)));
231 ATA_IDX_OUTW(ch, ATA_CYL_MSB,
232 (request->u.ata.lba / (sectors * heads)) >> 8);
233 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) |
234 (((request->u.ata.lba% (sectors * heads)) /
235 sectors) & 0xf));
236 }
237 else {
238 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
239 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
240 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
241 ATA_IDX_OUTW(ch, ATA_DRIVE,
242 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) |
243 ((request->u.ata.lba >> 24) & 0x0f));
244 }
245 }
246 }
247
248 static void
ata_serverworks_setmode(device_t dev,int mode)249 ata_serverworks_setmode(device_t dev, int mode)
250 {
251 device_t gparent = GRANDPARENT(dev);
252 struct ata_pci_controller *ctlr = device_get_softc(gparent);
253 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
254 struct ata_device *atadev = device_get_softc(dev);
255 int devno = (ch->unit << 1) + atadev->unit;
256 int offset = (devno ^ 0x01) << 3;
257 int error;
258 static const uint8_t piotimings[] =
259 { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
260 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
261 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
262
263 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
264
265 mode = ata_check_80pin(dev, mode);
266
267 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
268
269 if (bootverbose)
270 device_printf(dev, "%ssetting %s on %s chip\n",
271 (error) ? "FAILURE " : "",
272 ata_mode2str(mode), ctlr->chip->text);
273 if (!error) {
274 if (mode >= ATA_UDMA0) {
275 pci_write_config(gparent, 0x56,
276 (pci_read_config(gparent, 0x56, 2) &
277 ~(0xf << (devno << 2))) |
278 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
279 pci_write_config(gparent, 0x54,
280 pci_read_config(gparent, 0x54, 1) |
281 (0x01 << devno), 1);
282 pci_write_config(gparent, 0x44,
283 (pci_read_config(gparent, 0x44, 4) &
284 ~(0xff << offset)) |
285 (dmatimings[2] << offset), 4);
286 }
287 else if (mode >= ATA_WDMA0) {
288 pci_write_config(gparent, 0x54,
289 pci_read_config(gparent, 0x54, 1) &
290 ~(0x01 << devno), 1);
291 pci_write_config(gparent, 0x44,
292 (pci_read_config(gparent, 0x44, 4) &
293 ~(0xff << offset)) |
294 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
295 }
296 else
297 pci_write_config(gparent, 0x54,
298 pci_read_config(gparent, 0x54, 1) &
299 ~(0x01 << devno), 1);
300
301 pci_write_config(gparent, 0x40,
302 (pci_read_config(gparent, 0x40, 4) &
303 ~(0xff << offset)) |
304 (piotimings[ata_mode2idx(mode)] << offset), 4);
305 atadev->mode = mode;
306 }
307 }
308