1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 /*
29 * Pre-requisites: headers required by header of this unit
30 */
31 #include "include/i2caux_interface.h"
32 #include "../i2caux.h"
33 #include "../engine.h"
34 #include "../i2c_engine.h"
35 #include "../i2c_sw_engine.h"
36 #include "../i2c_hw_engine.h"
37
38 /*
39 * Header of this unit
40 */
41 #include "i2caux_dce110.h"
42
43 #include "i2c_sw_engine_dce110.h"
44 #include "i2c_hw_engine_dce110.h"
45 #include "aux_engine_dce110.h"
46 #include "../../dc.h"
47 #include "dc_types.h"
48
49
50 /*
51 * Post-requisites: headers required by this unit
52 */
53
54 /*
55 * This unit
56 */
57 /*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
58 #define FROM_I2C_AUX(ptr) \
59 container_of((ptr), struct i2caux_dce110, base)
60
destruct(struct i2caux_dce110 * i2caux_dce110)61 static void destruct(
62 struct i2caux_dce110 *i2caux_dce110)
63 {
64 dal_i2caux_destruct(&i2caux_dce110->base);
65 }
66
destroy(struct i2caux ** i2c_engine)67 static void destroy(
68 struct i2caux **i2c_engine)
69 {
70 struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
71
72 destruct(i2caux_dce110);
73
74 kfree(i2caux_dce110);
75
76 *i2c_engine = NULL;
77 }
78
acquire_i2c_hw_engine(struct i2caux * i2caux,struct ddc * ddc)79 static struct i2c_engine *acquire_i2c_hw_engine(
80 struct i2caux *i2caux,
81 struct ddc *ddc)
82 {
83 struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
84
85 struct i2c_engine *engine = NULL;
86 /* generic hw engine is not used for EDID read
87 * It may be needed for external i2c device, like thermal chip,
88 * TODO will be implemented when needed.
89 * check dce80 bool non_generic for generic hw engine;
90 */
91
92 if (!ddc)
93 return NULL;
94
95 if (ddc->hw_info.hw_supported) {
96 enum gpio_ddc_line line = dal_ddc_get_line(ddc);
97
98 if (line < GPIO_DDC_LINE_COUNT)
99 engine = i2caux->i2c_hw_engines[line];
100 }
101
102 if (!engine)
103 return NULL;
104
105 if (!i2caux_dce110->i2c_hw_buffer_in_use &&
106 engine->base.funcs->acquire(&engine->base, ddc)) {
107 i2caux_dce110->i2c_hw_buffer_in_use = true;
108 return engine;
109 }
110
111 return NULL;
112 }
113
release_engine(struct i2caux * i2caux,struct engine * engine)114 static void release_engine(
115 struct i2caux *i2caux,
116 struct engine *engine)
117 {
118 struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
119
120 if (engine->funcs->get_engine_type(engine) ==
121 I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
122 i2caux_dce110->i2c_hw_buffer_in_use = false;
123
124 dal_i2caux_release_engine(i2caux, engine);
125 }
126
127 static const enum gpio_ddc_line hw_ddc_lines[] = {
128 GPIO_DDC_LINE_DDC1,
129 GPIO_DDC_LINE_DDC2,
130 GPIO_DDC_LINE_DDC3,
131 GPIO_DDC_LINE_DDC4,
132 GPIO_DDC_LINE_DDC5,
133 GPIO_DDC_LINE_DDC6,
134 };
135
136 static const enum gpio_ddc_line hw_aux_lines[] = {
137 GPIO_DDC_LINE_DDC1,
138 GPIO_DDC_LINE_DDC2,
139 GPIO_DDC_LINE_DDC3,
140 GPIO_DDC_LINE_DDC4,
141 GPIO_DDC_LINE_DDC5,
142 GPIO_DDC_LINE_DDC6,
143 };
144
145 /* function table */
146 static const struct i2caux_funcs i2caux_funcs = {
147 .destroy = destroy,
148 .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
149 .release_engine = release_engine,
150 .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
151 .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
152 };
153
154 #include "dce/dce_11_0_d.h"
155 #include "dce/dce_11_0_sh_mask.h"
156
157 /* set register offset */
158 #define SR(reg_name)\
159 .reg_name = mm ## reg_name
160
161 /* set register offset with instance */
162 #define SRI(reg_name, block, id)\
163 .reg_name = mm ## block ## id ## _ ## reg_name
164
165 #define aux_regs(id)\
166 [id] = {\
167 AUX_COMMON_REG_LIST(id), \
168 .AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
169 }
170
171 #define hw_engine_regs(id)\
172 {\
173 I2C_HW_ENGINE_COMMON_REG_LIST(id) \
174 }
175
176 static const struct dce110_aux_registers dce110_aux_regs[] = {
177 aux_regs(0),
178 aux_regs(1),
179 aux_regs(2),
180 aux_regs(3),
181 aux_regs(4),
182 aux_regs(5)
183 };
184
185 static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
186 hw_engine_regs(1),
187 hw_engine_regs(2),
188 hw_engine_regs(3),
189 hw_engine_regs(4),
190 hw_engine_regs(5),
191 hw_engine_regs(6)
192 };
193
194 static const struct dce110_i2c_hw_engine_shift i2c_shift = {
195 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
196 };
197
198 static const struct dce110_i2c_hw_engine_mask i2c_mask = {
199 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
200 };
201
dal_i2caux_dce110_construct(struct i2caux_dce110 * i2caux_dce110,struct dc_context * ctx,unsigned int num_i2caux_inst,const struct dce110_aux_registers aux_regs[],const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],const struct dce110_i2c_hw_engine_shift * i2c_shift,const struct dce110_i2c_hw_engine_mask * i2c_mask)202 void dal_i2caux_dce110_construct(
203 struct i2caux_dce110 *i2caux_dce110,
204 struct dc_context *ctx,
205 unsigned int num_i2caux_inst,
206 const struct dce110_aux_registers aux_regs[],
207 const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
208 const struct dce110_i2c_hw_engine_shift *i2c_shift,
209 const struct dce110_i2c_hw_engine_mask *i2c_mask)
210 {
211 uint32_t i = 0;
212 uint32_t reference_frequency = 0;
213 bool use_i2c_sw_engine = false;
214 struct i2caux *base = NULL;
215 /*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
216 * does not return 48KHz, we need hard coded for 48Khz.
217 * Some BIOS setting incorrect cause this
218 * For production, we always get value from BIOS*/
219 reference_frequency =
220 dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
221
222 base = &i2caux_dce110->base;
223
224 dal_i2caux_construct(base, ctx);
225
226 i2caux_dce110->base.funcs = &i2caux_funcs;
227 i2caux_dce110->i2c_hw_buffer_in_use = false;
228 /* Create I2C engines (DDC lines per connector)
229 * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
230 */
231 do {
232 enum gpio_ddc_line line_id = hw_ddc_lines[i];
233
234 struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
235
236 if (use_i2c_sw_engine) {
237 struct i2c_sw_engine_dce110_create_arg sw_arg;
238
239 sw_arg.engine_id = i;
240 sw_arg.default_speed = base->default_i2c_sw_speed;
241 sw_arg.ctx = ctx;
242 base->i2c_sw_engines[line_id] =
243 dal_i2c_sw_engine_dce110_create(&sw_arg);
244 }
245
246 hw_arg_dce110.engine_id = i;
247 hw_arg_dce110.reference_frequency = reference_frequency;
248 hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
249 hw_arg_dce110.ctx = ctx;
250 hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
251 hw_arg_dce110.i2c_shift = i2c_shift;
252 hw_arg_dce110.i2c_mask = i2c_mask;
253
254 base->i2c_hw_engines[line_id] =
255 dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
256 if (base->i2c_hw_engines[line_id] != NULL) {
257 switch (ctx->dce_version) {
258 case DCN_VERSION_1_0:
259 base->i2c_hw_engines[line_id]->setup_limit =
260 I2C_SETUP_TIME_LIMIT_DCN;
261 base->i2c_hw_engines[line_id]->send_reset_length = 0;
262 break;
263 default:
264 base->i2c_hw_engines[line_id]->setup_limit =
265 I2C_SETUP_TIME_LIMIT_DCE;
266 base->i2c_hw_engines[line_id]->send_reset_length = 0;
267 break;
268 }
269 }
270 ++i;
271 } while (i < num_i2caux_inst);
272
273 /* Create AUX engines for all lines which has assisted HW AUX
274 * 'i' (loop counter) used as DDC/AUX engine_id */
275
276 i = 0;
277
278 do {
279 enum gpio_ddc_line line_id = hw_aux_lines[i];
280
281 struct aux_engine_dce110_init_data aux_init_data;
282
283 aux_init_data.engine_id = i;
284 aux_init_data.timeout_period = base->aux_timeout_period;
285 aux_init_data.ctx = ctx;
286 aux_init_data.regs = &aux_regs[i];
287
288 base->aux_engines[line_id] =
289 dal_aux_engine_dce110_create(&aux_init_data);
290
291 ++i;
292 } while (i < num_i2caux_inst);
293
294 /*TODO Generic I2C SW and HW*/
295 }
296
297 /*
298 * dal_i2caux_dce110_create
299 *
300 * @brief
301 * public interface to allocate memory for DCE11 I2CAUX
302 *
303 * @param
304 * struct adapter_service *as - [in]
305 * struct dc_context *ctx - [in]
306 *
307 * @return
308 * pointer to the base struct of DCE11 I2CAUX
309 */
dal_i2caux_dce110_create(struct dc_context * ctx)310 struct i2caux *dal_i2caux_dce110_create(
311 struct dc_context *ctx)
312 {
313 struct i2caux_dce110 *i2caux_dce110 =
314 kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
315
316 if (!i2caux_dce110) {
317 ASSERT_CRITICAL(false);
318 return NULL;
319 }
320
321 dal_i2caux_dce110_construct(i2caux_dce110,
322 ctx,
323 ARRAY_SIZE(dce110_aux_regs),
324 dce110_aux_regs,
325 i2c_hw_engine_regs,
326 &i2c_shift,
327 &i2c_mask);
328 return &i2caux_dce110->base;
329 }
330