1 #ifndef _E5_IMC_REG_H_ 2 #define _E5_IMC_REG_H_ 3 4 #ifndef _SYS_BITOPS_H_ 5 #include <sys/bitops.h> 6 #endif 7 8 /* 9 * E5 v2/v3 supports 4 channels, each channels could have 3 DIMMs. 10 * However each channel could only support 8 ranks, e.g. 3 quad- 11 * rank DIMMs can _not_ be installed. 12 * 13 * E5 v2 only has IMC0, which has 4 channels (channel 0~3). 14 * 15 * E5 v3 has two configuration: 16 * - IMC0, which has 4 channels (channel 0~3). 17 * - IMC0, which has 2 channels (channel 0~1) and IMC1, which has 18 * 2 channels (channel 2~3). 19 */ 20 21 #define PCI_E5_IMC_VID_ID 0x8086 22 #define PCI_E5_IMC_CHN_MAX 4 /* max chans/sock */ 23 #define PCI_E5_IMC_CHN_DIMM_MAX 3 /* max dimms/chan */ 24 #define PCI_E5_IMC_ERROR_RANK_MAX 8 25 26 /* 27 * UBOX0 28 */ 29 /* E5 v2 */ 30 #define PCISLOT_E5V2_UBOX0 11 31 #define PCIFUNC_E5V2_UBOX0 0 32 #define PCI_E5V2_UBOX0_DID_ID 0x0e1e 33 /* E5 v3 */ 34 #define PCISLOT_E5V3_UBOX0 16 35 #define PCIFUNC_E5V3_UBOX0 5 36 #define PCI_E5V3_UBOX0_DID_ID 0x2f1e 37 /* UBOX0 regs */ 38 #define PCI_E5_UBOX0_CPUNODEID 0x40 39 #define PCI_E5_UBOX0_CPUNODEID_LCLNODEID __BITS(0, 2) /* local socket */ 40 41 /* 42 * IMC main (aka CPGC) 43 */ 44 /* E5 v2 */ 45 #define PCISLOT_E5V2_IMC0_CPGC 15 46 #define PCIFUNC_E5V2_IMC0_CPGC 0 47 #define PCI_E5V2_IMC0_CPGC_DID_ID 0x0ea8 48 /* E5 v3 */ 49 #define PCISLOT_E5V3_IMC0_CPGC 19 50 #define PCIFUNC_E5V3_IMC0_CPGC 0 51 #define PCI_E5V3_IMC0_CPGC_DID_ID 0x2fa8 52 #define PCISLOT_E5V3_IMC1_CPGC 22 53 #define PCIFUNC_E5V3_IMC1_CPGC 0 54 #define PCI_E5V3_IMC1_CPGC_DID_ID 0x2f68 55 /* CPGC regs */ 56 #define PCI_E5_IMC_CPGC_MCMTR 0x7c 57 #define PCI_E5V2_IMC_CPGC_MCMTR_CHN_DISABLE(c) __BIT(16 + (c)) 58 #define PCI_E5V3_IMC_CPGC_MCMTR_CHN_DISABLE(c) __BIT(18 + (c)) 59 #define PCI_E5V3_IMC_CPGC_MCMTR_DDR4 __BIT(14) 60 #define PCI_E5_IMC_CPGC_MCMTR_IMC_MODE __BITS(12, 13) 61 #define PCI_E5_IMC_CPGC_MCMTR_IMC_MODE_DDR3 0 /* v3 native DDR */ 62 #define PCI_E5_IMC_CPGC_MCMTR_ECC_EN __BIT(2) 63 64 /* 65 * Channel Target Address Decoder, per-channel 66 */ 67 /* E5 v2 */ 68 #define PCISLOT_E5V2_IMC0_CTAD 15 69 #define PCIFUNC_E5V2_IMC0_CTAD(c) (2 + (c)) 70 #define PCI_E5V2_IMC0_CTAD_DID_ID(c) (0x0eaa + (c)) 71 /* E5 v3 */ 72 #define PCISLOT_E5V3_IMC0_CTAD 19 73 #define PCIFUNC_E5V3_IMC0_CTAD(c) (2 + (c)) 74 #define PCI_E5V3_IMC0_CTAD_DID_ID(c) (0x2faa + (c)) 75 #define PCISLOT_E5V3_IMC1_CTAD 22 76 #define PCIFUNC_E5V3_IMC1_CTAD(c) (2 + (c)) 77 #define PCI_E5V3_IMC1_CTAD_DID_ID(c) (0x2f6a + (c)) 78 /* CTAD regs */ 79 #define PCI_E5_IMC_CTAD_DIMMMTR(dimm) (0x80 + ((dimm) * 4)) 80 #define PCI_E5V3_IMC_CTAD_DIMMMTR_DDR4 __BIT(20) 81 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_DISABLE(r) __BIT(16 + (r)) 82 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_DISABLE_ALL __BITS(16, 19) 83 #define PCI_E5_IMC_CTAD_DIMMMTR_DIMM_POP __BIT(14) 84 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT __BITS(12, 13) 85 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT_SR 0 86 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT_DR 1 87 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT_QR 2 88 #define PCI_E5V3_IMC_CTAD_DIMMMTR_RANK_CNT_8R 3 89 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH __BITS(7, 8) 90 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH_4 0 91 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH_8 1 92 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH_16 2 93 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH_RSVD 3 94 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY __BITS(5, 6) 95 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY_1G 0 /* v3 reserved */ 96 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY_2G 1 97 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY_4G 2 98 #define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY_8G 3 99 100 /* 101 * ERROR, per-channel 102 */ 103 /* E5 v2 */ 104 #define PCISLOT_E5V2_IMC0_ERROR_CHN0 16 105 #define PCIFUNC_E5V2_IMC0_ERROR_CHN0 2 106 #define PCI_E5V2_IMC0_ERROR_CHN0_DID_ID 0x0eb2 107 #define PCISLOT_E5V2_IMC0_ERROR_CHN1 16 108 #define PCIFUNC_E5V2_IMC0_ERROR_CHN1 3 109 #define PCI_E5V2_IMC0_ERROR_CHN1_DID_ID 0x0eb3 110 #define PCISLOT_E5V2_IMC0_ERROR_CHN2 16 111 #define PCIFUNC_E5V2_IMC0_ERROR_CHN2 6 112 #define PCI_E5V2_IMC0_ERROR_CHN2_DID_ID 0x0eb6 113 #define PCISLOT_E5V2_IMC0_ERROR_CHN3 16 114 #define PCIFUNC_E5V2_IMC0_ERROR_CHN3 7 115 #define PCI_E5V2_IMC0_ERROR_CHN3_DID_ID 0x0eb7 116 /* E5 v3 */ 117 #define PCISLOT_E5V3_IMC0_ERROR_CHN0 20 118 #define PCIFUNC_E5V3_IMC0_ERROR_CHN0 2 119 #define PCI_E5V3_IMC0_ERROR_CHN0_DID_ID 0x2fb2 120 #define PCISLOT_E5V3_IMC0_ERROR_CHN1 20 121 #define PCIFUNC_E5V3_IMC0_ERROR_CHN1 3 122 #define PCI_E5V3_IMC0_ERROR_CHN1_DID_ID 0x2fb3 123 #define PCISLOT_E5V3_IMC0_ERROR_CHN2 21 124 #define PCIFUNC_E5V3_IMC0_ERROR_CHN2 2 125 #define PCI_E5V3_IMC0_ERROR_CHN2_DID_ID 0x2fb6 126 #define PCISLOT_E5V3_IMC0_ERROR_CHN3 21 127 #define PCIFUNC_E5V3_IMC0_ERROR_CHN3 3 128 #define PCI_E5V3_IMC0_ERROR_CHN3_DID_ID 0x2fb7 129 #define PCISLOT_E5V3_IMC1_ERROR_CHN0 23 130 #define PCIFUNC_E5V3_IMC1_ERROR_CHN0 2 131 #define PCI_E5V3_IMC1_ERROR_CHN0_DID_ID 0x2fd6 132 #define PCISLOT_E5V3_IMC1_ERROR_CHN1 23 133 #define PCIFUNC_E5V3_IMC1_ERROR_CHN1 3 134 #define PCI_E5V3_IMC1_ERROR_CHN1_DID_ID 0x2fd7 135 /* ERROR regs */ 136 #define PCI_E5_IMC_ERROR_COR_ERR_CNT(i) (0x104 + ((i) * 4)) 137 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_HI_OVFL __BIT(31) 138 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_HI __BITS(16, 30) 139 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_LO_OVFL __BIT(15) 140 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_LO __BITS(0, 14) 141 #define PCI_E5_IMC_ERROR_COR_ERR_TH(i) (0x11c + ((i) * 4)) 142 #define PCI_E5_IMC_ERROR_COR_ERR_TH_HI __BITS(16, 30) 143 #define PCI_E5_IMC_ERROR_COR_ERR_TH_LO __BITS(0, 14) 144 #define PCI_E5_IMC_ERROR_COR_ERR_STAT 0x134 145 #define PCI_E5_IMC_ERROR_COR_ERR_STAT_RANKS __BITS(0, 7) 146 147 /* 148 * Thermal, per-channel 149 */ 150 /* E5 v2 */ 151 #define PCISLOT_E5V2_IMC0_THERMAL_CHN0 16 152 #define PCIFUNC_E5V2_IMC0_THERMAL_CHN0 0 153 #define PCI_E5V2_IMC0_THERMAL_CHN0_DID_ID 0x0eb0 154 #define PCISLOT_E5V2_IMC0_THERMAL_CHN1 16 155 #define PCIFUNC_E5V2_IMC0_THERMAL_CHN1 1 156 #define PCI_E5V2_IMC0_THERMAL_CHN1_DID_ID 0x0eb1 157 #define PCISLOT_E5V2_IMC0_THERMAL_CHN2 16 158 #define PCIFUNC_E5V2_IMC0_THERMAL_CHN2 4 159 #define PCI_E5V2_IMC0_THERMAL_CHN2_DID_ID 0x0eb4 160 #define PCISLOT_E5V2_IMC0_THERMAL_CHN3 16 161 #define PCIFUNC_E5V2_IMC0_THERMAL_CHN3 5 162 #define PCI_E5V2_IMC0_THERMAL_CHN3_DID_ID 0x0eb5 163 /* E5 v3 */ 164 #define PCISLOT_E5V3_IMC0_THERMAL_CHN0 20 165 #define PCIFUNC_E5V3_IMC0_THERMAL_CHN0 0 166 #define PCI_E5V3_IMC0_THERMAL_CHN0_DID_ID 0x2fb0 167 #define PCISLOT_E5V3_IMC0_THERMAL_CHN1 20 168 #define PCIFUNC_E5V3_IMC0_THERMAL_CHN1 1 169 #define PCI_E5V3_IMC0_THERMAL_CHN1_DID_ID 0x2fb1 170 #define PCISLOT_E5V3_IMC0_THERMAL_CHN2 21 171 #define PCIFUNC_E5V3_IMC0_THERMAL_CHN2 0 172 #define PCI_E5V3_IMC0_THERMAL_CHN2_DID_ID 0x2fb4 173 #define PCISLOT_E5V3_IMC0_THERMAL_CHN3 21 174 #define PCIFUNC_E5V3_IMC0_THERMAL_CHN3 1 175 #define PCI_E5V3_IMC0_THERMAL_CHN3_DID_ID 0x2fb5 176 #define PCISLOT_E5V3_IMC1_THERMAL_CHN0 23 177 #define PCIFUNC_E5V3_IMC1_THERMAL_CHN0 0 178 #define PCI_E5V3_IMC1_THERMAL_CHN0_DID_ID 0x2fd0 179 #define PCISLOT_E5V3_IMC1_THERMAL_CHN1 23 180 #define PCIFUNC_E5V3_IMC1_THERMAL_CHN1 1 181 #define PCI_E5V3_IMC1_THERMAL_CHN1_DID_ID 0x2fd1 182 /* Thermal regs */ 183 #define PCI_E5_IMC_THERMAL_CHN_TEMP_CFG 0x108 184 #define PCI_E5_IMC_THERMAL_CHN_TEMP_CFG_OLTT_EN __BIT(31) 185 #define PCI_E5_IMC_THERMAL_CHN_TEMP_CFG_CLTT __BIT(29) 186 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH(dimm) (0x120 + ((dimm) * 4)) 187 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPHI __BITS(16, 23) 188 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPMID __BITS(8, 15) 189 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPLO __BITS(0, 7) 190 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPMIN 32 /* [MIN, MAX) */ 191 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPMAX 128 192 #define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_DISABLE 255 193 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT(dimm) (0x150 + ((dimm) * 4)) 194 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPHI __BIT(28) 195 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPMID __BIT(27) 196 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPLO __BIT(26) 197 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPOEMLO __BIT(25) 198 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPOEMHI __BIT(24) 199 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMP __BITS(0, 7) 200 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPMIN 0 /* [MIN, MAX) */ 201 #define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMPMAX 127 202 203 #endif /* !_E5_IMC_REG_H_ */ 204