1 /*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written consent. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.13 2007/05/16 23:34:11 davidch Exp $ 30 */ 31 32 #ifndef _BCE_H_DEFINED 33 #define _BCE_H_DEFINED 34 35 /****************************************************************************/ 36 /* Device identification definitions. */ 37 /****************************************************************************/ 38 #define BRCM_VENDORID 0x14E4 39 #define BRCM_DEVICEID_BCM5706 0x164A 40 #define BRCM_DEVICEID_BCM5706S 0x16AA 41 #define BRCM_DEVICEID_BCM5708 0x164C 42 #define BRCM_DEVICEID_BCM5708S 0x16AC 43 #define BRCM_DEVICEID_BCM5709 0x1639 44 #define BRCM_DEVICEID_BCM5709S 0x163A 45 #define BRCM_DEVICEID_BCM5716 0x163B 46 47 #define HP_VENDORID 0x103C 48 49 #define PCI_ANY_ID (uint16_t) (~0U) 50 51 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 52 53 #define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 54 #define BCE_CHIP_NUM_5706 0x57060000 55 #define BCE_CHIP_NUM_5708 0x57080000 56 #define BCE_CHIP_NUM_5709 0x57090000 57 #define BCE_CHIP_NUM_5716 0x57160000 58 59 #define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 60 #define BCE_CHIP_REV_Ax 0x00000000 61 #define BCE_CHIP_REV_Bx 0x00001000 62 #define BCE_CHIP_REV_Cx 0x00002000 63 64 #define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 65 #define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 66 67 #define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 68 #define BCE_CHIP_ID_5706_A0 0x57060000 69 #define BCE_CHIP_ID_5706_A1 0x57060010 70 #define BCE_CHIP_ID_5706_A2 0x57060020 71 #define BCE_CHIP_ID_5706_A3 0x57060030 72 #define BCE_CHIP_ID_5708_A0 0x57080000 73 #define BCE_CHIP_ID_5708_B0 0x57081000 74 #define BCE_CHIP_ID_5708_B1 0x57081010 75 #define BCE_CHIP_ID_5708_B2 0x57081020 76 #define BCE_CHIP_ID_5709_A0 0x57090000 77 #define BCE_CHIP_ID_5709_A1 0x57090010 78 #define BCE_CHIP_ID_5709_B0 0x57091000 79 #define BCE_CHIP_ID_5709_B1 0x57091010 80 #define BCE_CHIP_ID_5709_B2 0x57091020 81 #define BCE_CHIP_ID_5709_C0 0x57092000 82 #define BCE_CHIP_ID_5716_C0 0x57162000 83 84 #define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 85 86 /* A serdes chip will have the first bit of the bond id set. */ 87 #define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 88 89 90 /* shorthand one */ 91 #define BCE_ASICREV(x) ((x) >> 28) 92 #define BCE_ASICREV_BCM5700 0x06 93 94 /* chip revisions */ 95 #define BCE_CHIPREV(x) ((x) >> 24) 96 #define BCE_CHIPREV_5700_AX 0x70 97 #define BCE_CHIPREV_5700_BX 0x71 98 #define BCE_CHIPREV_5700_CX 0x72 99 #define BCE_CHIPREV_5701_AX 0x00 100 101 struct bce_type { 102 uint16_t bce_vid; 103 uint16_t bce_did; 104 uint16_t bce_svid; 105 uint16_t bce_sdid; 106 const char *bce_name; 107 }; 108 109 /****************************************************************************/ 110 /* NVRAM Access */ 111 /****************************************************************************/ 112 113 /* Buffered flash (Atmel: AT45DB011B) specific information */ 114 #define SEEPROM_PAGE_BITS 2 115 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 116 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 117 #define SEEPROM_PAGE_SIZE 4 118 #define SEEPROM_TOTAL_SIZE 65536 119 120 #define BUFFERED_FLASH_PAGE_BITS 9 121 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 122 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 123 #define BUFFERED_FLASH_PAGE_SIZE 264 124 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 125 126 #define SAIFUN_FLASH_PAGE_BITS 8 127 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 128 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 129 #define SAIFUN_FLASH_PAGE_SIZE 256 130 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 131 132 #define ST_MICRO_FLASH_PAGE_BITS 8 133 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 134 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 135 #define ST_MICRO_FLASH_PAGE_SIZE 256 136 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 137 138 #define BCM5709_FLASH_PAGE_BITS 8 139 #define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) 140 #define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) 141 #define BCM5709_FLASH_PAGE_SIZE 256 142 143 #define NVRAM_TIMEOUT_COUNT 30000 144 #define BCE_FLASHDESC_MAX 64 145 146 #define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 147 BCE_NVM_CFG1_BUFFER_MODE | \ 148 BCE_NVM_CFG1_PROTECT_MODE | \ 149 BCE_NVM_CFG1_FLASH_SIZE) 150 151 #define FLASH_BACKUP_STRAP_MASK (0xf << 26) 152 153 struct flash_spec { 154 uint32_t strapping; 155 uint32_t config1; 156 uint32_t config2; 157 uint32_t config3; 158 uint32_t write1; 159 #define BCE_NV_BUFFERED 0x00000001 160 #define BCE_NV_TRANSLATE 0x00000002 161 #define BCE_NV_WREN 0x00000004 162 uint32_t flags; 163 uint32_t page_bits; 164 uint32_t page_size; 165 uint32_t addr_mask; 166 uint32_t total_size; 167 uint8_t *name; 168 }; 169 170 171 /****************************************************************************/ 172 /* Shared Memory layout */ 173 /* The BCE bootcode will initialize this data area with port configurtion */ 174 /* information which can be accessed by the driver. */ 175 /****************************************************************************/ 176 177 /* 178 * This value (in milliseconds) determines the frequency of the driver 179 * issuing the PULSE message code. The firmware monitors this periodic 180 * pulse to determine when to switch to an OS-absent mode. 181 */ 182 #define DRV_PULSE_PERIOD_MS 250 183 184 /* 185 * This value (in milliseconds) determines how long the driver should 186 * wait for an acknowledgement from the firmware before timing out. Once 187 * the firmware has timed out, the driver will assume there is no firmware 188 * running and there won't be any firmware-driver synchronization during a 189 * driver reset. 190 */ 191 #define FW_ACK_TIME_OUT_MS 1000 192 193 194 #define BCE_DRV_RESET_SIGNATURE 0x00000000 195 #define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 196 197 #define BCE_DRV_MB 0x00000004 198 #define BCE_DRV_MSG_CODE 0xff000000 199 #define BCE_DRV_MSG_CODE_RESET 0x01000000 200 #define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 201 #define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 202 #define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 203 #define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 204 #define BCE_DRV_MSG_CODE_PULSE 0x06000000 205 #define BCE_DRV_MSG_CODE_DIAG 0x07000000 206 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 207 #define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 208 209 #define BCE_DRV_MSG_DATA 0x00ff0000 210 #define BCE_DRV_MSG_DATA_WAIT0 0x00010000 211 #define BCE_DRV_MSG_DATA_WAIT1 0x00020000 212 #define BCE_DRV_MSG_DATA_WAIT2 0x00030000 213 #define BCE_DRV_MSG_DATA_WAIT3 0x00040000 214 215 #define BCE_DRV_MSG_SEQ 0x0000ffff 216 217 #define BCE_FW_MB 0x00000008 218 #define BCE_FW_MSG_ACK 0x0000ffff 219 #define BCE_FW_MSG_STATUS_MASK 0x00ff0000 220 #define BCE_FW_MSG_STATUS_OK 0x00000000 221 #define BCE_FW_MSG_STATUS_INVALID_ARGS 0x00010000 222 #define BCE_FW_MSG_STATUS_DRV_PRSNT 0x00020000 223 #define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 224 225 #define BCE_LINK_STATUS 0x0000000c 226 #define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 227 #define BCE_LINK_STATUS_LINK_UP 0x1 228 #define BCE_LINK_STATUS_LINK_DOWN 0x0 229 #define BCE_LINK_STATUS_SPEED_MASK 0x1e 230 #define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 231 #define BCE_LINK_STATUS_10HALF (1<<1) 232 #define BCE_LINK_STATUS_10FULL (2<<1) 233 #define BCE_LINK_STATUS_100HALF (3<<1) 234 #define BCE_LINK_STATUS_100BASE_T4 (4<<1) 235 #define BCE_LINK_STATUS_100FULL (5<<1) 236 #define BCE_LINK_STATUS_1000HALF (6<<1) 237 #define BCE_LINK_STATUS_1000FULL (7<<1) 238 #define BCE_LINK_STATUS_2500HALF (8<<1) 239 #define BCE_LINK_STATUS_2500FULL (9<<1) 240 #define BCE_LINK_STATUS_AN_ENABLED (1<<5) 241 #define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 242 #define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 243 #define BCE_LINK_STATUS_RESERVED (1<<8) 244 #define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 245 #define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 246 #define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 247 #define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 248 #define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 249 #define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 250 #define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 251 #define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 252 #define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 253 #define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 254 #define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 255 #define BCE_LINK_STATUS_SERDES_LINK (1<<20) 256 #define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 257 #define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 258 259 #define BCE_DRV_PULSE_MB 0x00000010 260 #define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 261 262 /* Indicate to the firmware not to go into the 263 * OS absent when it is not getting driver pulse. 264 * This is used for debugging. */ 265 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 266 267 #define BCE_DEV_INFO_SIGNATURE 0x00000020 268 #define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 269 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 270 #define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 271 #define BCE_DEV_INFO_SECONDARY_PORT 0x80 272 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 273 274 #define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 275 276 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 277 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 278 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 279 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 280 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 281 282 #define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 283 #define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 284 #define BCE_SHARED_HW_CFG_DESIGN_NIC 0 285 #define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 286 #define BCE_SHARED_HW_CFG_PHY_COPPER 0 287 #define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 288 #define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 289 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 290 #define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 291 #define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 292 #define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 293 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 294 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 295 296 #define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 297 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 298 299 #define BCE_DEV_INFO_BC_REV 0x0000004c 300 301 #define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 302 #define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 303 304 #define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 305 #define BCE_PORT_HW_CFG_CONFIG 0x00000058 306 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 307 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 308 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 309 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 310 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 311 312 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 313 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 314 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 315 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 316 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 317 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 318 319 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 320 321 #define BCE_DEV_INFO_FORMAT_REV 0x000000c4 322 #define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 323 #define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 324 325 #define BCE_SHARED_FEATURE 0x000000c8 326 #define BCE_SHARED_FEATURE_MASK 0xffffffff 327 328 #define BCE_PORT_FEATURE 0x000000d8 329 #define BCE_PORT2_FEATURE 0x00000014c 330 #define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 331 #define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 332 #define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 333 #define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 334 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 335 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 336 #define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 337 #define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 338 #define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 339 #define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 340 #define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 341 #define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 342 #define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 343 #define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 344 #define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 345 #define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 346 #define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 347 #define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 348 #define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 349 #define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 350 #define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 351 352 #define BCE_PORT_FEATURE_WOL 0xdc 353 #define BCE_PORT2_FEATURE_WOL 0x150 354 #define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 355 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 356 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 357 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 358 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 359 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 360 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 361 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 362 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 363 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 364 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 365 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 366 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 367 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 368 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 369 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 370 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 371 372 #define BCE_PORT_FEATURE_MBA 0xe0 373 #define BCE_PORT2_FEATURE_MBA 0x154 374 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 375 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 376 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 377 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 378 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 379 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 380 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 381 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 382 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 383 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 384 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 385 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 386 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 387 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 388 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 389 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 390 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 391 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 392 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 393 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 394 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 395 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 396 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 397 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 398 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 399 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 400 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 401 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 402 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 403 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 404 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 405 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 406 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 407 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 408 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 409 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 410 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 411 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 412 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 413 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 414 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 415 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 416 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 417 418 #define BCE_PORT_FEATURE_IMD 0xe4 419 #define BCE_PORT2_FEATURE_IMD 0x158 420 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 421 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 422 423 #define BCE_PORT_FEATURE_VLAN 0xe8 424 #define BCE_PORT2_FEATURE_VLAN 0x15c 425 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 426 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 427 428 #define BCE_MFW_VER_PTR 0x00000014c 429 430 #define BCE_BC_STATE_RESET_TYPE 0x000001c0 431 #define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 432 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 433 #define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ 434 0x00010000) 435 #define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ 436 0x00020000) 437 #define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ 438 0x00030000) 439 #define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 440 #define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ 441 DRV_MSG_CODE_RESET) 442 #define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ 443 DRV_MSG_CODE_UNLOAD) 444 #define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ 445 DRV_MSG_CODE_SHUTDOWN) 446 #define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ 447 DRV_MSG_CODE_WOL) 448 #define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ 449 DRV_MSG_CODE_DIAG) 450 #define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ 451 (msg)) 452 453 #define BCE_BC_STATE 0x000001c4 454 #define BCE_BC_STATE_ERR_MASK 0x0000ff00 455 #define BCE_BC_STATE_SIGN 0x42530000 456 #define BCE_BC_STATE_SIGN_MASK 0xffff0000 457 #define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 458 #define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 459 #define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 460 #define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 461 #define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 462 #define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 463 #define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 464 #define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 465 #define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 466 #define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 467 #define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 468 #define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 469 #define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 470 #define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 471 #define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 472 #define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 473 #define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 474 #define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 475 #define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 476 #define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 477 #define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 478 #define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 479 #define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 480 #define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 481 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 482 483 #define BCE_BC_STATE_CONDITION 0x000001c8 484 #define BCE_CONDITION_INIT_POR 0x00000001 485 #define BCE_CONDITION_INIT_VAUX_AVAIL 0x00000002 486 #define BCE_CONDITION_INIT_PCI_AVAIL 0x00000004 487 #define BCE_CONDITION_INIT_PCI_RESET 0x00000008 488 #define BCE_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */ 489 #define BCE_CONDITION_DRV_PRESENT 0x00000100 490 #define BCE_CONDITION_LOW_POWER_LINK 0x00000200 491 #define BCE_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */ 492 #define BCE_CONDITION_UNUSED 0x00000800 493 #define BCE_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */ 494 495 #define BCE_CONDITION_MFW_RUN_UNKNOWN 0x00000000 496 #define BCE_CONDITION_MFW_RUN_IPMI 0x00002000 497 #define BCE_CONDITION_MFW_RUN_UMP 0x00004000 498 #define BCE_CONDITION_MFW_RUN_NCSI 0x00006000 499 #define BCE_CONDITION_MFW_RUN_NONE 0x0000e000 500 #define BCE_CONDITION_MFW_RUN_MASK 0x0000e000 501 502 /* 5709/16 only */ 503 #define BCE_CONDITION_PM_STATE_MASK 0x00030000 504 #define BCE_CONDITION_PM_STATE_FULL 0x00030000 505 #define BCE_CONDITION_PM_STATE_PREP 0x00020000 506 #define BCE_CONDITION_PM_STATE_UNPREP 0x00010000 507 #define BCE_CONDITION_PM_RESERVED 0x00000000 508 509 /* 5709/16 only */ 510 #define BCE_CONDITION_RXMODE_KEEP_VLAN 0x00040000 511 #define BCE_CONDITION_DRV_WOL_ENABLED 0x00080000 512 #define BCE_CONDITION_PORT_DISABLED 0x00100000 513 #define BCE_CONDITION_DRV_MAYBE_OUT 0x00200000 514 #define BCE_CONDITION_DPFW_DEAD 0x00400000 515 516 #define BCE_BC_STATE_DEBUG_CMD 0x1dc 517 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 518 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 519 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 520 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 521 522 #define HOST_VIEW_SHMEM_BASE 0x167c00 523 524 /* 525 * PCI registers defined in the PCI 2.2 spec. 526 */ 527 #define BCE_PCI_PCIX_CMD 0x42 528 529 530 /****************************************************************************/ 531 /* Convenience definitions. */ 532 /****************************************************************************/ 533 #define REG_WR(sc, reg, val) \ 534 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) 535 #define REG_WR16(sc, reg, val) \ 536 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) 537 #define REG_RD(sc, reg) \ 538 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) 539 540 #define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 541 #define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 542 543 #define CTX_WR(sc, cid_addr, offset, val) \ 544 bce_ctx_wr(sc, cid_addr, offset, val) 545 546 #define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 547 #define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 548 549 #define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 550 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 551 #define BCE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 552 #define BCE_ADDR_HI(y) ((uint64_t) (y) >> 32) 553 #else 554 #define BCE_ADDR_LO(y) ((uint32_t)y) 555 #define BCE_ADDR_HI(y) (0) 556 #endif 557 558 559 /* 560 * The following data structures are generated from RTL code. 561 * Do not modify any values below this line. 562 */ 563 564 /****************************************************************************/ 565 /* Do not modify any of the following data structures, they are generated */ 566 /* from RTL code. */ 567 /* */ 568 /* Begin machine generated definitions. */ 569 /****************************************************************************/ 570 571 /* 572 * tx_bd definition 573 */ 574 struct tx_bd { 575 uint32_t tx_bd_haddr_hi; 576 uint32_t tx_bd_haddr_lo; 577 uint32_t tx_bd_mss_nbytes; 578 uint16_t tx_bd_flags; 579 uint16_t tx_bd_vlan_tag; 580 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 581 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 582 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 583 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 584 #define TX_BD_FLAGS_COAL_NOW (1<<4) 585 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 586 #define TX_BD_FLAGS_END (1<<6) 587 #define TX_BD_FLAGS_START (1<<7) 588 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 589 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 590 #define TX_BD_FLAGS_SW_SNAP (1<<14) 591 #define TX_BD_FLAGS_SW_LSO (1<<15) 592 }; 593 594 595 /* 596 * rx_bd definition 597 */ 598 struct rx_bd { 599 uint32_t rx_bd_haddr_hi; 600 uint32_t rx_bd_haddr_lo; 601 uint32_t rx_bd_len; 602 uint32_t rx_bd_flags; 603 #define RX_BD_FLAGS_NOPUSH (1<<0) 604 #define RX_BD_FLAGS_DUMMY (1<<1) 605 #define RX_BD_FLAGS_END (1<<2) 606 #define RX_BD_FLAGS_START (1<<3) 607 }; 608 609 610 /* 611 * status_block definition 612 */ 613 struct status_block { 614 uint32_t status_attn_bits; 615 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 616 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 617 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 618 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 619 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 620 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 621 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 622 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 623 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 624 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 625 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 626 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 627 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 628 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 629 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 630 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 631 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 632 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 633 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 634 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 635 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 636 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 637 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 638 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 639 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 640 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 641 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 642 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 643 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 644 645 uint32_t status_attn_bits_ack; 646 #if BYTE_ORDER == BIG_ENDIAN 647 uint16_t status_tx_quick_consumer_index0; 648 uint16_t status_tx_quick_consumer_index1; 649 uint16_t status_tx_quick_consumer_index2; 650 uint16_t status_tx_quick_consumer_index3; 651 uint16_t status_rx_quick_consumer_index0; 652 uint16_t status_rx_quick_consumer_index1; 653 uint16_t status_rx_quick_consumer_index2; 654 uint16_t status_rx_quick_consumer_index3; 655 uint16_t status_rx_quick_consumer_index4; 656 uint16_t status_rx_quick_consumer_index5; 657 uint16_t status_rx_quick_consumer_index6; 658 uint16_t status_rx_quick_consumer_index7; 659 uint16_t status_rx_quick_consumer_index8; 660 uint16_t status_rx_quick_consumer_index9; 661 uint16_t status_rx_quick_consumer_index10; 662 uint16_t status_rx_quick_consumer_index11; 663 uint16_t status_rx_quick_consumer_index12; 664 uint16_t status_rx_quick_consumer_index13; 665 uint16_t status_rx_quick_consumer_index14; 666 uint16_t status_rx_quick_consumer_index15; 667 uint16_t status_completion_producer_index; 668 uint16_t status_cmd_consumer_index; 669 uint16_t status_idx; 670 uint16_t status_unused; 671 #else 672 uint16_t status_tx_quick_consumer_index1; 673 uint16_t status_tx_quick_consumer_index0; 674 uint16_t status_tx_quick_consumer_index3; 675 uint16_t status_tx_quick_consumer_index2; 676 uint16_t status_rx_quick_consumer_index1; 677 uint16_t status_rx_quick_consumer_index0; 678 uint16_t status_rx_quick_consumer_index3; 679 uint16_t status_rx_quick_consumer_index2; 680 uint16_t status_rx_quick_consumer_index5; 681 uint16_t status_rx_quick_consumer_index4; 682 uint16_t status_rx_quick_consumer_index7; 683 uint16_t status_rx_quick_consumer_index6; 684 uint16_t status_rx_quick_consumer_index9; 685 uint16_t status_rx_quick_consumer_index8; 686 uint16_t status_rx_quick_consumer_index11; 687 uint16_t status_rx_quick_consumer_index10; 688 uint16_t status_rx_quick_consumer_index13; 689 uint16_t status_rx_quick_consumer_index12; 690 uint16_t status_rx_quick_consumer_index15; 691 uint16_t status_rx_quick_consumer_index14; 692 uint16_t status_cmd_consumer_index; 693 uint16_t status_completion_producer_index; 694 uint16_t status_unused; 695 uint16_t status_idx; 696 #endif 697 }; 698 699 700 struct status_block_msix { 701 #if BYTE_ORDER == BIG_ENDIAN 702 uint16_t status_tx_quick_consumer_index; 703 uint16_t status_rx_quick_consumer_index; 704 uint16_t status_completion_producer_index; 705 uint16_t status_cmd_consumer_index; 706 uint32_t status_unused; 707 uint16_t status_idx; 708 uint8_t status_unused2; 709 uint8_t status_blk_num; 710 #else 711 uint16_t status_rx_quick_consumer_index; 712 uint16_t status_tx_quick_consumer_index; 713 uint16_t status_cmd_consumer_index; 714 uint16_t status_completion_producer_index; 715 uint32_t status_unused; 716 uint8_t status_blk_num; 717 uint8_t status_unused2; 718 uint16_t status_idx; 719 #endif 720 }; 721 722 #define BCE_STATUS_BLK_MSIX_ALIGN 128 723 724 725 /* 726 * statistics_block definition 727 */ 728 struct statistics_block { 729 uint32_t stat_IfHCInOctets_hi; 730 uint32_t stat_IfHCInOctets_lo; 731 uint32_t stat_IfHCInBadOctets_hi; 732 uint32_t stat_IfHCInBadOctets_lo; 733 uint32_t stat_IfHCOutOctets_hi; 734 uint32_t stat_IfHCOutOctets_lo; 735 uint32_t stat_IfHCOutBadOctets_hi; 736 uint32_t stat_IfHCOutBadOctets_lo; 737 uint32_t stat_IfHCInUcastPkts_hi; 738 uint32_t stat_IfHCInUcastPkts_lo; 739 uint32_t stat_IfHCInMulticastPkts_hi; 740 uint32_t stat_IfHCInMulticastPkts_lo; 741 uint32_t stat_IfHCInBroadcastPkts_hi; 742 uint32_t stat_IfHCInBroadcastPkts_lo; 743 uint32_t stat_IfHCOutUcastPkts_hi; 744 uint32_t stat_IfHCOutUcastPkts_lo; 745 uint32_t stat_IfHCOutMulticastPkts_hi; 746 uint32_t stat_IfHCOutMulticastPkts_lo; 747 uint32_t stat_IfHCOutBroadcastPkts_hi; 748 uint32_t stat_IfHCOutBroadcastPkts_lo; 749 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 750 uint32_t stat_Dot3StatsCarrierSenseErrors; 751 uint32_t stat_Dot3StatsFCSErrors; 752 uint32_t stat_Dot3StatsAlignmentErrors; 753 uint32_t stat_Dot3StatsSingleCollisionFrames; 754 uint32_t stat_Dot3StatsMultipleCollisionFrames; 755 uint32_t stat_Dot3StatsDeferredTransmissions; 756 uint32_t stat_Dot3StatsExcessiveCollisions; 757 uint32_t stat_Dot3StatsLateCollisions; 758 uint32_t stat_EtherStatsCollisions; 759 uint32_t stat_EtherStatsFragments; 760 uint32_t stat_EtherStatsJabbers; 761 uint32_t stat_EtherStatsUndersizePkts; 762 uint32_t stat_EtherStatsOverrsizePkts; 763 uint32_t stat_EtherStatsPktsRx64Octets; 764 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; 765 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; 766 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; 767 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 768 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 769 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 770 uint32_t stat_EtherStatsPktsTx64Octets; 771 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; 772 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; 773 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; 774 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 775 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 776 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 777 uint32_t stat_XonPauseFramesReceived; 778 uint32_t stat_XoffPauseFramesReceived; 779 uint32_t stat_OutXonSent; 780 uint32_t stat_OutXoffSent; 781 uint32_t stat_FlowControlDone; 782 uint32_t stat_MacControlFramesReceived; 783 uint32_t stat_XoffStateEntered; 784 uint32_t stat_IfInFramesL2FilterDiscards; 785 uint32_t stat_IfInRuleCheckerDiscards; 786 uint32_t stat_IfInFTQDiscards; 787 uint32_t stat_IfInMBUFDiscards; 788 uint32_t stat_IfInRuleCheckerP4Hit; 789 uint32_t stat_CatchupInRuleCheckerDiscards; 790 uint32_t stat_CatchupInFTQDiscards; 791 uint32_t stat_CatchupInMBUFDiscards; 792 uint32_t stat_CatchupInRuleCheckerP4Hit; 793 uint32_t stat_GenStat00; 794 uint32_t stat_GenStat01; 795 uint32_t stat_GenStat02; 796 uint32_t stat_GenStat03; 797 uint32_t stat_GenStat04; 798 uint32_t stat_GenStat05; 799 uint32_t stat_GenStat06; 800 uint32_t stat_GenStat07; 801 uint32_t stat_GenStat08; 802 uint32_t stat_GenStat09; 803 uint32_t stat_GenStat10; 804 uint32_t stat_GenStat11; 805 uint32_t stat_GenStat12; 806 uint32_t stat_GenStat13; 807 uint32_t stat_GenStat14; 808 uint32_t stat_GenStat15; 809 }; 810 811 812 /* 813 * l2_fhdr definition 814 */ 815 struct l2_fhdr { 816 uint32_t l2_fhdr_status; 817 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 818 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 819 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 820 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 821 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 822 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 823 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 824 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 825 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 826 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 827 828 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 829 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 830 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 831 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 832 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 833 #define L2_FHDR_ERRORS_IPV4_BAD_LEN (1<<22) 834 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 835 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 836 837 uint32_t l2_fhdr_hash; 838 #if BYTE_ORDER == BIG_ENDIAN 839 uint16_t l2_fhdr_pkt_len; 840 uint16_t l2_fhdr_vlan_tag; 841 uint16_t l2_fhdr_ip_xsum; 842 uint16_t l2_fhdr_tcp_udp_xsum; 843 #else 844 uint16_t l2_fhdr_vlan_tag; 845 uint16_t l2_fhdr_pkt_len; 846 uint16_t l2_fhdr_tcp_udp_xsum; 847 uint16_t l2_fhdr_ip_xsum; 848 #endif 849 }; 850 851 852 /* 853 * l2_tx_context definition (5706 and 5708) 854 */ 855 #define BCE_L2CTX_TX_TYPE 0x00000000 856 #define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 857 #define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28) 858 #define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28) 859 #define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28) 860 861 #define BCE_L2CTX_TX_HOST_BIDX 0x00000088 862 #define BCE_L2CTX_TX_EST_NBD 0x00000088 863 #define BCE_L2CTX_TX_CMD_TYPE 0x00000088 864 #define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24) 865 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24) 866 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24) 867 868 #define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 869 #define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094 870 #define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098 871 #define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c 872 #define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c 873 #define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0 874 #define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4 875 #define BCE_L2CTX_TX_TXP_BOFF 0x000000a8 876 #define BCE_L2CTX_TX_TXP_BIDX 0x000000a8 877 #define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac 878 879 /* 880 * l2_tx_context definition (5709 and 5716) 881 */ 882 #define BCE_L2CTX_TX_TYPE_XI 0x00000080 883 #define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16) 884 #define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28) 885 #define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28) 886 #define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28) 887 888 #define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240 889 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24) 890 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24) 891 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24) 892 893 #define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240 894 #define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248 895 #define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258 896 #define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c 897 898 899 /* 900 * l2_rx_context definition (5706, 5708, 5709, and 5716) 901 */ 902 #define BCE_L2CTX_RX_WATER_MARK 0x00000000 903 #define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0 904 #define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 905 #define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4 906 #define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0 907 #define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4 908 #define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16 909 #define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff 910 911 #define BCE_L2CTX_RX_BD_PRE_READ 0x00000000 912 #define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8 913 914 #define BCE_L2CTX_RX_CTX_SIZE 0x00000000 915 #define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16 916 #define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT) 917 918 #define BCE_L2CTX_RX_CTX_TYPE 0x00000000 919 #define BCE_L2CTX_RX_CTX_TYPE_SHIFT 24 920 921 #define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 922 #define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 923 #define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 924 925 #define BCE_L2CTX_RX_HOST_BDIDX 0x00000004 926 #define BCE_L2CTX_RX_HOST_BSEQ 0x00000008 927 #define BCE_L2CTX_RX_NX_BSEQ 0x0000000c 928 #define BCE_L2CTX_RX_NX_BDHADDR_HI 0x00000010 929 #define BCE_L2CTX_RX_NX_BDHADDR_LO 0x00000014 930 #define BCE_L2CTX_RX_NX_BDIDX 0x00000018 931 932 #define BCE_L2CTX_RX_HOST_PG_BDIDX 0x00000044 933 #define BCE_L2CTX_RX_PG_BUF_SIZE 0x00000048 934 #define BCE_L2CTX_RX_RBDC_KEY 0x0000004c 935 #define BCE_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe 936 #define BCE_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050 937 #define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054 938 #define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058 939 940 941 /* 942 * l2_mq definitions (5706, 5708, 5709, and 5716) 943 */ 944 #define BCE_L2MQ_RX_HOST_BDIDX 0x00000004 945 #define BCE_L2MQ_RX_HOST_BSEQ 0x00000008 946 #define BCE_L2MQ_RX_HOST_PG_BDIDX 0x00000044 947 948 #define BCE_L2MQ_TX_HOST_BIDX 0x00000088 949 #define BCE_L2MQ_TX_HOST_BSEQ 0x00000090 950 951 952 /* 953 * pci_config_l definition 954 * offset: 0000 955 */ 956 #define BCE_PCICFG_MSI_CONTROL 0x00000058 957 #define BCE_PCICFG_MSI_CONTROL_ENABLE (1L<<16) 958 959 #define BCE_PCICFG_MISC_CONFIG 0x00000068 960 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 961 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 962 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 963 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 964 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 965 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 966 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 967 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 968 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 969 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 970 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 971 972 #define BCE_PCICFG_MISC_STATUS 0x0000006c 973 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 974 #define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 975 #define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 976 #define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 977 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 978 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 979 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 980 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 981 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 982 983 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 984 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 985 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 986 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 987 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 988 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 989 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 990 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 991 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 992 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 993 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 994 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 995 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 996 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 997 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 998 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 999 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1000 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1001 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1002 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1003 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1004 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1005 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1006 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1007 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1008 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1009 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1010 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1011 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1012 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1013 1014 #define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1015 #define BCE_PCICFG_REG_WINDOW 0x00000080 1016 #define BCE_PCICFG_INT_ACK_CMD 0x00000084 1017 #define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1018 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1019 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1020 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1021 1022 #define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1023 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1024 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1025 #define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1026 1027 1028 /* 1029 * pci_reg definition 1030 * offset: 0x400 1031 */ 1032 #define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1033 #define BCE_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13) 1034 #define BCE_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31) 1035 1036 #define BCE_PCI_GRC_WINDOW2_BASE 0xc000 1037 #define BCE_PCI_GRC_WINDOW3_BASE 0xe000 1038 1039 #define BCE_PCI_CONFIG_1 0x00000404 1040 #define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1041 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1042 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1043 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1044 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1045 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1046 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1047 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1048 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1049 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1050 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1051 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1052 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1053 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1054 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1055 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1056 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1057 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1058 1059 #define BCE_PCI_CONFIG_2 0x00000408 1060 #define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1061 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1062 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1063 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1064 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1065 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1066 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1067 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1068 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1069 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1070 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1071 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1072 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1073 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1074 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1075 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1076 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1077 #define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1078 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1079 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1080 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1081 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1082 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1083 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1084 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1085 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1086 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1087 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1088 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1089 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1090 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1091 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1092 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1093 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1094 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1095 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1096 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1097 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1098 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1099 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1100 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1101 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1102 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1103 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1104 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1105 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1106 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1107 1108 #define BCE_PCI_CONFIG_3 0x0000040c 1109 #define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1110 #define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1111 #define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1112 #define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1113 #define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1114 #define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1115 #define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1116 1117 #define BCE_PCI_PM_DATA_A 0x00000410 1118 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1119 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1120 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1121 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1122 1123 #define BCE_PCI_PM_DATA_B 0x00000414 1124 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1125 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1126 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1127 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1128 1129 #define BCE_PCI_SWAP_DIAG0 0x00000418 1130 #define BCE_PCI_SWAP_DIAG1 0x0000041c 1131 #define BCE_PCI_EXP_ROM_ADDR 0x00000420 1132 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1133 #define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1134 1135 #define BCE_PCI_EXP_ROM_DATA 0x00000424 1136 #define BCE_PCI_VPD_INTF 0x00000428 1137 #define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1138 1139 #define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1140 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1141 #define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1142 1143 #define BCE_PCI_VPD_DATA 0x00000430 1144 #define BCE_PCI_ID_VAL1 0x00000434 1145 #define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1146 #define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1147 1148 #define BCE_PCI_ID_VAL2 0x00000438 1149 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1150 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1151 1152 #define BCE_PCI_ID_VAL3 0x0000043c 1153 #define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1154 #define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1155 1156 #define BCE_PCI_ID_VAL4 0x00000440 1157 #define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1158 #define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1159 #define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1160 #define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1161 #define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1162 #define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1163 #define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1164 #define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1165 #define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1166 #define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1167 #define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1168 #define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1169 #define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1170 #define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1171 #define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1172 #define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1173 #define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1174 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1175 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1176 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1177 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1178 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1179 #define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1180 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1181 #define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1182 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1183 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1184 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1185 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1186 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1187 1188 #define BCE_PCI_ID_VAL5 0x00000444 1189 #define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1190 #define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1191 #define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1192 #define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1193 #define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1194 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1195 1196 #define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1197 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1198 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1199 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1200 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1201 1202 #define BCE_PCI_ID_VAL6 0x0000044c 1203 #define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1204 #define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1205 #define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1206 1207 #define BCE_PCI_MSI_DATA 0x00000450 1208 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1209 1210 #define BCE_PCI_MSI_ADDR_H 0x00000454 1211 #define BCE_PCI_MSI_ADDR_L 0x00000458 1212 1213 #define BCE_PCI_MSIX_CONTROL 0x000004c0 1214 #define BCE_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0) 1215 #define BCE_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11) 1216 1217 #define BCE_PCI_MSIX_TBL_OFF_BIR 0x000004c4 1218 #define BCE_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0) 1219 #define BCE_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3) 1220 1221 #define BCE_PCI_MSIX_PBA_OFF_BIT 0x000004c8 1222 #define BCE_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0) 1223 #define BCE_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3) 1224 1225 #define BCE_PCI_GRC_WINDOW2_ADDR 0x00000614 1226 #define BCE_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13) 1227 1228 #define BCE_PCI_GRC_WINDOW3_ADDR 0x00000618 1229 #define BCE_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13) 1230 1231 #define BCE_MSIX_TABLE_ADDR 0x318000 1232 #define BCE_MSIX_PBA_ADDR 0x31c000 1233 1234 /* 1235 * misc_reg definition 1236 * offset: 0x800 1237 */ 1238 #define BCE_MISC_COMMAND 0x00000800 1239 #define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1240 #define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1241 #define BCE_MISC_COMMAND_SW_RESET (1L<<4) 1242 #define BCE_MISC_COMMAND_POR_RESET (1L<<5) 1243 #define BCE_MISC_COMMAND_HD_RESET (1L<<6) 1244 #define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7) 1245 #define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1246 #define BCE_MISC_COMMAND_CS16_ERR (1L<<9) 1247 #define BCE_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12) 1248 #define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1249 #define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23) 1250 #define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24) 1251 #define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25) 1252 #define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26) 1253 #define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27) 1254 #define BCE_MISC_COMMAND_PCIE_DIS (1L<<28) 1255 1256 #define BCE_MISC_CFG 0x00000804 1257 #define BCE_MISC_CFG_GRC_TMOUT (1L<<0) 1258 #define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1259 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1260 #define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1261 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1262 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1263 #define BCE_MISC_CFG_BIST_EN (1L<<3) 1264 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1265 #define BCE_MISC_CFG_RESERVED5_TE (1L<<5) 1266 #define BCE_MISC_CFG_RESERVED6_TE (1L<<6) 1267 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1268 #define BCE_MISC_CFG_LEDMODE (0x7L<<8) 1269 #define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1270 #define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8) 1271 #define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8) 1272 #define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8) 1273 #define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8) 1274 #define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8) 1275 #define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8) 1276 #define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8) 1277 #define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11) 1278 #define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12) 1279 #define BCE_MISC_CFG_LEDMODE_XI (0xfL<<8) 1280 #define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8) 1281 #define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8) 1282 #define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8) 1283 #define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8) 1284 #define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8) 1285 #define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8) 1286 #define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8) 1287 #define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8) 1288 #define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8) 1289 #define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8) 1290 #define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8) 1291 #define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8) 1292 #define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8) 1293 #define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8) 1294 #define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8) 1295 #define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8) 1296 #define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13) 1297 #define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14) 1298 1299 #define BCE_MISC_ID 0x00000808 1300 #define BCE_MISC_ID_BOND_ID (0xfL<<0) 1301 #define BCE_MISC_ID_BOND_ID_X (0L<<0) 1302 #define BCE_MISC_ID_BOND_ID_C (3L<<0) 1303 #define BCE_MISC_ID_BOND_ID_S (12L<<0) 1304 #define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1305 #define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1306 #define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1307 1308 #define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1309 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1310 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1311 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1312 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1313 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1314 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1315 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1316 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1317 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1318 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1319 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1320 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1321 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1322 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1323 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1324 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1325 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1326 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1327 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1328 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1329 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1330 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1331 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1332 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1333 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1334 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1335 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1336 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1337 #define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1338 #define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1339 1340 #define BCE_MISC_ENABLE_SET_BITS 0x00000810 1341 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1342 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1343 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1344 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1345 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1346 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1347 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1348 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1349 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1350 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1351 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1352 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1353 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1354 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1355 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1356 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1357 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1358 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1359 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1360 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1361 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1362 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1363 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1364 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1365 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1366 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1367 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1368 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1369 #define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1370 #define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1371 1372 #define BCE_MISC_ENABLE_DEFAULT 0x05ffffff 1373 #define BCE_MISC_ENABLE_DEFAULT_XI 0x17ffffff 1374 1375 #define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1376 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1377 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1378 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1379 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1380 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1381 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1382 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1383 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1384 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1385 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1386 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1387 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1388 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1389 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1390 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1391 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1392 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1393 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1394 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1395 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1396 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1397 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1398 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1399 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1400 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1401 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1402 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1403 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1404 #define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1405 #define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1406 1407 #define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff 1408 1409 #define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1410 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1411 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1412 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1413 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1414 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1415 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1416 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1417 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1418 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1419 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1420 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1421 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1422 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1423 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1424 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1425 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1426 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1427 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8) 1428 #define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11) 1429 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1430 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1431 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1432 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1433 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1434 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1435 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12) 1436 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1437 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17) 1438 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18) 1439 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19) 1440 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20) 1441 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17) 1442 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18) 1443 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24) 1444 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27) 1445 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28) 1446 1447 #define BCE_MISC_SPIO 0x0000081c 1448 #define BCE_MISC_SPIO_VALUE (0xffL<<0) 1449 #define BCE_MISC_SPIO_SET (0xffL<<8) 1450 #define BCE_MISC_SPIO_CLR (0xffL<<16) 1451 #define BCE_MISC_SPIO_FLOAT (0xffL<<24) 1452 1453 #define BCE_MISC_SPIO_INT 0x00000820 1454 #define BCE_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0) 1455 #define BCE_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8) 1456 #define BCE_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16) 1457 #define BCE_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24) 1458 #define BCE_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0) 1459 #define BCE_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8) 1460 #define BCE_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16) 1461 #define BCE_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24) 1462 1463 #define BCE_MISC_CONFIG_LFSR 0x00000824 1464 #define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1465 1466 #define BCE_MISC_LFSR_MASK_BITS 0x00000828 1467 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1468 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1469 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1470 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1471 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1472 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1473 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1474 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1475 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1476 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1477 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1478 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1479 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1480 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1481 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1482 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1483 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1484 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1485 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1486 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1487 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1488 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1489 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1490 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1491 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1492 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1493 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1494 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1495 #define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1496 #define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1497 1498 #define BCE_MISC_ARB_REQ0 0x0000082c 1499 #define BCE_MISC_ARB_REQ1 0x00000830 1500 #define BCE_MISC_ARB_REQ2 0x00000834 1501 #define BCE_MISC_ARB_REQ3 0x00000838 1502 #define BCE_MISC_ARB_REQ4 0x0000083c 1503 #define BCE_MISC_ARB_FREE0 0x00000840 1504 #define BCE_MISC_ARB_FREE1 0x00000844 1505 #define BCE_MISC_ARB_FREE2 0x00000848 1506 #define BCE_MISC_ARB_FREE3 0x0000084c 1507 #define BCE_MISC_ARB_FREE4 0x00000850 1508 #define BCE_MISC_ARB_REQ_STATUS0 0x00000854 1509 #define BCE_MISC_ARB_REQ_STATUS1 0x00000858 1510 #define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 1511 #define BCE_MISC_ARB_REQ_STATUS3 0x00000860 1512 #define BCE_MISC_ARB_REQ_STATUS4 0x00000864 1513 #define BCE_MISC_ARB_GNT0 0x00000868 1514 #define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 1515 #define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 1516 #define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 1517 #define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 1518 #define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 1519 #define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 1520 #define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 1521 #define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 1522 1523 #define BCE_MISC_ARB_GNT1 0x0000086c 1524 #define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 1525 #define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 1526 #define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 1527 #define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 1528 #define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 1529 #define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 1530 #define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 1531 #define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 1532 1533 #define BCE_MISC_ARB_GNT2 0x00000870 1534 #define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 1535 #define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 1536 #define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 1537 #define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 1538 #define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 1539 #define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 1540 #define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 1541 #define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 1542 1543 #define BCE_MISC_ARB_GNT3 0x00000874 1544 #define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 1545 #define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 1546 #define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 1547 #define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 1548 #define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 1549 #define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 1550 #define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 1551 #define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 1552 1553 #define BCE_MISC_RESERVED1 0x00000878 1554 #define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0) 1555 1556 #define BCE_MISC_RESERVED2 0x0000087c 1557 #define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0) 1558 #define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1) 1559 1560 #define BCE_MISC_SM_ASF_CONTROL 0x00000880 1561 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1562 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1563 #define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1564 #define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1565 #define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1566 #define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1567 #define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1568 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1569 #define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8) 1570 #define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9) 1571 #define BCE_MISC_SM_ASF_CONTROL_RES (0x3L<<10) 1572 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1573 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1574 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1575 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1576 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16) 1577 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23) 1578 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1579 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1580 1581 #define BCE_MISC_SMB_IN 0x00000884 1582 #define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 1583 #define BCE_MISC_SMB_IN_RDY (1L<<8) 1584 #define BCE_MISC_SMB_IN_DONE (1L<<9) 1585 #define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1586 #define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 1587 #define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1588 #define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1589 #define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1590 #define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1591 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1592 1593 #define BCE_MISC_SMB_OUT 0x00000888 1594 #define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1595 #define BCE_MISC_SMB_OUT_RDY (1L<<8) 1596 #define BCE_MISC_SMB_OUT_START (1L<<9) 1597 #define BCE_MISC_SMB_OUT_LAST (1L<<10) 1598 #define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1599 #define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 1600 #define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1601 #define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1602 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1603 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1604 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1605 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1606 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1607 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1608 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1609 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20) 1610 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1611 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1612 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1613 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1614 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1615 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1616 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1617 1618 #define BCE_MISC_SMB_WATCHDOG 0x0000088c 1619 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1620 1621 #define BCE_MISC_SMB_HEARTBEAT 0x00000890 1622 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1623 1624 #define BCE_MISC_SMB_POLL_ASF 0x00000894 1625 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1626 1627 #define BCE_MISC_SMB_POLL_LEGACY 0x00000898 1628 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1629 1630 #define BCE_MISC_SMB_RETRAN 0x0000089c 1631 #define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1632 1633 #define BCE_MISC_SMB_TIMESTAMP 0x000008a0 1634 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1635 1636 #define BCE_MISC_PERR_ENA0 0x000008a4 1637 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1638 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1639 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1640 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1641 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1642 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1643 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1644 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1645 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1646 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1647 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1648 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1649 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1650 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1651 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1652 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1653 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1654 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1655 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1656 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1657 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1658 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1659 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1660 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1661 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1662 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1663 #define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1664 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1665 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1666 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1667 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1668 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1669 #define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0) 1670 #define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1) 1671 #define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2) 1672 #define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3) 1673 #define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4) 1674 #define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5) 1675 #define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6) 1676 #define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7) 1677 #define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8) 1678 #define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9) 1679 #define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10) 1680 #define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11) 1681 #define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12) 1682 #define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13) 1683 #define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14) 1684 #define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15) 1685 #define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16) 1686 #define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17) 1687 #define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18) 1688 #define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19) 1689 #define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20) 1690 #define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21) 1691 #define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22) 1692 #define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23) 1693 #define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24) 1694 #define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25) 1695 #define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26) 1696 #define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27) 1697 #define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28) 1698 #define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29) 1699 #define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30) 1700 #define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31) 1701 1702 #define BCE_MISC_PERR_ENA1 0x000008a8 1703 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1704 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1705 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1706 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1707 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1708 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1709 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1710 #define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1711 #define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1712 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1713 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1714 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1715 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1716 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1717 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1718 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1719 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1720 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1721 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1722 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1723 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1724 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1725 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1726 #define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1727 #define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1728 #define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1729 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1730 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1731 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1732 #define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1733 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1734 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1735 #define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0) 1736 #define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2) 1737 #define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3) 1738 #define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4) 1739 #define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5) 1740 #define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6) 1741 #define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7) 1742 #define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8) 1743 #define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9) 1744 #define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10) 1745 #define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11) 1746 #define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12) 1747 #define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13) 1748 #define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14) 1749 #define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15) 1750 #define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16) 1751 #define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17) 1752 #define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18) 1753 #define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19) 1754 #define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20) 1755 #define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21) 1756 #define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22) 1757 #define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23) 1758 #define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24) 1759 #define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25) 1760 #define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26) 1761 #define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27) 1762 #define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28) 1763 #define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29) 1764 1765 #define BCE_MISC_PERR_ENA2 0x000008ac 1766 #define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1767 #define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1768 #define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1769 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1770 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1771 #define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1772 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1773 #define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1774 #define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1775 #define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0) 1776 #define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1) 1777 #define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2) 1778 #define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3) 1779 #define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4) 1780 #define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5) 1781 #define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6) 1782 1783 #define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 1784 #define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1785 #define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1786 #define BCE_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15) 1787 1788 #define BCE_MISC_VREG_CONTROL 0x000008b4 1789 #define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1790 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0) 1791 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0) 1792 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0) 1793 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0) 1794 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0) 1795 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0) 1796 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0) 1797 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0) 1798 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0) 1799 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0) 1800 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0) 1801 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0) 1802 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0) 1803 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0) 1804 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0) 1805 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0) 1806 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0) 1807 #define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1808 #define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4) 1809 #define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4) 1810 #define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4) 1811 #define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4) 1812 #define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4) 1813 #define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4) 1814 #define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4) 1815 #define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4) 1816 #define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4) 1817 #define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4) 1818 #define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4) 1819 #define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4) 1820 #define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4) 1821 #define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4) 1822 #define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4) 1823 #define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4) 1824 #define BCE_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8) 1825 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8) 1826 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8) 1827 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8) 1828 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8) 1829 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8) 1830 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8) 1831 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8) 1832 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8) 1833 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8) 1834 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8) 1835 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8) 1836 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8) 1837 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8) 1838 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8) 1839 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8) 1840 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8) 1841 1842 #define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1843 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1844 1845 #define BCE_MISC_GP_HW_CTL0 0x000008bc 1846 #define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0) 1847 #define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1) 1848 #define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2) 1849 #define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3) 1850 #define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4) 1851 #define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5) 1852 #define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6) 1853 #define BCE_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4) 1854 #define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7) 1855 #define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8) 1856 #define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9) 1857 #define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10) 1858 #define BCE_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8) 1859 #define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11) 1860 #define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12) 1861 #define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13) 1862 #define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14) 1863 #define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15) 1864 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16) 1865 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16) 1866 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16) 1867 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16) 1868 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16) 1869 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16) 1870 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16) 1871 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20) 1872 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21) 1873 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22) 1874 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22) 1875 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22) 1876 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22) 1877 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22) 1878 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24) 1879 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24) 1880 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24) 1881 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24) 1882 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24) 1883 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26) 1884 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26) 1885 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26) 1886 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26) 1887 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26) 1888 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28) 1889 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28) 1890 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28) 1891 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28) 1892 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28) 1893 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30) 1894 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30) 1895 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30) 1896 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30) 1897 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30) 1898 1899 #define BCE_MISC_GP_HW_CTL1 0x000008c0 1900 #define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0) 1901 #define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1) 1902 #define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2) 1903 #define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3) 1904 #define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0) 1905 #define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16) 1906 1907 #define BCE_MISC_NEW_HW_CTL 0x000008c4 1908 #define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0) 1909 #define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1) 1910 #define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2) 1911 #define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3) 1912 #define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4) 1913 #define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16) 1914 1915 #define BCE_MISC_NEW_CORE_CTL 0x000008c8 1916 #define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) 1917 #define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) 1918 #define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16) 1919 #define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) 1920 #define BCE_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) 1921 1922 #define BCE_MISC_ECO_HW_CTL 0x000008cc 1923 #define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0) 1924 #define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1) 1925 #define BCE_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16) 1926 1927 #define BCE_MISC_ECO_CORE_CTL 0x000008d0 1928 #define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0) 1929 #define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16) 1930 1931 #define BCE_MISC_PPIO 0x000008d4 1932 #define BCE_MISC_PPIO_VALUE (0xfL<<0) 1933 #define BCE_MISC_PPIO_SET (0xfL<<8) 1934 #define BCE_MISC_PPIO_CLR (0xfL<<16) 1935 #define BCE_MISC_PPIO_FLOAT (0xfL<<24) 1936 1937 #define BCE_MISC_PPIO_INT 0x000008d8 1938 #define BCE_MISC_PPIO_INT_INT_STATE (0xfL<<0) 1939 #define BCE_MISC_PPIO_INT_OLD_VALUE (0xfL<<8) 1940 #define BCE_MISC_PPIO_INT_OLD_SET (0xfL<<16) 1941 #define BCE_MISC_PPIO_INT_OLD_CLR (0xfL<<24) 1942 1943 #define BCE_MISC_RESET_NUMS 0x000008dc 1944 #define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0) 1945 #define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4) 1946 #define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8) 1947 #define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12) 1948 #define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16) 1949 1950 #define BCE_MISC_CS16_ERR 0x000008e0 1951 #define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0) 1952 #define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1) 1953 #define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2) 1954 #define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3) 1955 #define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4) 1956 #define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5) 1957 #define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6) 1958 #define BCE_MISC_CS16_ERR_ENA_COM (1L<<7) 1959 #define BCE_MISC_CS16_ERR_ENA_CP (1L<<8) 1960 #define BCE_MISC_CS16_ERR_STA_PCI (1L<<16) 1961 #define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17) 1962 #define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18) 1963 #define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19) 1964 #define BCE_MISC_CS16_ERR_STA_CTX (1L<<20) 1965 #define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21) 1966 #define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22) 1967 #define BCE_MISC_CS16_ERR_STA_COM (1L<<23) 1968 #define BCE_MISC_CS16_ERR_STA_CP (1L<<24) 1969 1970 #define BCE_MISC_SPIO_EVENT 0x000008e4 1971 #define BCE_MISC_SPIO_EVENT_ENABLE (0xffL<<0) 1972 1973 #define BCE_MISC_PPIO_EVENT 0x000008e8 1974 #define BCE_MISC_PPIO_EVENT_ENABLE (0xfL<<0) 1975 1976 #define BCE_MISC_DUAL_MEDIA_CTRL 0x000008ec 1977 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0) 1978 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0) 1979 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0) 1980 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0) 1981 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8) 1982 #define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11) 1983 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12) 1984 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13) 1985 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14) 1986 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15) 1987 #define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16) 1988 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17) 1989 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18) 1990 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19) 1991 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20) 1992 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21) 1993 #define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24) 1994 #define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25) 1995 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26) 1996 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26) 1997 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26) 1998 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26) 1999 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26) 2000 2001 #define BCE_MISC_OTP_CMD1 0x000008f0 2002 #define BCE_MISC_OTP_CMD1_FMODE (0x7L<<0) 2003 #define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0) 2004 #define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0) 2005 #define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0) 2006 #define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0) 2007 #define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0) 2008 #define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0) 2009 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0) 2010 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0) 2011 #define BCE_MISC_OTP_CMD1_USEPINS (1L<<8) 2012 #define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9) 2013 #define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10) 2014 #define BCE_MISC_OTP_CMD1_PCOUNT (0x7L<<16) 2015 #define BCE_MISC_OTP_CMD1_PBYP (1L<<19) 2016 #define BCE_MISC_OTP_CMD1_VSEL (0xfL<<20) 2017 #define BCE_MISC_OTP_CMD1_TM (0x7L<<27) 2018 #define BCE_MISC_OTP_CMD1_SADBYP (1L<<30) 2019 #define BCE_MISC_OTP_CMD1_DEBUG (1L<<31) 2020 2021 #define BCE_MISC_OTP_CMD2 0x000008f4 2022 #define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0) 2023 #define BCE_MISC_OTP_CMD2_DOSEL (0x7fL<<16) 2024 #define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16) 2025 #define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16) 2026 #define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16) 2027 2028 #define BCE_MISC_OTP_STATUS 0x000008f8 2029 #define BCE_MISC_OTP_STATUS_DATA (0xffL<<0) 2030 #define BCE_MISC_OTP_STATUS_VALID (1L<<8) 2031 #define BCE_MISC_OTP_STATUS_BUSY (1L<<9) 2032 #define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10) 2033 #define BCE_MISC_OTP_STATUS_DONE (1L<<11) 2034 2035 #define BCE_MISC_OTP_SHIFT1_CMD 0x000008fc 2036 #define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0) 2037 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1) 2038 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2) 2039 #define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3) 2040 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8) 2041 2042 #define BCE_MISC_OTP_SHIFT1_DATA 0x00000900 2043 #define BCE_MISC_OTP_SHIFT2_CMD 0x00000904 2044 #define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0) 2045 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1) 2046 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2) 2047 #define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3) 2048 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8) 2049 2050 #define BCE_MISC_OTP_SHIFT2_DATA 0x00000908 2051 #define BCE_MISC_BIST_CS0 0x0000090c 2052 #define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0) 2053 #define BCE_MISC_BIST_CS0_BIST_SETUP (0x3L<<1) 2054 #define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3) 2055 #define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8) 2056 #define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9) 2057 #define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31) 2058 2059 #define BCE_MISC_BIST_MEMSTATUS0 0x00000910 2060 #define BCE_MISC_BIST_CS1 0x00000914 2061 #define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0) 2062 #define BCE_MISC_BIST_CS1_BIST_SETUP (0x3L<<1) 2063 #define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3) 2064 #define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8) 2065 #define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9) 2066 2067 #define BCE_MISC_BIST_MEMSTATUS1 0x00000918 2068 #define BCE_MISC_BIST_CS2 0x0000091c 2069 #define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0) 2070 #define BCE_MISC_BIST_CS2_BIST_SETUP (0x3L<<1) 2071 #define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3) 2072 #define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8) 2073 #define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9) 2074 2075 #define BCE_MISC_BIST_MEMSTATUS2 0x00000920 2076 #define BCE_MISC_BIST_CS3 0x00000924 2077 #define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0) 2078 #define BCE_MISC_BIST_CS3_BIST_SETUP (0x3L<<1) 2079 #define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3) 2080 #define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8) 2081 #define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9) 2082 2083 #define BCE_MISC_BIST_MEMSTATUS3 0x00000928 2084 #define BCE_MISC_BIST_CS4 0x0000092c 2085 #define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0) 2086 #define BCE_MISC_BIST_CS4_BIST_SETUP (0x3L<<1) 2087 #define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3) 2088 #define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8) 2089 #define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9) 2090 2091 #define BCE_MISC_BIST_MEMSTATUS4 0x00000930 2092 #define BCE_MISC_BIST_CS5 0x00000934 2093 #define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0) 2094 #define BCE_MISC_BIST_CS5_BIST_SETUP (0x3L<<1) 2095 #define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3) 2096 #define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8) 2097 #define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9) 2098 2099 #define BCE_MISC_BIST_MEMSTATUS5 0x00000938 2100 #define BCE_MISC_MEM_TM0 0x0000093c 2101 #define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0) 2102 #define BCE_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8) 2103 #define BCE_MISC_MEM_TM0_UMP_TM (0xffL<<16) 2104 #define BCE_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24) 2105 2106 #define BCE_MISC_USPLL_CTRL 0x00000940 2107 #define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0) 2108 #define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1) 2109 #define BCE_MISC_USPLL_CTRL_LCPX (0x3fL<<2) 2110 #define BCE_MISC_USPLL_CTRL_RX (0x3L<<8) 2111 #define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10) 2112 #define BCE_MISC_USPLL_CTRL_VCO_MG (0x3L<<11) 2113 #define BCE_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13) 2114 #define BCE_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16) 2115 #define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19) 2116 #define BCE_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20) 2117 #define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23) 2118 #define BCE_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24) 2119 #define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26) 2120 #define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27) 2121 #define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28) 2122 #define BCE_MISC_USPLL_CTRL_LOCK (1L<<29) 2123 2124 #define BCE_MISC_PERR_STATUS0 0x00000944 2125 #define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0) 2126 #define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1) 2127 #define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2) 2128 #define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3) 2129 #define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4) 2130 #define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5) 2131 #define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6) 2132 #define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7) 2133 #define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8) 2134 #define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9) 2135 #define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10) 2136 #define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11) 2137 #define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12) 2138 #define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13) 2139 #define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14) 2140 #define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15) 2141 #define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16) 2142 #define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17) 2143 #define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18) 2144 #define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19) 2145 #define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20) 2146 #define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21) 2147 #define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22) 2148 #define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23) 2149 #define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24) 2150 #define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25) 2151 #define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26) 2152 #define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27) 2153 #define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28) 2154 #define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29) 2155 #define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30) 2156 #define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31) 2157 2158 #define BCE_MISC_PERR_STATUS1 0x00000948 2159 #define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0) 2160 #define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2) 2161 #define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3) 2162 #define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4) 2163 #define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5) 2164 #define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6) 2165 #define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7) 2166 #define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8) 2167 #define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9) 2168 #define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10) 2169 #define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11) 2170 #define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12) 2171 #define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13) 2172 #define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14) 2173 #define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15) 2174 #define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16) 2175 #define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17) 2176 #define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18) 2177 #define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19) 2178 #define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20) 2179 #define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21) 2180 #define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22) 2181 #define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23) 2182 #define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24) 2183 #define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25) 2184 #define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26) 2185 #define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27) 2186 #define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28) 2187 #define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29) 2188 2189 #define BCE_MISC_PERR_STATUS2 0x0000094c 2190 #define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0) 2191 #define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1) 2192 #define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2) 2193 #define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3) 2194 #define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4) 2195 #define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5) 2196 #define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6) 2197 2198 #define BCE_MISC_LCPLL_CTRL0 0x00000950 2199 #define BCE_MISC_LCPLL_CTRL0_OAC (0x7L<<0) 2200 #define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0) 2201 #define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0) 2202 #define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0) 2203 #define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0) 2204 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3) 2205 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3) 2206 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3) 2207 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3) 2208 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3) 2209 #define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6) 2210 #define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8) 2211 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11) 2212 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11) 2213 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11) 2214 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11) 2215 #define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13) 2216 #define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14) 2217 #define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15) 2218 #define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16) 2219 #define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17) 2220 #define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18) 2221 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19) 2222 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20) 2223 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21) 2224 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22) 2225 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23) 2226 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24) 2227 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25) 2228 #define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26) 2229 #define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27) 2230 2231 #define BCE_MISC_LCPLL_CTRL1 0x00000954 2232 #define BCE_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0) 2233 #define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5) 2234 #define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6) 2235 #define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7) 2236 2237 #define BCE_MISC_LCPLL_STATUS 0x00000958 2238 #define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0) 2239 #define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1) 2240 #define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2) 2241 #define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3) 2242 #define BCE_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4) 2243 #define BCE_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7) 2244 #define BCE_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10) 2245 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15) 2246 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15) 2247 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15) 2248 2249 #define BCE_MISC_OSCFUNDS_CTRL 0x0000095c 2250 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5) 2251 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5) 2252 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5) 2253 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6) 2254 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6) 2255 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6) 2256 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6) 2257 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6) 2258 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8) 2259 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8) 2260 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8) 2261 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8) 2262 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8) 2263 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10) 2264 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10) 2265 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10) 2266 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10) 2267 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10) 2268 2269 2270 /* 2271 * dma_reg definition 2272 * offset: 0xc00 2273 */ 2274 #define BCE_DMA_COMMAND 0x00000c00 2275 #define BCE_DMA_COMMAND_ENABLE (1L<<0) 2276 2277 #define BCE_DMA_STATUS 0x00000c04 2278 #define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 2279 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 2280 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 2281 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 2282 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 2283 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 2284 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 2285 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 2286 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 2287 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 2288 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 2289 2290 #define BCE_DMA_CONFIG 0x00000c08 2291 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 2292 #define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 2293 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 2294 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 2295 #define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 2296 #define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 2297 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 2298 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 2299 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 2300 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 2301 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 2302 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 2303 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 2304 #define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 2305 #define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 2306 #define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 2307 #define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 2308 #define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 2309 #define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 2310 2311 #define BCE_DMA_BLACKOUT 0x00000c0c 2312 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 2313 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 2314 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 2315 2316 #define BCE_DMA_RCHAN_STAT 0x00000c30 2317 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2318 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 2319 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2320 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 2321 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2322 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 2323 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2324 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 2325 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2326 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 2327 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2328 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 2329 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2330 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 2331 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2332 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 2333 2334 #define BCE_DMA_WCHAN_STAT 0x00000c34 2335 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2336 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 2337 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2338 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 2339 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2340 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 2341 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2342 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 2343 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2344 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 2345 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2346 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 2347 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2348 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 2349 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2350 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 2351 2352 #define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 2353 #define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 2354 #define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 2355 #define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 2356 #define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 2357 #define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 2358 #define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 2359 #define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 2360 #define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 2361 2362 #define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 2363 #define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 2364 #define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 2365 #define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 2366 #define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 2367 #define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 2368 #define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2369 #define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2370 #define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2371 2372 #define BCE_DMA_RCHAN_STAT_00 0x00000c40 2373 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2374 2375 #define BCE_DMA_RCHAN_STAT_01 0x00000c44 2376 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2377 2378 #define BCE_DMA_RCHAN_STAT_02 0x00000c48 2379 #define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2380 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2381 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2382 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2383 2384 #define BCE_DMA_RCHAN_STAT_10 0x00000c4c 2385 #define BCE_DMA_RCHAN_STAT_11 0x00000c50 2386 #define BCE_DMA_RCHAN_STAT_12 0x00000c54 2387 #define BCE_DMA_RCHAN_STAT_20 0x00000c58 2388 #define BCE_DMA_RCHAN_STAT_21 0x00000c5c 2389 #define BCE_DMA_RCHAN_STAT_22 0x00000c60 2390 #define BCE_DMA_RCHAN_STAT_30 0x00000c64 2391 #define BCE_DMA_RCHAN_STAT_31 0x00000c68 2392 #define BCE_DMA_RCHAN_STAT_32 0x00000c6c 2393 #define BCE_DMA_RCHAN_STAT_40 0x00000c70 2394 #define BCE_DMA_RCHAN_STAT_41 0x00000c74 2395 #define BCE_DMA_RCHAN_STAT_42 0x00000c78 2396 #define BCE_DMA_RCHAN_STAT_50 0x00000c7c 2397 #define BCE_DMA_RCHAN_STAT_51 0x00000c80 2398 #define BCE_DMA_RCHAN_STAT_52 0x00000c84 2399 #define BCE_DMA_RCHAN_STAT_60 0x00000c88 2400 #define BCE_DMA_RCHAN_STAT_61 0x00000c8c 2401 #define BCE_DMA_RCHAN_STAT_62 0x00000c90 2402 #define BCE_DMA_RCHAN_STAT_70 0x00000c94 2403 #define BCE_DMA_RCHAN_STAT_71 0x00000c98 2404 #define BCE_DMA_RCHAN_STAT_72 0x00000c9c 2405 #define BCE_DMA_WCHAN_STAT_00 0x00000ca0 2406 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2407 2408 #define BCE_DMA_WCHAN_STAT_01 0x00000ca4 2409 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2410 2411 #define BCE_DMA_WCHAN_STAT_02 0x00000ca8 2412 #define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2413 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2414 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2415 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2416 2417 #define BCE_DMA_WCHAN_STAT_10 0x00000cac 2418 #define BCE_DMA_WCHAN_STAT_11 0x00000cb0 2419 #define BCE_DMA_WCHAN_STAT_12 0x00000cb4 2420 #define BCE_DMA_WCHAN_STAT_20 0x00000cb8 2421 #define BCE_DMA_WCHAN_STAT_21 0x00000cbc 2422 #define BCE_DMA_WCHAN_STAT_22 0x00000cc0 2423 #define BCE_DMA_WCHAN_STAT_30 0x00000cc4 2424 #define BCE_DMA_WCHAN_STAT_31 0x00000cc8 2425 #define BCE_DMA_WCHAN_STAT_32 0x00000ccc 2426 #define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2427 #define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2428 #define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2429 #define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2430 #define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2431 #define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2432 #define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2433 #define BCE_DMA_WCHAN_STAT_61 0x00000cec 2434 #define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2435 #define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2436 #define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2437 #define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2438 #define BCE_DMA_ARB_STAT_00 0x00000d00 2439 #define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2440 #define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2441 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2442 2443 #define BCE_DMA_ARB_STAT_01 0x00000d04 2444 #define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2445 #define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2446 #define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2447 #define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2448 #define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2449 #define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2450 #define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2451 #define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2452 2453 #define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2454 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2455 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2456 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2457 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2458 #define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2459 2460 #define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2461 #define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2462 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2463 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2464 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2465 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2466 #define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2467 2468 #define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2469 #define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2470 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2471 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2472 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2473 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2474 #define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2475 2476 #define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2477 2478 2479 /* 2480 * context_reg definition 2481 * offset: 0x1000 2482 */ 2483 #define BCE_CTX_COMMAND 0x00001000 2484 #define BCE_CTX_COMMAND_ENABLED (1L<<0) 2485 #define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1) 2486 #define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2) 2487 #define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3) 2488 #define BCE_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8) 2489 #define BCE_CTX_COMMAND_MEM_INIT (1L<<13) 2490 #define BCE_CTX_COMMAND_PAGE_SIZE (0xfL<<16) 2491 #define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16) 2492 #define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16) 2493 #define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16) 2494 #define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16) 2495 #define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16) 2496 #define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16) 2497 #define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16) 2498 #define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16) 2499 #define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16) 2500 #define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16) 2501 #define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16) 2502 #define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16) 2503 #define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16) 2504 2505 #define BCE_CTX_STATUS 0x00001004 2506 #define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 2507 #define BCE_CTX_STATUS_READ_STAT (1L<<16) 2508 #define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 2509 #define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2510 #define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2511 #define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20) 2512 #define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21) 2513 #define BCE_CTX_STATUS_MISS_STAT (1L<<22) 2514 #define BCE_CTX_STATUS_HIT_STAT (1L<<23) 2515 #define BCE_CTX_STATUS_DEAD_LOCK (1L<<24) 2516 #define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25) 2517 #define BCE_CTX_STATUS_INVALID_PAGE (1L<<26) 2518 2519 #define BCE_CTX_VIRT_ADDR 0x00001008 2520 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2521 2522 #define BCE_CTX_PAGE_TBL 0x0000100c 2523 #define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2524 2525 #define BCE_CTX_DATA_ADR 0x00001010 2526 #define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2527 2528 #define BCE_CTX_DATA 0x00001014 2529 #define BCE_CTX_LOCK 0x00001018 2530 #define BCE_CTX_LOCK_TYPE (0x7L<<0) 2531 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2532 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2533 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2534 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2535 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2536 #define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0) 2537 #define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0) 2538 #define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0) 2539 #define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0) 2540 #define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0) 2541 #define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2542 #define BCE_CTX_LOCK_GRANTED (1L<<26) 2543 #define BCE_CTX_LOCK_MODE (0x7L<<27) 2544 #define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2545 #define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2546 #define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 2547 #define BCE_CTX_LOCK_STATUS (1L<<30) 2548 #define BCE_CTX_LOCK_REQ (1L<<31) 2549 2550 #define BCE_CTX_CTX_CTRL 0x0000101c 2551 #define BCE_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2) 2552 #define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21) 2553 #define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23) 2554 #define BCE_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24) 2555 #define BCE_CTX_CTX_CTRL_ATTR (1L<<26) 2556 #define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30) 2557 #define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31) 2558 2559 #define BCE_CTX_CTX_DATA 0x00001020 2560 #define BCE_CTX_ACCESS_STATUS 0x00001040 2561 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2562 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2563 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2564 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2565 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2566 #define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0) 2567 #define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5) 2568 #define BCE_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10) 2569 2570 #define BCE_CTX_DBG_LOCK_STATUS 0x00001044 2571 #define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2572 #define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2573 2574 #define BCE_CTX_CACHE_CTRL_STATUS 0x00001048 2575 #define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0) 2576 #define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1) 2577 #define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6) 2578 #define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7) 2579 #define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13) 2580 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19) 2581 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20) 2582 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21) 2583 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22) 2584 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23) 2585 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24) 2586 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25) 2587 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26) 2588 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27) 2589 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28) 2590 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29) 2591 2592 #define BCE_CTX_CACHE_CTRL_SM_STATUS 0x0000104c 2593 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0) 2594 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3) 2595 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6) 2596 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9) 2597 #define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16) 2598 2599 #define BCE_CTX_CACHE_STATUS 0x00001050 2600 #define BCE_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0) 2601 #define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16) 2602 2603 #define BCE_CTX_DMA_STATUS 0x00001054 2604 #define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0) 2605 #define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2) 2606 #define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4) 2607 #define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6) 2608 #define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8) 2609 #define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10) 2610 #define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12) 2611 #define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14) 2612 #define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16) 2613 #define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18) 2614 #define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20) 2615 2616 #define BCE_CTX_REP_STATUS 0x00001058 2617 #define BCE_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0) 2618 #define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10) 2619 #define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16) 2620 #define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17) 2621 #define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18) 2622 2623 #define BCE_CTX_CKSUM_ERROR_STATUS 0x0000105c 2624 #define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0) 2625 #define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16) 2626 2627 #define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 2628 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2629 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2630 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2631 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14) 2632 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15) 2633 2634 #define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 2635 #define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 2636 #define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2637 #define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 2638 #define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 2639 #define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 2640 #define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2641 #define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2642 #define BCE_CTX_CHNL_LOCK_STATUS_9 0x000010a4 2643 2644 #define BCE_CTX_CACHE_DATA 0x000010c4 2645 #define BCE_CTX_HOST_PAGE_TBL_CTRL 0x000010c8 2646 #define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0) 2647 #define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30) 2648 #define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31) 2649 2650 #define BCE_CTX_HOST_PAGE_TBL_DATA0 0x000010cc 2651 #define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0) 2652 #define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8) 2653 2654 #define BCE_CTX_HOST_PAGE_TBL_DATA1 0x000010d0 2655 #define BCE_CTX_CAM_CTRL 0x000010d4 2656 #define BCE_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0) 2657 #define BCE_CTX_CAM_CTRL_RESET (1L<<27) 2658 #define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28) 2659 #define BCE_CTX_CAM_CTRL_SEARCH (1L<<29) 2660 #define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30) 2661 #define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31) 2662 2663 2664 /* 2665 * emac_reg definition 2666 * offset: 0x1400 2667 */ 2668 #define BCE_EMAC_MODE 0x00001400 2669 #define BCE_EMAC_MODE_RESET (1L<<0) 2670 #define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 2671 #define BCE_EMAC_MODE_PORT (0x3L<<2) 2672 #define BCE_EMAC_MODE_PORT_NONE (0L<<2) 2673 #define BCE_EMAC_MODE_PORT_MII (1L<<2) 2674 #define BCE_EMAC_MODE_PORT_GMII (2L<<2) 2675 #define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 2676 #define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 2677 #define BCE_EMAC_MODE_25G (1L<<5) 2678 #define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2679 #define BCE_EMAC_MODE_TX_BURST (1L<<8) 2680 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2681 #define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 2682 #define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 2683 #define BCE_EMAC_MODE_MPKT (1L<<18) 2684 #define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 2685 #define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 2686 2687 #define BCE_EMAC_STATUS 0x00001404 2688 #define BCE_EMAC_STATUS_LINK (1L<<11) 2689 #define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 2690 #define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 2691 #define BCE_EMAC_STATUS_MI_INT (1L<<23) 2692 #define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 2693 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2694 2695 #define BCE_EMAC_ATTENTION_ENA 0x00001408 2696 #define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 2697 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2698 #define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2699 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2700 2701 #define BCE_EMAC_LED 0x0000140c 2702 #define BCE_EMAC_LED_OVERRIDE (1L<<0) 2703 #define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2704 #define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 2705 #define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 2706 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2707 #define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2708 #define BCE_EMAC_LED_TRAFFIC (1L<<6) 2709 #define BCE_EMAC_LED_1000MB (1L<<7) 2710 #define BCE_EMAC_LED_100MB (1L<<8) 2711 #define BCE_EMAC_LED_10MB (1L<<9) 2712 #define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 2713 #define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 2714 #define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2715 2716 #define BCE_EMAC_MAC_MATCH0 0x00001410 2717 #define BCE_EMAC_MAC_MATCH1 0x00001414 2718 #define BCE_EMAC_MAC_MATCH2 0x00001418 2719 #define BCE_EMAC_MAC_MATCH3 0x0000141c 2720 #define BCE_EMAC_MAC_MATCH4 0x00001420 2721 #define BCE_EMAC_MAC_MATCH5 0x00001424 2722 #define BCE_EMAC_MAC_MATCH6 0x00001428 2723 #define BCE_EMAC_MAC_MATCH7 0x0000142c 2724 #define BCE_EMAC_MAC_MATCH8 0x00001430 2725 #define BCE_EMAC_MAC_MATCH9 0x00001434 2726 #define BCE_EMAC_MAC_MATCH10 0x00001438 2727 #define BCE_EMAC_MAC_MATCH11 0x0000143c 2728 #define BCE_EMAC_MAC_MATCH12 0x00001440 2729 #define BCE_EMAC_MAC_MATCH13 0x00001444 2730 #define BCE_EMAC_MAC_MATCH14 0x00001448 2731 #define BCE_EMAC_MAC_MATCH15 0x0000144c 2732 #define BCE_EMAC_MAC_MATCH16 0x00001450 2733 #define BCE_EMAC_MAC_MATCH17 0x00001454 2734 #define BCE_EMAC_MAC_MATCH18 0x00001458 2735 #define BCE_EMAC_MAC_MATCH19 0x0000145c 2736 #define BCE_EMAC_MAC_MATCH20 0x00001460 2737 #define BCE_EMAC_MAC_MATCH21 0x00001464 2738 #define BCE_EMAC_MAC_MATCH22 0x00001468 2739 #define BCE_EMAC_MAC_MATCH23 0x0000146c 2740 #define BCE_EMAC_MAC_MATCH24 0x00001470 2741 #define BCE_EMAC_MAC_MATCH25 0x00001474 2742 #define BCE_EMAC_MAC_MATCH26 0x00001478 2743 #define BCE_EMAC_MAC_MATCH27 0x0000147c 2744 #define BCE_EMAC_MAC_MATCH28 0x00001480 2745 #define BCE_EMAC_MAC_MATCH29 0x00001484 2746 #define BCE_EMAC_MAC_MATCH30 0x00001488 2747 #define BCE_EMAC_MAC_MATCH31 0x0000148c 2748 #define BCE_EMAC_BACKOFF_SEED 0x00001498 2749 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2750 2751 #define BCE_EMAC_RX_MTU_SIZE 0x0000149c 2752 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2753 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2754 2755 #define BCE_EMAC_SERDES_CNTL 0x000014a4 2756 #define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2757 #define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2758 #define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2759 #define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2760 #define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2761 #define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2762 #define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2763 #define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2764 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2765 #define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2766 #define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2767 #define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2768 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2769 #define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2770 #define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2771 #define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2772 2773 #define BCE_EMAC_SERDES_STATUS 0x000014a8 2774 #define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2775 #define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2776 2777 #define BCE_EMAC_MDIO_COMM 0x000014ac 2778 #define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2779 #define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2780 #define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2781 #define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2782 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2783 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2784 #define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2785 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2786 #define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 2787 #define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2788 #define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 2789 2790 #define BCE_EMAC_MDIO_STATUS 0x000014b0 2791 #define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 2792 #define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 2793 2794 #define BCE_EMAC_MDIO_MODE 0x000014b4 2795 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2796 #define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2797 #define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2798 #define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 2799 #define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2800 #define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 2801 #define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 2802 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2803 2804 #define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 2805 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2806 2807 #define BCE_EMAC_TX_MODE 0x000014bc 2808 #define BCE_EMAC_TX_MODE_RESET (1L<<0) 2809 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2810 #define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 2811 #define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2812 #define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2813 #define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2814 2815 #define BCE_EMAC_TX_STATUS 0x000014c0 2816 #define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 2817 #define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2818 #define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 2819 #define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 2820 #define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2821 2822 #define BCE_EMAC_TX_LENGTHS 0x000014c4 2823 #define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2824 #define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2825 #define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2826 2827 #define BCE_EMAC_RX_MODE 0x000014c8 2828 #define BCE_EMAC_RX_MODE_RESET (1L<<0) 2829 #define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 2830 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2831 #define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2832 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2833 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2834 #define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 2835 #define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2836 #define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2837 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2838 #define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2839 #define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 2840 2841 #define BCE_EMAC_RX_STATUS 0x000014cc 2842 #define BCE_EMAC_RX_STATUS_FFED (1L<<0) 2843 #define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2844 #define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2845 2846 #define BCE_EMAC_MULTICAST_HASH0 0x000014d0 2847 #define BCE_EMAC_MULTICAST_HASH1 0x000014d4 2848 #define BCE_EMAC_MULTICAST_HASH2 0x000014d8 2849 #define BCE_EMAC_MULTICAST_HASH3 0x000014dc 2850 #define BCE_EMAC_MULTICAST_HASH4 0x000014e0 2851 #define BCE_EMAC_MULTICAST_HASH5 0x000014e4 2852 #define BCE_EMAC_MULTICAST_HASH6 0x000014e8 2853 #define BCE_EMAC_MULTICAST_HASH7 0x000014ec 2854 #define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2855 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2856 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2857 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2858 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2859 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2860 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2861 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2862 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2863 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2864 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2865 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2866 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2867 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2868 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2869 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2870 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2871 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2872 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2873 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2874 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2875 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2876 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2877 #define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 2878 #define BCE_EMAC_RXMAC_DEBUG1 0x00001560 2879 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2880 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2881 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2882 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2883 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2884 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2885 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2886 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2887 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2888 2889 #define BCE_EMAC_RXMAC_DEBUG2 0x00001564 2890 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2891 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2892 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2893 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2894 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2895 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2896 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2897 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2898 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2899 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2900 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2901 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2902 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2903 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2904 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2905 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2906 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2907 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2908 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2909 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2910 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2911 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2912 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2913 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2914 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2915 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2916 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2917 2918 #define BCE_EMAC_RXMAC_DEBUG3 0x00001568 2919 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2920 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2921 2922 #define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 2923 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2924 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2925 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2926 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2927 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2928 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2929 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2930 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2931 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2932 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2933 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2934 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2935 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2936 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2937 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2938 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2939 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2940 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2941 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2942 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2943 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2944 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2945 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2946 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2947 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2948 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2949 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2950 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2951 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2952 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2953 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2954 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2955 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2956 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2957 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2958 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2959 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2960 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2961 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2962 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2963 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2964 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2965 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2966 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2967 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2968 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2969 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2970 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2971 #define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 2972 2973 #define BCE_EMAC_RXMAC_DEBUG5 0x00001570 2974 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2975 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2976 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2977 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2978 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2979 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2980 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2981 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2982 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2983 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2984 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2985 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2986 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2987 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2988 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2989 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2990 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2991 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2992 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2993 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2994 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2995 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2996 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2997 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2998 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2999 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 3000 3001 #define BCE_EMAC_RX_STAT_AC0 0x00001580 3002 #define BCE_EMAC_RX_STAT_AC1 0x00001584 3003 #define BCE_EMAC_RX_STAT_AC2 0x00001588 3004 #define BCE_EMAC_RX_STAT_AC3 0x0000158c 3005 #define BCE_EMAC_RX_STAT_AC4 0x00001590 3006 #define BCE_EMAC_RX_STAT_AC5 0x00001594 3007 #define BCE_EMAC_RX_STAT_AC6 0x00001598 3008 #define BCE_EMAC_RX_STAT_AC7 0x0000159c 3009 #define BCE_EMAC_RX_STAT_AC8 0x000015a0 3010 #define BCE_EMAC_RX_STAT_AC9 0x000015a4 3011 #define BCE_EMAC_RX_STAT_AC10 0x000015a8 3012 #define BCE_EMAC_RX_STAT_AC11 0x000015ac 3013 #define BCE_EMAC_RX_STAT_AC12 0x000015b0 3014 #define BCE_EMAC_RX_STAT_AC13 0x000015b4 3015 #define BCE_EMAC_RX_STAT_AC14 0x000015b8 3016 #define BCE_EMAC_RX_STAT_AC15 0x000015bc 3017 #define BCE_EMAC_RX_STAT_AC16 0x000015c0 3018 #define BCE_EMAC_RX_STAT_AC17 0x000015c4 3019 #define BCE_EMAC_RX_STAT_AC18 0x000015c8 3020 #define BCE_EMAC_RX_STAT_AC19 0x000015cc 3021 #define BCE_EMAC_RX_STAT_AC20 0x000015d0 3022 #define BCE_EMAC_RX_STAT_AC21 0x000015d4 3023 #define BCE_EMAC_RX_STAT_AC22 0x000015d8 3024 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 3025 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 3026 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 3027 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 3028 #define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c 3029 #define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 3030 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 3031 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 3032 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 3033 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 3034 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 3035 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 3036 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 3037 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 3038 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 3039 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 3040 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 3041 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 3042 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 3043 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 3044 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 3045 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 3046 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 3047 #define BCE_EMAC_TXMAC_DEBUG0 0x00001658 3048 #define BCE_EMAC_TXMAC_DEBUG1 0x0000165c 3049 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 3050 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 3051 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 3052 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 3053 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 3054 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 3055 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 3056 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 3057 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 3058 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 3059 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 3060 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 3061 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 3062 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 3063 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 3064 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 3065 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 3066 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 3067 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 3068 3069 #define BCE_EMAC_TXMAC_DEBUG2 0x00001660 3070 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 3071 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 3072 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 3073 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 3074 3075 #define BCE_EMAC_TXMAC_DEBUG3 0x00001664 3076 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 3077 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 3078 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 3079 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 3080 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 3081 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 3082 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 3083 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 3084 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 3085 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 3086 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 3087 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 3088 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 3089 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 3090 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 3091 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 3092 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 3093 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 3094 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 3095 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 3096 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 3097 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 3098 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 3099 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 3100 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 3101 #define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 3102 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 3103 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 3104 3105 #define BCE_EMAC_TXMAC_DEBUG4 0x00001668 3106 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 3107 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 3108 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 3109 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 3110 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 3111 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 3112 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 3113 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 3114 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 3115 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 3116 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 3117 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 3118 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 3119 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 3120 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 3121 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 3122 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 3123 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 3124 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 3125 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 3126 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 3127 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 3128 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 3129 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 3130 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 3131 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 3132 #define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) 3133 3134 #define BCE_EMAC_TX_STAT_AC0 0x00001680 3135 #define BCE_EMAC_TX_STAT_AC1 0x00001684 3136 #define BCE_EMAC_TX_STAT_AC2 0x00001688 3137 #define BCE_EMAC_TX_STAT_AC3 0x0000168c 3138 #define BCE_EMAC_TX_STAT_AC4 0x00001690 3139 #define BCE_EMAC_TX_STAT_AC5 0x00001694 3140 #define BCE_EMAC_TX_STAT_AC6 0x00001698 3141 #define BCE_EMAC_TX_STAT_AC7 0x0000169c 3142 #define BCE_EMAC_TX_STAT_AC8 0x000016a0 3143 #define BCE_EMAC_TX_STAT_AC9 0x000016a4 3144 #define BCE_EMAC_TX_STAT_AC10 0x000016a8 3145 #define BCE_EMAC_TX_STAT_AC11 0x000016ac 3146 #define BCE_EMAC_TX_STAT_AC12 0x000016b0 3147 #define BCE_EMAC_TX_STAT_AC13 0x000016b4 3148 #define BCE_EMAC_TX_STAT_AC14 0x000016b8 3149 #define BCE_EMAC_TX_STAT_AC15 0x000016bc 3150 #define BCE_EMAC_TX_STAT_AC16 0x000016c0 3151 #define BCE_EMAC_TX_STAT_AC17 0x000016c4 3152 #define BCE_EMAC_TX_STAT_AC18 0x000016c8 3153 #define BCE_EMAC_TX_STAT_AC19 0x000016cc 3154 #define BCE_EMAC_TX_STAT_AC20 0x000016d0 3155 #define BCE_EMAC_TX_STAT_AC21 0x000016d4 3156 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 3157 3158 3159 /* 3160 * rpm_reg definition 3161 * offset: 0x1800 3162 */ 3163 #define BCE_RPM_COMMAND 0x00001800 3164 #define BCE_RPM_COMMAND_ENABLED (1L<<0) 3165 #define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 3166 3167 #define BCE_RPM_STATUS 0x00001804 3168 #define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) 3169 #define BCE_RPM_STATUS_FREE_WAIT (1L<<1) 3170 3171 #define BCE_RPM_CONFIG 0x00001808 3172 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 3173 #define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) 3174 #define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) 3175 #define BCE_RPM_CONFIG_MP_KEEP (1L<<3) 3176 #define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 3177 #define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) 3178 3179 #define BCE_RPM_MGMT_PKT_CTRL 0x0000180c 3180 #define BCE_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30) 3181 #define BCE_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31) 3182 3183 #define BCE_RPM_VLAN_MATCH0 0x00001810 3184 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 3185 3186 #define BCE_RPM_VLAN_MATCH1 0x00001814 3187 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 3188 3189 #define BCE_RPM_VLAN_MATCH2 0x00001818 3190 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 3191 3192 #define BCE_RPM_VLAN_MATCH3 0x0000181c 3193 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 3194 3195 #define BCE_RPM_SORT_USER0 0x00001820 3196 #define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) 3197 #define BCE_RPM_SORT_USER0_BC_EN (1L<<16) 3198 #define BCE_RPM_SORT_USER0_MC_EN (1L<<17) 3199 #define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 3200 #define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) 3201 #define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 3202 #define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) 3203 #define BCE_RPM_SORT_USER0_ENA (1L<<31) 3204 3205 #define BCE_RPM_SORT_USER1 0x00001824 3206 #define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) 3207 #define BCE_RPM_SORT_USER1_BC_EN (1L<<16) 3208 #define BCE_RPM_SORT_USER1_MC_EN (1L<<17) 3209 #define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 3210 #define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) 3211 #define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 3212 #define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) 3213 #define BCE_RPM_SORT_USER1_ENA (1L<<31) 3214 3215 #define BCE_RPM_SORT_USER2 0x00001828 3216 #define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) 3217 #define BCE_RPM_SORT_USER2_BC_EN (1L<<16) 3218 #define BCE_RPM_SORT_USER2_MC_EN (1L<<17) 3219 #define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 3220 #define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) 3221 #define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 3222 #define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) 3223 #define BCE_RPM_SORT_USER2_ENA (1L<<31) 3224 3225 #define BCE_RPM_SORT_USER3 0x0000182c 3226 #define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) 3227 #define BCE_RPM_SORT_USER3_BC_EN (1L<<16) 3228 #define BCE_RPM_SORT_USER3_MC_EN (1L<<17) 3229 #define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 3230 #define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) 3231 #define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 3232 #define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) 3233 #define BCE_RPM_SORT_USER3_ENA (1L<<31) 3234 3235 #define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 3236 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 3237 #define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 3238 #define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c 3239 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 3240 #define BCE_RPM_STAT_AC0 0x00001880 3241 #define BCE_RPM_STAT_AC1 0x00001884 3242 #define BCE_RPM_STAT_AC2 0x00001888 3243 #define BCE_RPM_STAT_AC3 0x0000188c 3244 #define BCE_RPM_STAT_AC4 0x00001890 3245 #define BCE_RPM_RC_CNTL_0 0x00001900 3246 #define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 3247 #define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) 3248 #define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) 3249 #define BCE_RPM_RC_CNTL_0_P4 (1L<<12) 3250 #define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 3251 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 3252 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 3253 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 3254 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 3255 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 3256 #define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) 3257 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 3258 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 3259 #define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 3260 #define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 3261 #define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) 3262 #define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 3263 #define BCE_RPM_RC_CNTL_0_MAP (1L<<24) 3264 #define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) 3265 #define BCE_RPM_RC_CNTL_0_MASK (1L<<26) 3266 #define BCE_RPM_RC_CNTL_0_P1 (1L<<27) 3267 #define BCE_RPM_RC_CNTL_0_P2 (1L<<28) 3268 #define BCE_RPM_RC_CNTL_0_P3 (1L<<29) 3269 #define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) 3270 3271 #define BCE_RPM_RC_VALUE_MASK_0 0x00001904 3272 #define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 3273 #define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 3274 3275 #define BCE_RPM_RC_CNTL_1 0x00001908 3276 #define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) 3277 #define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) 3278 3279 #define BCE_RPM_RC_VALUE_MASK_1 0x0000190c 3280 #define BCE_RPM_RC_CNTL_2 0x00001910 3281 #define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) 3282 #define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) 3283 3284 #define BCE_RPM_RC_VALUE_MASK_2 0x00001914 3285 #define BCE_RPM_RC_CNTL_3 0x00001918 3286 #define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) 3287 #define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) 3288 3289 #define BCE_RPM_RC_VALUE_MASK_3 0x0000191c 3290 #define BCE_RPM_RC_CNTL_4 0x00001920 3291 #define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) 3292 #define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) 3293 3294 #define BCE_RPM_RC_VALUE_MASK_4 0x00001924 3295 #define BCE_RPM_RC_CNTL_5 0x00001928 3296 #define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) 3297 #define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) 3298 3299 #define BCE_RPM_RC_VALUE_MASK_5 0x0000192c 3300 #define BCE_RPM_RC_CNTL_6 0x00001930 3301 #define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) 3302 #define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) 3303 3304 #define BCE_RPM_RC_VALUE_MASK_6 0x00001934 3305 #define BCE_RPM_RC_CNTL_7 0x00001938 3306 #define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) 3307 #define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) 3308 3309 #define BCE_RPM_RC_VALUE_MASK_7 0x0000193c 3310 #define BCE_RPM_RC_CNTL_8 0x00001940 3311 #define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) 3312 #define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) 3313 3314 #define BCE_RPM_RC_VALUE_MASK_8 0x00001944 3315 #define BCE_RPM_RC_CNTL_9 0x00001948 3316 #define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) 3317 #define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) 3318 3319 #define BCE_RPM_RC_VALUE_MASK_9 0x0000194c 3320 #define BCE_RPM_RC_CNTL_10 0x00001950 3321 #define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) 3322 #define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) 3323 3324 #define BCE_RPM_RC_VALUE_MASK_10 0x00001954 3325 #define BCE_RPM_RC_CNTL_11 0x00001958 3326 #define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) 3327 #define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) 3328 3329 #define BCE_RPM_RC_VALUE_MASK_11 0x0000195c 3330 #define BCE_RPM_RC_CNTL_12 0x00001960 3331 #define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) 3332 #define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) 3333 3334 #define BCE_RPM_RC_VALUE_MASK_12 0x00001964 3335 #define BCE_RPM_RC_CNTL_13 0x00001968 3336 #define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) 3337 #define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) 3338 3339 #define BCE_RPM_RC_VALUE_MASK_13 0x0000196c 3340 #define BCE_RPM_RC_CNTL_14 0x00001970 3341 #define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) 3342 #define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) 3343 3344 #define BCE_RPM_RC_VALUE_MASK_14 0x00001974 3345 #define BCE_RPM_RC_CNTL_15 0x00001978 3346 #define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) 3347 #define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) 3348 3349 #define BCE_RPM_RC_VALUE_MASK_15 0x0000197c 3350 #define BCE_RPM_RC_CONFIG 0x00001980 3351 #define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 3352 #define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 3353 3354 #define BCE_RPM_DEBUG0 0x00001984 3355 #define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 3356 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 3357 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 3358 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 3359 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 3360 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 3361 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 3362 #define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) 3363 #define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) 3364 #define BCE_RPM_DEBUG0_DONE (1L<<24) 3365 #define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 3366 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 3367 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 3368 #define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 3369 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 3370 3371 #define BCE_RPM_DEBUG1 0x00001988 3372 #define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 3373 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 3374 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 3375 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 3376 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 3377 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 3378 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 3379 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 3380 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 3381 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 3382 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 3383 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 3384 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 3385 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 3386 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 3387 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 3388 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 3389 #define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 3390 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 3391 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 3392 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 3393 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 3394 3395 #define BCE_RPM_DEBUG2 0x0000198c 3396 #define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 3397 #define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) 3398 #define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 3399 #define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 3400 #define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 3401 #define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 3402 #define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 3403 #define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) 3404 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 3405 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 3406 3407 #define BCE_RPM_DEBUG3 0x00001990 3408 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 3409 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 3410 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 3411 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 3412 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 3413 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 3414 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 3415 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 3416 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 3417 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 3418 #define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 3419 #define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) 3420 #define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 3421 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 3422 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 3423 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 3424 #define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 3425 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 3426 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 3427 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 3428 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 3429 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 3430 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 3431 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 3432 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 3433 #define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) 3434 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 3435 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 3436 #define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 3437 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 3438 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 3439 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 3440 3441 #define BCE_RPM_DEBUG4 0x00001994 3442 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 3443 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 3444 #define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 3445 #define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 3446 3447 #define BCE_RPM_DEBUG5 0x00001998 3448 #define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 3449 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 3450 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 3451 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 3452 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 3453 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 3454 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 3455 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 3456 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 3457 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 3458 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 3459 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 3460 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 3461 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 3462 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 3463 #define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) 3464 3465 #define BCE_RPM_DEBUG6 0x0000199c 3466 #define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 3467 #define BCE_RPM_DEBUG6_VEC (0xffffL<<16) 3468 3469 #define BCE_RPM_DEBUG7 0x000019a0 3470 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 3471 3472 #define BCE_RPM_DEBUG8 0x000019a4 3473 #define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 3474 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 3475 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 3476 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 3477 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 3478 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 3479 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 3480 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 3481 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 3482 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 3483 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 3484 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 3485 #define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 3486 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 3487 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 3488 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 3489 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 3490 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 3491 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 3492 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 3493 #define BCE_RPM_DEBUG8_EOF_DET (1L<<12) 3494 #define BCE_RPM_DEBUG8_SOF_DET (1L<<13) 3495 #define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 3496 #define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) 3497 #define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 3498 #define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 3499 3500 #define BCE_RPM_DEBUG9 0x000019a8 3501 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 3502 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 3503 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 3504 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 3505 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 3506 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 3507 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 3508 3509 #define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 3510 #define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 3511 #define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 3512 #define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc 3513 #define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 3514 #define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 3515 #define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 3516 #define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc 3517 #define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 3518 #define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 3519 #define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 3520 #define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec 3521 #define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 3522 #define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 3523 #define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 3524 #define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc 3525 3526 3527 /* 3528 * rlup_reg definition 3529 * offset: 0x2000 3530 */ 3531 #define BCE_RLUP_RSS_CONFIG 0x0000201c 3532 #define BCE_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3L<<0) 3533 #define BCE_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0) 3534 #define BCE_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0) 3535 #define BCE_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0) 3536 #define BCE_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0) 3537 #define BCE_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3L<<2) 3538 #define BCE_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2) 3539 #define BCE_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1L<<2) 3540 #define BCE_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2) 3541 #define BCE_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2) 3542 3543 #define BCE_RLUP_RSS_KEY_BASE 0x00002020 3544 #define BCE_RLUP_RSS_KEY_SIZE 4 3545 #define BCE_RLUP_RSS_KEY_CNT 10 3546 #define BCE_RLUP_RSS_KEY(i) \ 3547 (BCE_RLUP_RSS_KEY_BASE + (i * BCE_RLUP_RSS_KEY_SIZE)) 3548 #define BCE_RLUP_RSS_KEYVAL(key, i) \ 3549 (key[(i) * BCE_RLUP_RSS_KEY_SIZE] << 24 | \ 3550 key[(i) * BCE_RLUP_RSS_KEY_SIZE + 1] << 16 | \ 3551 key[(i) * BCE_RLUP_RSS_KEY_SIZE + 2] << 8 | \ 3552 key[(i) * BCE_RLUP_RSS_KEY_SIZE + 3]) 3553 3554 #define BCE_RLUP_RSS_COMMAND 0x00002048 3555 #define BCE_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0) 3556 #define BCE_RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4) 3557 #define BCE_RLUP_RSS_COMMAND_WRITE (1UL<<12) 3558 #define BCE_RLUP_RSS_COMMAND_READ (1UL<<13) 3559 #define BCE_RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14) 3560 3561 #define BCE_RLUP_RSS_DATA 0x0000204c 3562 3563 #define BCE_RLUP_FTQ_CMD 0x000023f8 3564 #define BCE_RLUP_FTQ_CTL 0x000023fc 3565 #define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3566 #define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3567 3568 3569 /* 3570 * rv2pcsr_reg definition 3571 * offset: 0x2400 3572 */ 3573 #define BCE_RV2PCSR_FTQ_CMD 0x000027f8 3574 #define BCE_RV2PCSR_FTQ_CTL 0x000027fc 3575 #define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3576 #define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3577 3578 3579 /* 3580 * rdma_reg definition 3581 * offset: 0x2c00 3582 */ 3583 #define BCE_RDMA_FTQ_CMD 0x00002ff8 3584 #define BCE_RDMA_FTQ_CTL 0x00002ffc 3585 #define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3586 #define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3587 3588 3589 /* 3590 * timer_reg definition 3591 * offset: 0x4400 3592 */ 3593 #define BCE_TIMER_COMMAND 0x00004400 3594 #define BCE_TIMER_COMMAND_ENABLED (1L<<0) 3595 3596 #define BCE_TIMER_STATUS 0x00004404 3597 #define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0) 3598 #define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8) 3599 #define BCE_TIMER_STATUS_TMR1_CNT (1L<<9) 3600 #define BCE_TIMER_STATUS_TMR2_CNT (1L<<10) 3601 #define BCE_TIMER_STATUS_TMR3_CNT (1L<<11) 3602 #define BCE_TIMER_STATUS_TMR4_CNT (1L<<12) 3603 #define BCE_TIMER_STATUS_TMR5_CNT (1L<<13) 3604 3605 #define BCE_TIMER_25MHZ_FREE_RUNi 0x00004448 3606 3607 3608 /* 3609 * tsch_reg definition 3610 * offset: 0x4c00 3611 */ 3612 #define BCE_TSCH_FTQ_CMD 0x00004ff8 3613 #define BCE_TSCH_FTQ_CTL 0x00004ffc 3614 #define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3615 #define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3616 3617 3618 /* 3619 * rbuf_reg definition 3620 * offset: 0x200000 3621 */ 3622 #define BCE_RBUF_COMMAND 0x00200000 3623 #define BCE_RBUF_COMMAND_ENABLED (1L<<0) 3624 #define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) 3625 #define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) 3626 #define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) 3627 #define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) 3628 3629 #define BCE_RBUF_STATUS1 0x00200004 3630 #define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 3631 3632 #define BCE_RBUF_STATUS2 0x00200008 3633 #define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 3634 #define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 3635 3636 #define BCE_RBUF_CONFIG 0x0020000c 3637 #define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 3638 #define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 3639 3640 #define BCE_RBUF_FW_BUF_ALLOC 0x00200010 3641 #define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 3642 3643 #define BCE_RBUF_FW_BUF_FREE 0x00200014 3644 #define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 3645 #define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 3646 #define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3647 3648 #define BCE_RBUF_FW_BUF_SEL 0x00200018 3649 #define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3650 #define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3651 #define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3652 3653 #define BCE_RBUF_CONFIG2 0x0020001c 3654 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3655 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3656 3657 #define BCE_RBUF_CONFIG3 0x00200020 3658 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3659 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3660 3661 #define BCE_RBUF_PKT_DATA 0x00208000 3662 #define BCE_RBUF_CLIST_DATA 0x00210000 3663 #define BCE_RBUF_BUF_DATA 0x00220000 3664 3665 3666 /* 3667 * rv2p_reg definition 3668 * offset: 0x2800 3669 */ 3670 #define BCE_RV2P_COMMAND 0x00002800 3671 #define BCE_RV2P_COMMAND_ENABLED (1L<<0) 3672 #define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3673 #define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3674 #define BCE_RV2P_COMMAND_ABORT0 (1L<<4) 3675 #define BCE_RV2P_COMMAND_ABORT1 (1L<<5) 3676 #define BCE_RV2P_COMMAND_ABORT2 (1L<<6) 3677 #define BCE_RV2P_COMMAND_ABORT3 (1L<<7) 3678 #define BCE_RV2P_COMMAND_ABORT4 (1L<<8) 3679 #define BCE_RV2P_COMMAND_ABORT5 (1L<<9) 3680 #define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) 3681 #define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) 3682 #define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3683 3684 #define BCE_RV2P_STATUS 0x00002804 3685 #define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) 3686 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3687 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3688 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3689 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3690 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3691 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3692 3693 #define BCE_RV2P_CONFIG 0x00002808 3694 #define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3695 #define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3696 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3697 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3698 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3699 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3700 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3701 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3702 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3703 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3704 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3705 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3706 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3707 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3708 #define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3709 #define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3710 #define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3711 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3712 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3713 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3714 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3715 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3716 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3717 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3718 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3719 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3720 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3721 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3722 3723 #define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 3724 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3725 3726 #define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 3727 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3728 3729 #define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 3730 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3731 3732 #define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c 3733 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3734 3735 #define BCE_RV2P_INSTR_HIGH 0x00002830 3736 #define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3737 3738 #define BCE_RV2P_INSTR_LOW 0x00002834 3739 #define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 3740 #define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3741 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3742 3743 #define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c 3744 #define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3745 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3746 3747 #define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 3748 #define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 3749 #define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 3750 #define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c 3751 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3752 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3753 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3754 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3755 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3756 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3757 3758 #define BCE_RV2P_PFTQ_DATA 0x00002b40 3759 #define BCE_RV2P_PFTQ_CMD 0x00002b78 3760 #define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3761 #define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3762 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3763 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3764 #define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3765 #define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3766 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3767 #define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3768 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3769 #define BCE_RV2P_PFTQ_CMD_POP (1L<<30) 3770 #define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) 3771 3772 #define BCE_RV2P_PFTQ_CTL 0x00002b7c 3773 #define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3774 #define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3775 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3776 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3777 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3778 3779 #define BCE_RV2P_TFTQ_DATA 0x00002b80 3780 #define BCE_RV2P_TFTQ_CMD 0x00002bb8 3781 #define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3782 #define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3783 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3784 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3785 #define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3786 #define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3787 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3788 #define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3789 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3790 #define BCE_RV2P_TFTQ_CMD_POP (1L<<30) 3791 #define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) 3792 3793 #define BCE_RV2P_TFTQ_CTL 0x00002bbc 3794 #define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3795 #define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3796 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3797 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3798 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3799 3800 #define BCE_RV2P_MFTQ_DATA 0x00002bc0 3801 #define BCE_RV2P_MFTQ_CMD 0x00002bf8 3802 #define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3803 #define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3804 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3805 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3806 #define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3807 #define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3808 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3809 #define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3810 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3811 #define BCE_RV2P_MFTQ_CMD_POP (1L<<30) 3812 #define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) 3813 3814 #define BCE_RV2P_MFTQ_CTL 0x00002bfc 3815 #define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3816 #define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3817 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3818 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3819 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3820 3821 3822 /* 3823 * mq_reg definition 3824 * offset: 0x3c00 3825 */ 3826 #define BCE_MQ_COMMAND 0x00003c00 3827 #define BCE_MQ_COMMAND_ENABLED (1L<<0) 3828 #define BCE_MQ_COMMAND_INIT (1L<<1) 3829 #define BCE_MQ_COMMAND_OVERFLOW (1L<<4) 3830 #define BCE_MQ_COMMAND_WR_ERROR (1L<<5) 3831 #define BCE_MQ_COMMAND_RD_ERROR (1L<<6) 3832 #define BCE_MQ_COMMAND_IDB_CFG_ERROR (1L<<7) 3833 #define BCE_MQ_COMMAND_IDB_OVERFLOW (1L<<10) 3834 #define BCE_MQ_COMMAND_NO_BIN_ERROR (1L<<11) 3835 #define BCE_MQ_COMMAND_NO_MAP_ERROR (1L<<12) 3836 3837 #define BCE_MQ_STATUS 0x00003c04 3838 #define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3839 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3840 #define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3841 #define BCE_MQ_STATUS_IDB_OFLOW_STAT (1L<<19) 3842 3843 #define BCE_MQ_CONFIG 0x00003c08 3844 #define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3845 #define BCE_MQ_CONFIG_HALT_DIS (1L<<1) 3846 #define BCE_MQ_CONFIG_BIN_MQ_MODE (1L<<2) 3847 #define BCE_MQ_CONFIG_DIS_IDB_DROP (1L<<3) 3848 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3849 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3850 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3851 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3852 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3853 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3854 #define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3855 #define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3856 3857 #define BCE_MQ_ENQUEUE1 0x00003c0c 3858 #define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3859 #define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) 3860 #define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3861 #define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3862 3863 #define BCE_MQ_ENQUEUE2 0x00003c10 3864 #define BCE_MQ_BAD_WR_ADDR 0x00003c14 3865 #define BCE_MQ_BAD_RD_ADDR 0x00003c18 3866 #define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c 3867 #define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3868 3869 #define BCE_MQ_KNL_WIND_END 0x00003c20 3870 #define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3871 3872 #define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 3873 #define BCE_MQ_KNL_TX_MASK1 0x00003c28 3874 #define BCE_MQ_KNL_CMD_MASK1 0x00003c2c 3875 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3876 #define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 3877 #define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 3878 #define BCE_MQ_KNL_TX_MASK2 0x00003c3c 3879 #define BCE_MQ_KNL_CMD_MASK2 0x00003c40 3880 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3881 #define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 3882 #define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3883 #define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 3884 #define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3885 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3886 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3887 #define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3888 #define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 3889 #define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3890 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3891 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3892 #define BCE_MQ_MEM_WR_ADDR 0x00003c74 3893 #define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3894 3895 #define BCE_MQ_MEM_WR_DATA0 0x00003c78 3896 #define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3897 3898 #define BCE_MQ_MEM_WR_DATA1 0x00003c7c 3899 #define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3900 3901 #define BCE_MQ_MEM_WR_DATA2 0x00003c80 3902 #define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3903 #define BCE_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0) 3904 3905 #define BCE_MQ_MEM_RD_ADDR 0x00003c84 3906 #define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3907 3908 #define BCE_MQ_MEM_RD_DATA0 0x00003c88 3909 #define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3910 3911 #define BCE_MQ_MEM_RD_DATA1 0x00003c8c 3912 #define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3913 3914 #define BCE_MQ_MEM_RD_DATA2 0x00003c90 3915 #define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3916 #define BCE_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0) 3917 3918 #define BCE_MQ_CONFIG2 0x00003d00 3919 #define BCE_MQ_CONFIG2_CONT_SZ (0x7L<<4) 3920 #define BCE_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8) 3921 3922 #define BCE_MQ_MAP_L2_3 0x00003d2c 3923 #define BCE_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0) 3924 #define BCE_MQ_MAP_L2_3_SZ (0x3L<<8) 3925 #define BCE_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10) 3926 #define BCE_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23) 3927 #define BCE_MQ_MAP_L2_3_ARM (0x3L<<26) 3928 #define BCE_MQ_MAP_L2_3_ENA (0x1L<<31) 3929 #define BCE_MQ_MAP_L2_3_DEFAULT 0x82004646 3930 3931 #define BCE_MQ_MAP_L2_5 0x00003d34 3932 #define BCE_MQ_MAP_L2_5_MQ_OFFSET (0xffL<<0) 3933 #define BCE_MQ_MAP_L2_5_SZ (0x3L<<8) 3934 #define BCE_MQ_MAP_L2_5_CTX_OFFSET (0x2ffL<<10) 3935 #define BCE_MQ_MAP_L2_5_BIN_OFFSET (0x7L<<23) 3936 #define BCE_MQ_MAP_L2_5_ARM (0x3L<<26) 3937 #define BCE_MQ_MAP_L2_5_ENA (0x1L<<31) 3938 #define BCE_MQ_MAP_L2_5_DEFAULT 0x83000b08 3939 3940 3941 /* 3942 * csch_reg definition 3943 * offset: 0x4000 3944 */ 3945 #define BCE_CSCH_COMMAND 0x00004000 3946 #define BCE_CSCH_CH_FTQ_CMD 0x000043f8 3947 #define BCE_CSCH_CH_FTQ_CTL 0x000043fc 3948 #define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3949 #define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3950 3951 3952 /* 3953 * tsch_reg definition 3954 * offset: 0x4c00 3955 */ 3956 #define BCE_TSCH_TSS_CFG 0x00004c1c 3957 #define BCE_TSCH_TSS_CFG_TSS_START_CID (0x7ffL<<8) 3958 #define BCE_TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfL<<24) 3959 3960 3961 /* 3962 * tbdr_reg definition 3963 * offset: 0x5000 3964 */ 3965 #define BCE_TBDR_COMMAND 0x00005000 3966 #define BCE_TBDR_COMMAND_ENABLE (1L<<0) 3967 #define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) 3968 #define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3969 3970 #define BCE_TBDR_STATUS 0x00005004 3971 #define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) 3972 #define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) 3973 #define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3974 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3975 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3976 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3977 #define BCE_TBDR_STATUS_BURST_CNT (1L<<6) 3978 3979 #define BCE_TBDR_CONFIG 0x00005008 3980 #define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3981 #define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) 3982 #define BCE_TBDR_CONFIG_PRIORITY (1L<<9) 3983 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3984 #define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3985 #define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3986 #define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3987 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3988 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3989 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3990 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3991 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3992 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3993 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3994 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3995 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3996 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3997 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3998 3999 #define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c 4000 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4001 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4002 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4003 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4004 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4005 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4006 4007 #define BCE_TBDR_FTQ_DATA 0x000053c0 4008 #define BCE_TBDR_FTQ_CMD 0x000053f8 4009 #define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 4010 #define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) 4011 #define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 4012 #define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 4013 #define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 4014 #define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) 4015 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 4016 #define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 4017 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 4018 #define BCE_TBDR_FTQ_CMD_POP (1L<<30) 4019 #define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) 4020 4021 #define BCE_TBDR_FTQ_CTL 0x000053fc 4022 #define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) 4023 #define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 4024 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4025 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4026 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4027 4028 4029 4030 /* 4031 * tdma_reg definition 4032 * offset: 0x5c00 4033 */ 4034 #define BCE_TDMA_COMMAND 0x00005c00 4035 #define BCE_TDMA_COMMAND_ENABLED (1L<<0) 4036 #define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) 4037 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 4038 4039 #define BCE_TDMA_STATUS 0x00005c04 4040 #define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) 4041 #define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 4042 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 4043 #define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) 4044 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 4045 #define BCE_TDMA_STATUS_BURST_CNT (1L<<17) 4046 4047 #define BCE_TDMA_CONFIG 0x00005c08 4048 #define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) 4049 #define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) 4050 #define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 4051 #define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 4052 #define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 4053 #define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 4054 #define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 4055 #define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) 4056 #define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 4057 #define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 4058 #define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 4059 #define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 4060 #define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) 4061 #define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) 4062 #define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 4063 4064 #define BCE_TDMA_PAYLOAD_PROD 0x00005c0c 4065 #define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 4066 4067 #define BCE_TDMA_DBG_WATCHDOG 0x00005c10 4068 #define BCE_TDMA_DBG_TRIGGER 0x00005c14 4069 #define BCE_TDMA_DMAD_FSM 0x00005c80 4070 #define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 4071 #define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) 4072 #define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 4073 #define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 4074 #define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) 4075 #define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) 4076 #define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) 4077 4078 #define BCE_TDMA_DMAD_STATUS 0x00005c84 4079 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 4080 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 4081 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 4082 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 4083 4084 #define BCE_TDMA_DR_INTF_FSM 0x00005c88 4085 #define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 4086 #define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 4087 #define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 4088 #define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 4089 #define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 4090 4091 #define BCE_TDMA_DR_INTF_STATUS 0x00005c8c 4092 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 4093 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 4094 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 4095 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 4096 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 4097 4098 #define BCE_TDMA_FTQ_DATA 0x00005fc0 4099 #define BCE_TDMA_FTQ_CMD 0x00005ff8 4100 #define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 4101 #define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) 4102 #define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 4103 #define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 4104 #define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 4105 #define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) 4106 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 4107 #define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 4108 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 4109 #define BCE_TDMA_FTQ_CMD_POP (1L<<30) 4110 #define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) 4111 4112 #define BCE_TDMA_FTQ_CTL 0x00005ffc 4113 #define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) 4114 #define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 4115 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4116 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4117 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4118 4119 4120 /* 4121 * nvm_reg definition 4122 * offset: 0x6400 4123 */ 4124 #define BCE_NVM_COMMAND 0x00006400 4125 #define BCE_NVM_COMMAND_RST (1L<<0) 4126 #define BCE_NVM_COMMAND_DONE (1L<<3) 4127 #define BCE_NVM_COMMAND_DOIT (1L<<4) 4128 #define BCE_NVM_COMMAND_WR (1L<<5) 4129 #define BCE_NVM_COMMAND_ERASE (1L<<6) 4130 #define BCE_NVM_COMMAND_FIRST (1L<<7) 4131 #define BCE_NVM_COMMAND_LAST (1L<<8) 4132 #define BCE_NVM_COMMAND_WREN (1L<<16) 4133 #define BCE_NVM_COMMAND_WRDI (1L<<17) 4134 #define BCE_NVM_COMMAND_EWSR (1L<<18) 4135 #define BCE_NVM_COMMAND_WRSR (1L<<19) 4136 4137 #define BCE_NVM_STATUS 0x00006404 4138 #define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 4139 #define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 4140 #define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 4141 4142 #define BCE_NVM_WRITE 0x00006408 4143 #define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 4144 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 4145 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 4146 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 4147 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 4148 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 4149 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 4150 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 4151 4152 #define BCE_NVM_ADDR 0x0000640c 4153 #define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 4154 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 4155 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 4156 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 4157 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 4158 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 4159 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 4160 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 4161 4162 #define BCE_NVM_READ 0x00006410 4163 #define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 4164 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 4165 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 4166 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 4167 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 4168 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 4169 #define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 4170 #define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 4171 4172 #define BCE_NVM_CFG1 0x00006414 4173 #define BCE_NVM_CFG1_FLASH_MODE (1L<<0) 4174 #define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) 4175 #define BCE_NVM_CFG1_PASS_MODE (1L<<2) 4176 #define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) 4177 #define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) 4178 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 4179 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 4180 #define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 4181 #define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 4182 #define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) 4183 #define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) 4184 #define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 4185 4186 #define BCE_NVM_CFG2 0x00006418 4187 #define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) 4188 #define BCE_NVM_CFG2_DUMMY (0xffL<<8) 4189 #define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) 4190 4191 #define BCE_NVM_CFG3 0x0000641c 4192 #define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 4193 #define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) 4194 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 4195 #define BCE_NVM_CFG3_READ_CMD (0xffL<<24) 4196 4197 #define BCE_NVM_SW_ARB 0x00006420 4198 #define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 4199 #define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 4200 #define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 4201 #define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 4202 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 4203 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 4204 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 4205 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 4206 #define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) 4207 #define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) 4208 #define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) 4209 #define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) 4210 #define BCE_NVM_SW_ARB_REQ0 (1L<<12) 4211 #define BCE_NVM_SW_ARB_REQ1 (1L<<13) 4212 #define BCE_NVM_SW_ARB_REQ2 (1L<<14) 4213 #define BCE_NVM_SW_ARB_REQ3 (1L<<15) 4214 4215 #define BCE_NVM_ACCESS_ENABLE 0x00006424 4216 #define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) 4217 #define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 4218 4219 #define BCE_NVM_WRITE1 0x00006428 4220 #define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) 4221 #define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) 4222 #define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) 4223 4224 4225 /* 4226 * hc_reg definition 4227 * offset: 0x6800 4228 */ 4229 #define BCE_HC_COMMAND 0x00006800 4230 #define BCE_HC_COMMAND_ENABLE (1L<<0) 4231 #define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) 4232 #define BCE_HC_COMMAND_COAL_NOW (1L<<16) 4233 #define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 4234 #define BCE_HC_COMMAND_STATS_NOW (1L<<18) 4235 #define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) 4236 #define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) 4237 #define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 4238 #define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) 4239 #define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) 4240 #define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) 4241 #define BCE_HC_COMMAND_MAIN_PWR_INT (1L<<22) 4242 #define BCE_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27) 4243 4244 #define BCE_HC_STATUS 0x00006804 4245 #define BCE_HC_STATUS_MASTER_ABORT (1L<<0) 4246 #define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 4247 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 4248 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 4249 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 4250 #define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 4251 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 4252 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 4253 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 4254 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 4255 4256 #define BCE_HC_CONFIG 0x00006808 4257 #define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) 4258 #define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) 4259 #define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) 4260 #define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) 4261 #define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) 4262 #define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 4263 #define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) 4264 #define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 4265 #define BCE_HC_CONFIG_PER_MODE (1L<<16) 4266 #define BCE_HC_CONFIG_ONE_SHOT (1L<<17) 4267 #define BCE_HC_CONFIG_USE_INT_PARAM (1L<<18) 4268 #define BCE_HC_CONFIG_SET_MASK_AT_RD (1L<<19) 4269 #define BCE_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20) 4270 #define BCE_HC_CONFIG_SB_ADDR_INC (0x7L<<24) 4271 #define BCE_HC_CONFIG_SB_ADDR_INC_64B (0L<<24) 4272 #define BCE_HC_CONFIG_SB_ADDR_INC_128B (1L<<24) 4273 #define BCE_HC_CONFIG_SB_ADDR_INC_256B (2L<<24) 4274 #define BCE_HC_CONFIG_SB_ADDR_INC_512B (3L<<24) 4275 #define BCE_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24) 4276 #define BCE_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24) 4277 #define BCE_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24) 4278 #define BCE_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24) 4279 #define BCE_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29) 4280 #define BCE_HC_CONFIG_UNMASK_ALL (1L<<30) 4281 #define BCE_HC_CONFIG_TX_SEL (1L<<31) 4282 4283 #define BCE_HC_ATTN_BITS_ENABLE 0x0000680c 4284 #define BCE_HC_STATUS_ADDR_L 0x00006810 4285 #define BCE_HC_STATUS_ADDR_H 0x00006814 4286 #define BCE_HC_STATISTICS_ADDR_L 0x00006818 4287 #define BCE_HC_STATISTICS_ADDR_H 0x0000681c 4288 #define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 4289 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 4290 #define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 4291 4292 #define BCE_HC_COMP_PROD_TRIP 0x00006824 4293 #define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 4294 #define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) 4295 4296 #define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 4297 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 4298 #define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 4299 4300 #define BCE_HC_RX_TICKS 0x0000682c 4301 #define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) 4302 #define BCE_HC_RX_TICKS_INT (0x3ffL<<16) 4303 4304 #define BCE_HC_TX_TICKS 0x00006830 4305 #define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) 4306 #define BCE_HC_TX_TICKS_INT (0x3ffL<<16) 4307 4308 #define BCE_HC_COM_TICKS 0x00006834 4309 #define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) 4310 #define BCE_HC_COM_TICKS_INT (0x3ffL<<16) 4311 4312 #define BCE_HC_CMD_TICKS 0x00006838 4313 #define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) 4314 #define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) 4315 4316 #define BCE_HC_PERIODIC_TICKS 0x0000683c 4317 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 4318 #define BCE_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4319 4320 #define BCE_HC_STAT_COLLECT_TICKS 0x00006840 4321 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 4322 4323 #define BCE_HC_STATS_TICKS 0x00006844 4324 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 4325 4326 #define BCE_HC_STATS_INTERRUPT_STATUS 0x00006848 4327 #define BCE_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0) 4328 #define BCE_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16) 4329 4330 #define BCE_HC_STAT_MEM_DATA 0x0000684c 4331 #define BCE_HC_STAT_GEN_SEL_0 0x00006850 4332 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 4333 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 4334 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 4335 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 4336 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 4337 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 4338 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 4339 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 4340 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 4341 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 4342 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 4343 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 4344 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 4345 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 4346 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 4347 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 4348 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 4349 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 4350 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 4351 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 4352 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 4353 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 4354 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 4355 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 4356 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 4357 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 4358 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 4359 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 4360 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 4361 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 4362 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 4363 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 4364 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 4365 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 4366 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 4367 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 4368 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 4369 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 4370 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 4371 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 4372 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 4373 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 4374 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 4375 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 4376 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 4377 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 4378 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 4379 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 4380 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 4381 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 4382 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 4383 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 4384 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 4385 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 4386 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 4387 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 4388 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 4389 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 4390 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 4391 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 4392 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 4393 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 4394 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 4395 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 4396 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 4397 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 4398 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 4399 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 4400 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 4401 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 4402 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 4403 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 4404 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 4405 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 4406 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 4407 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 4408 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 4409 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 4410 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 4411 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 4412 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 4413 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 4414 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 4415 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 4416 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 4417 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 4418 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 4419 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT \ 4420 (88L<<0) 4421 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT \ 4422 (89L<<0) 4423 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 4424 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 4425 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 4426 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT \ 4427 (93L<<0) 4428 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT\ 4429 (94L<<0) 4430 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 4431 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 4432 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 4433 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 4434 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 4435 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 4436 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 4437 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 4438 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 4439 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 4440 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 4441 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 4442 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 4443 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 4444 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 4445 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 4446 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 4447 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 4448 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 4449 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 4450 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 4451 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 4452 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 4453 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 4454 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 4455 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 4456 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 4457 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 4458 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 4459 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 4460 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 4461 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 4462 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0) 4463 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0) 4464 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0) 4465 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0) 4466 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0) 4467 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0) 4468 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0) 4469 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0) 4470 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0) 4471 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0) 4472 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0) 4473 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0) 4474 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0) 4475 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0) 4476 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0) 4477 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0) 4478 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0) 4479 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0) 4480 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0) 4481 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0) 4482 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0) 4483 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0) 4484 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0) 4485 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0) 4486 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0) 4487 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0) 4488 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0) 4489 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0) 4490 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0) 4491 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0) 4492 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0) 4493 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0) 4494 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0) 4495 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0) 4496 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0) 4497 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0) 4498 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0) 4499 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0) 4500 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0) 4501 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0) 4502 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0) 4503 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0) 4504 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0) 4505 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0) 4506 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0) 4507 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0) 4508 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0) 4509 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0) 4510 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0) 4511 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0) 4512 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0) 4513 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0) 4514 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0) 4515 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0) 4516 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0) 4517 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0) 4518 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0) 4519 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0) 4520 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0) 4521 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0) 4522 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0) 4523 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0) 4524 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0) 4525 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0) 4526 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0) 4527 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0) 4528 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0) 4529 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0) 4530 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0) 4531 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8) 4532 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16) 4533 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24) 4534 4535 #define BCE_HC_STAT_GEN_SEL_1 0x00006854 4536 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 4537 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 4538 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 4539 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 4540 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0) 4541 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8) 4542 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16) 4543 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24) 4544 4545 #define BCE_HC_STAT_GEN_SEL_2 0x00006858 4546 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 4547 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 4548 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 4549 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 4550 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0) 4551 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8) 4552 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16) 4553 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24) 4554 4555 #define BCE_HC_STAT_GEN_SEL_3 0x0000685c 4556 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 4557 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 4558 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 4559 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 4560 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0) 4561 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8) 4562 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16) 4563 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24) 4564 4565 #define BCE_HC_STAT_GEN_STAT0 0x00006888 4566 #define BCE_HC_STAT_GEN_STAT1 0x0000688c 4567 #define BCE_HC_STAT_GEN_STAT2 0x00006890 4568 #define BCE_HC_STAT_GEN_STAT3 0x00006894 4569 #define BCE_HC_STAT_GEN_STAT4 0x00006898 4570 #define BCE_HC_STAT_GEN_STAT5 0x0000689c 4571 #define BCE_HC_STAT_GEN_STAT6 0x000068a0 4572 #define BCE_HC_STAT_GEN_STAT7 0x000068a4 4573 #define BCE_HC_STAT_GEN_STAT8 0x000068a8 4574 #define BCE_HC_STAT_GEN_STAT9 0x000068ac 4575 #define BCE_HC_STAT_GEN_STAT10 0x000068b0 4576 #define BCE_HC_STAT_GEN_STAT11 0x000068b4 4577 #define BCE_HC_STAT_GEN_STAT12 0x000068b8 4578 #define BCE_HC_STAT_GEN_STAT13 0x000068bc 4579 #define BCE_HC_STAT_GEN_STAT14 0x000068c0 4580 #define BCE_HC_STAT_GEN_STAT15 0x000068c4 4581 #define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 4582 #define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc 4583 #define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 4584 #define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 4585 #define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 4586 #define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc 4587 #define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 4588 #define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 4589 #define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 4590 #define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec 4591 #define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 4592 #define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 4593 #define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 4594 #define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc 4595 #define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 4596 #define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 4597 #define BCE_HC_STAT_GEN_STAT_AC 0x000068c8 4598 #define BCE_HC_VIS 0x00006908 4599 #define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 4600 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 4601 #define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 4602 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 4603 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 4604 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 4605 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 4606 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 4607 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 4608 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 4609 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 4610 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 4611 #define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) 4612 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 4613 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 4614 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 4615 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 4616 #define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 4617 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 4618 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 4619 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 4620 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 4621 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 4622 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 4623 #define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) 4624 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 4625 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 4626 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 4627 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 4628 4629 #define BCE_HC_VIS_1 0x0000690c 4630 #define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) 4631 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 4632 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 4633 #define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) 4634 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 4635 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 4636 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 4637 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 4638 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 4639 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 4640 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 4641 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 4642 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 4643 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 4644 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 4645 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 4646 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 4647 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 4648 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 4649 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 4650 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 4651 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 4652 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 4653 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 4654 #define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) 4655 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 4656 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 4657 #define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 4658 #define BCE_HC_VIS_1_INT_B (1L<<27) 4659 4660 #define BCE_HC_DEBUG_VECT_PEEK 0x00006910 4661 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4662 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4663 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4664 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4665 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4666 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4667 4668 #define BCE_HC_COALESCE_NOW 0x00006914 4669 #define BCE_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1) 4670 #define BCE_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11) 4671 #define BCE_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21) 4672 4673 #define BCE_HC_MSIX_BIT_VECTOR 0x00006918 4674 #define BCE_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0) 4675 4676 #define BCE_HC_SB_CONFIG_1 0x00006a00 4677 #define BCE_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1) 4678 #define BCE_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2) 4679 #define BCE_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3) 4680 #define BCE_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4) 4681 #define BCE_HC_SB_CONFIG_1_PER_MODE (1L<<16) 4682 #define BCE_HC_SB_CONFIG_1_ONE_SHOT (1L<<17) 4683 #define BCE_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18) 4684 #define BCE_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20) 4685 4686 #define BCE_HC_TX_QUICK_CONS_TRIP_1 0x00006a04 4687 #define BCE_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0) 4688 #define BCE_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16) 4689 4690 #define BCE_HC_COMP_PROD_TRIP_1 0x00006a08 4691 #define BCE_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0) 4692 #define BCE_HC_COMP_PROD_TRIP_1_INT (0xffL<<16) 4693 4694 #define BCE_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c 4695 #define BCE_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0) 4696 #define BCE_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16) 4697 4698 #define BCE_HC_RX_TICKS_1 0x00006a10 4699 #define BCE_HC_RX_TICKS_1_VALUE (0x3ffL<<0) 4700 #define BCE_HC_RX_TICKS_1_INT (0x3ffL<<16) 4701 4702 #define BCE_HC_TX_TICKS_1 0x00006a14 4703 #define BCE_HC_TX_TICKS_1_VALUE (0x3ffL<<0) 4704 #define BCE_HC_TX_TICKS_1_INT (0x3ffL<<16) 4705 4706 #define BCE_HC_COM_TICKS_1 0x00006a18 4707 #define BCE_HC_COM_TICKS_1_VALUE (0x3ffL<<0) 4708 #define BCE_HC_COM_TICKS_1_INT (0x3ffL<<16) 4709 4710 #define BCE_HC_CMD_TICKS_1 0x00006a1c 4711 #define BCE_HC_CMD_TICKS_1_VALUE (0x3ffL<<0) 4712 #define BCE_HC_CMD_TICKS_1_INT (0x3ffL<<16) 4713 4714 #define BCE_HC_PERIODIC_TICKS_1 0x00006a20 4715 #define BCE_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0) 4716 #define BCE_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4717 4718 #define BCE_HC_SB_CONFIG_2 0x00006a24 4719 #define BCE_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1) 4720 #define BCE_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2) 4721 #define BCE_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3) 4722 #define BCE_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4) 4723 #define BCE_HC_SB_CONFIG_2_PER_MODE (1L<<16) 4724 #define BCE_HC_SB_CONFIG_2_ONE_SHOT (1L<<17) 4725 #define BCE_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18) 4726 #define BCE_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20) 4727 4728 #define BCE_HC_TX_QUICK_CONS_TRIP_2 0x00006a28 4729 #define BCE_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0) 4730 #define BCE_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16) 4731 4732 #define BCE_HC_COMP_PROD_TRIP_2 0x00006a2c 4733 #define BCE_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0) 4734 #define BCE_HC_COMP_PROD_TRIP_2_INT (0xffL<<16) 4735 4736 #define BCE_HC_RX_QUICK_CONS_TRIP_2 0x00006a30 4737 #define BCE_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0) 4738 #define BCE_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16) 4739 4740 #define BCE_HC_RX_TICKS_2 0x00006a34 4741 #define BCE_HC_RX_TICKS_2_VALUE (0x3ffL<<0) 4742 #define BCE_HC_RX_TICKS_2_INT (0x3ffL<<16) 4743 4744 #define BCE_HC_TX_TICKS_2 0x00006a38 4745 #define BCE_HC_TX_TICKS_2_VALUE (0x3ffL<<0) 4746 #define BCE_HC_TX_TICKS_2_INT (0x3ffL<<16) 4747 4748 #define BCE_HC_COM_TICKS_2 0x00006a3c 4749 #define BCE_HC_COM_TICKS_2_VALUE (0x3ffL<<0) 4750 #define BCE_HC_COM_TICKS_2_INT (0x3ffL<<16) 4751 4752 #define BCE_HC_CMD_TICKS_2 0x00006a40 4753 #define BCE_HC_CMD_TICKS_2_VALUE (0x3ffL<<0) 4754 #define BCE_HC_CMD_TICKS_2_INT (0x3ffL<<16) 4755 4756 #define BCE_HC_PERIODIC_TICKS_2 0x00006a44 4757 #define BCE_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0) 4758 #define BCE_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4759 4760 #define BCE_HC_SB_CONFIG_3 0x00006a48 4761 #define BCE_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1) 4762 #define BCE_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2) 4763 #define BCE_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3) 4764 #define BCE_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4) 4765 #define BCE_HC_SB_CONFIG_3_PER_MODE (1L<<16) 4766 #define BCE_HC_SB_CONFIG_3_ONE_SHOT (1L<<17) 4767 #define BCE_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18) 4768 #define BCE_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20) 4769 4770 #define BCE_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c 4771 #define BCE_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0) 4772 #define BCE_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16) 4773 4774 #define BCE_HC_COMP_PROD_TRIP_3 0x00006a50 4775 #define BCE_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0) 4776 #define BCE_HC_COMP_PROD_TRIP_3_INT (0xffL<<16) 4777 4778 #define BCE_HC_RX_QUICK_CONS_TRIP_3 0x00006a54 4779 #define BCE_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0) 4780 #define BCE_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16) 4781 4782 #define BCE_HC_RX_TICKS_3 0x00006a58 4783 #define BCE_HC_RX_TICKS_3_VALUE (0x3ffL<<0) 4784 #define BCE_HC_RX_TICKS_3_INT (0x3ffL<<16) 4785 4786 #define BCE_HC_TX_TICKS_3 0x00006a5c 4787 #define BCE_HC_TX_TICKS_3_VALUE (0x3ffL<<0) 4788 #define BCE_HC_TX_TICKS_3_INT (0x3ffL<<16) 4789 4790 #define BCE_HC_COM_TICKS_3 0x00006a60 4791 #define BCE_HC_COM_TICKS_3_VALUE (0x3ffL<<0) 4792 #define BCE_HC_COM_TICKS_3_INT (0x3ffL<<16) 4793 4794 #define BCE_HC_CMD_TICKS_3 0x00006a64 4795 #define BCE_HC_CMD_TICKS_3_VALUE (0x3ffL<<0) 4796 #define BCE_HC_CMD_TICKS_3_INT (0x3ffL<<16) 4797 4798 #define BCE_HC_PERIODIC_TICKS_3 0x00006a68 4799 #define BCE_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0) 4800 #define BCE_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4801 4802 #define BCE_HC_SB_CONFIG_4 0x00006a6c 4803 #define BCE_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1) 4804 #define BCE_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2) 4805 #define BCE_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3) 4806 #define BCE_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4) 4807 #define BCE_HC_SB_CONFIG_4_PER_MODE (1L<<16) 4808 #define BCE_HC_SB_CONFIG_4_ONE_SHOT (1L<<17) 4809 #define BCE_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18) 4810 #define BCE_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20) 4811 4812 #define BCE_HC_TX_QUICK_CONS_TRIP_4 0x00006a70 4813 #define BCE_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0) 4814 #define BCE_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16) 4815 4816 #define BCE_HC_COMP_PROD_TRIP_4 0x00006a74 4817 #define BCE_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0) 4818 #define BCE_HC_COMP_PROD_TRIP_4_INT (0xffL<<16) 4819 4820 #define BCE_HC_RX_QUICK_CONS_TRIP_4 0x00006a78 4821 #define BCE_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0) 4822 #define BCE_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16) 4823 4824 #define BCE_HC_RX_TICKS_4 0x00006a7c 4825 #define BCE_HC_RX_TICKS_4_VALUE (0x3ffL<<0) 4826 #define BCE_HC_RX_TICKS_4_INT (0x3ffL<<16) 4827 4828 #define BCE_HC_TX_TICKS_4 0x00006a80 4829 #define BCE_HC_TX_TICKS_4_VALUE (0x3ffL<<0) 4830 #define BCE_HC_TX_TICKS_4_INT (0x3ffL<<16) 4831 4832 #define BCE_HC_COM_TICKS_4 0x00006a84 4833 #define BCE_HC_COM_TICKS_4_VALUE (0x3ffL<<0) 4834 #define BCE_HC_COM_TICKS_4_INT (0x3ffL<<16) 4835 4836 #define BCE_HC_CMD_TICKS_4 0x00006a88 4837 #define BCE_HC_CMD_TICKS_4_VALUE (0x3ffL<<0) 4838 #define BCE_HC_CMD_TICKS_4_INT (0x3ffL<<16) 4839 4840 #define BCE_HC_PERIODIC_TICKS_4 0x00006a8c 4841 #define BCE_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0) 4842 #define BCE_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4843 4844 #define BCE_HC_SB_CONFIG_5 0x00006a90 4845 #define BCE_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1) 4846 #define BCE_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2) 4847 #define BCE_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3) 4848 #define BCE_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4) 4849 #define BCE_HC_SB_CONFIG_5_PER_MODE (1L<<16) 4850 #define BCE_HC_SB_CONFIG_5_ONE_SHOT (1L<<17) 4851 #define BCE_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18) 4852 #define BCE_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20) 4853 4854 #define BCE_HC_TX_QUICK_CONS_TRIP_5 0x00006a94 4855 #define BCE_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0) 4856 #define BCE_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16) 4857 4858 #define BCE_HC_COMP_PROD_TRIP_5 0x00006a98 4859 #define BCE_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0) 4860 #define BCE_HC_COMP_PROD_TRIP_5_INT (0xffL<<16) 4861 4862 #define BCE_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c 4863 #define BCE_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0) 4864 #define BCE_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16) 4865 4866 #define BCE_HC_RX_TICKS_5 0x00006aa0 4867 #define BCE_HC_RX_TICKS_5_VALUE (0x3ffL<<0) 4868 #define BCE_HC_RX_TICKS_5_INT (0x3ffL<<16) 4869 4870 #define BCE_HC_TX_TICKS_5 0x00006aa4 4871 #define BCE_HC_TX_TICKS_5_VALUE (0x3ffL<<0) 4872 #define BCE_HC_TX_TICKS_5_INT (0x3ffL<<16) 4873 4874 #define BCE_HC_COM_TICKS_5 0x00006aa8 4875 #define BCE_HC_COM_TICKS_5_VALUE (0x3ffL<<0) 4876 #define BCE_HC_COM_TICKS_5_INT (0x3ffL<<16) 4877 4878 #define BCE_HC_CMD_TICKS_5 0x00006aac 4879 #define BCE_HC_CMD_TICKS_5_VALUE (0x3ffL<<0) 4880 #define BCE_HC_CMD_TICKS_5_INT (0x3ffL<<16) 4881 4882 #define BCE_HC_PERIODIC_TICKS_5 0x00006ab0 4883 #define BCE_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0) 4884 #define BCE_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4885 4886 #define BCE_HC_SB_CONFIG_6 0x00006ab4 4887 #define BCE_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1) 4888 #define BCE_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2) 4889 #define BCE_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3) 4890 #define BCE_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4) 4891 #define BCE_HC_SB_CONFIG_6_PER_MODE (1L<<16) 4892 #define BCE_HC_SB_CONFIG_6_ONE_SHOT (1L<<17) 4893 #define BCE_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18) 4894 #define BCE_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20) 4895 4896 #define BCE_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8 4897 #define BCE_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0) 4898 #define BCE_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16) 4899 4900 #define BCE_HC_COMP_PROD_TRIP_6 0x00006abc 4901 #define BCE_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0) 4902 #define BCE_HC_COMP_PROD_TRIP_6_INT (0xffL<<16) 4903 4904 #define BCE_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0 4905 #define BCE_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0) 4906 #define BCE_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16) 4907 4908 #define BCE_HC_RX_TICKS_6 0x00006ac4 4909 #define BCE_HC_RX_TICKS_6_VALUE (0x3ffL<<0) 4910 #define BCE_HC_RX_TICKS_6_INT (0x3ffL<<16) 4911 4912 #define BCE_HC_TX_TICKS_6 0x00006ac8 4913 #define BCE_HC_TX_TICKS_6_VALUE (0x3ffL<<0) 4914 #define BCE_HC_TX_TICKS_6_INT (0x3ffL<<16) 4915 4916 #define BCE_HC_COM_TICKS_6 0x00006acc 4917 #define BCE_HC_COM_TICKS_6_VALUE (0x3ffL<<0) 4918 #define BCE_HC_COM_TICKS_6_INT (0x3ffL<<16) 4919 4920 #define BCE_HC_CMD_TICKS_6 0x00006ad0 4921 #define BCE_HC_CMD_TICKS_6_VALUE (0x3ffL<<0) 4922 #define BCE_HC_CMD_TICKS_6_INT (0x3ffL<<16) 4923 4924 #define BCE_HC_PERIODIC_TICKS_6 0x00006ad4 4925 #define BCE_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0) 4926 #define BCE_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4927 4928 #define BCE_HC_SB_CONFIG_7 0x00006ad8 4929 #define BCE_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1) 4930 #define BCE_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2) 4931 #define BCE_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3) 4932 #define BCE_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4) 4933 #define BCE_HC_SB_CONFIG_7_PER_MODE (1L<<16) 4934 #define BCE_HC_SB_CONFIG_7_ONE_SHOT (1L<<17) 4935 #define BCE_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18) 4936 #define BCE_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20) 4937 4938 #define BCE_HC_TX_QUICK_CONS_TRIP_7 0x00006adc 4939 #define BCE_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0) 4940 #define BCE_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16) 4941 4942 #define BCE_HC_COMP_PROD_TRIP_7 0x00006ae0 4943 #define BCE_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0) 4944 #define BCE_HC_COMP_PROD_TRIP_7_INT (0xffL<<16) 4945 4946 #define BCE_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4 4947 #define BCE_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0) 4948 #define BCE_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16) 4949 4950 #define BCE_HC_RX_TICKS_7 0x00006ae8 4951 #define BCE_HC_RX_TICKS_7_VALUE (0x3ffL<<0) 4952 #define BCE_HC_RX_TICKS_7_INT (0x3ffL<<16) 4953 4954 #define BCE_HC_TX_TICKS_7 0x00006aec 4955 #define BCE_HC_TX_TICKS_7_VALUE (0x3ffL<<0) 4956 #define BCE_HC_TX_TICKS_7_INT (0x3ffL<<16) 4957 4958 #define BCE_HC_COM_TICKS_7 0x00006af0 4959 #define BCE_HC_COM_TICKS_7_VALUE (0x3ffL<<0) 4960 #define BCE_HC_COM_TICKS_7_INT (0x3ffL<<16) 4961 4962 #define BCE_HC_CMD_TICKS_7 0x00006af4 4963 #define BCE_HC_CMD_TICKS_7_VALUE (0x3ffL<<0) 4964 #define BCE_HC_CMD_TICKS_7_INT (0x3ffL<<16) 4965 4966 #define BCE_HC_PERIODIC_TICKS_7 0x00006af8 4967 #define BCE_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0) 4968 #define BCE_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16) 4969 4970 #define BCE_HC_SB_CONFIG_8 0x00006afc 4971 #define BCE_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1) 4972 #define BCE_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2) 4973 #define BCE_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3) 4974 #define BCE_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4) 4975 #define BCE_HC_SB_CONFIG_8_PER_MODE (1L<<16) 4976 #define BCE_HC_SB_CONFIG_8_ONE_SHOT (1L<<17) 4977 #define BCE_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18) 4978 #define BCE_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20) 4979 4980 #define BCE_HC_TX_QUICK_CONS_TRIP_8 0x00006b00 4981 #define BCE_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0) 4982 #define BCE_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16) 4983 4984 #define BCE_HC_COMP_PROD_TRIP_8 0x00006b04 4985 #define BCE_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0) 4986 #define BCE_HC_COMP_PROD_TRIP_8_INT (0xffL<<16) 4987 4988 #define BCE_HC_RX_QUICK_CONS_TRIP_8 0x00006b08 4989 #define BCE_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0) 4990 #define BCE_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16) 4991 4992 #define BCE_HC_RX_TICKS_8 0x00006b0c 4993 #define BCE_HC_RX_TICKS_8_VALUE (0x3ffL<<0) 4994 #define BCE_HC_RX_TICKS_8_INT (0x3ffL<<16) 4995 4996 #define BCE_HC_TX_TICKS_8 0x00006b10 4997 #define BCE_HC_TX_TICKS_8_VALUE (0x3ffL<<0) 4998 #define BCE_HC_TX_TICKS_8_INT (0x3ffL<<16) 4999 5000 #define BCE_HC_COM_TICKS_8 0x00006b14 5001 #define BCE_HC_COM_TICKS_8_VALUE (0x3ffL<<0) 5002 #define BCE_HC_COM_TICKS_8_INT (0x3ffL<<16) 5003 5004 #define BCE_HC_CMD_TICKS_8 0x00006b18 5005 #define BCE_HC_CMD_TICKS_8_VALUE (0x3ffL<<0) 5006 #define BCE_HC_CMD_TICKS_8_INT (0x3ffL<<16) 5007 5008 #define BCE_HC_PERIODIC_TICKS_8 0x00006b1c 5009 #define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0) 5010 #define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16) 5011 5012 #define BCE_HC_SB_CONFIG_SIZE \ 5013 (BCE_HC_SB_CONFIG_2 - BCE_HC_SB_CONFIG_1) 5014 #define BCE_HC_COMP_PROD_TRIP_OFF \ 5015 (BCE_HC_COMP_PROD_TRIP_1 - BCE_HC_SB_CONFIG_1) 5016 #define BCE_HC_COM_TICKS_OFF \ 5017 (BCE_HC_COM_TICKS_1 - BCE_HC_SB_CONFIG_1) 5018 #define BCE_HC_CMD_TICKS_OFF \ 5019 (BCE_HC_CMD_TICKS_1 - BCE_HC_SB_CONFIG_1) 5020 #define BCE_HC_TX_QUICK_CONS_TRIP_OFF \ 5021 (BCE_HC_TX_QUICK_CONS_TRIP_1 - BCE_HC_SB_CONFIG_1) 5022 #define BCE_HC_TX_TICKS_OFF \ 5023 (BCE_HC_TX_TICKS_1 - BCE_HC_SB_CONFIG_1) 5024 #define BCE_HC_RX_QUICK_CONS_TRIP_OFF \ 5025 (BCE_HC_RX_QUICK_CONS_TRIP_1 - BCE_HC_SB_CONFIG_1) 5026 #define BCE_HC_RX_TICKS_OFF \ 5027 (BCE_HC_RX_TICKS_1 - BCE_HC_SB_CONFIG_1) 5028 5029 5030 /* 5031 * txp_reg definition 5032 * offset: 0x40000 5033 */ 5034 #define BCE_TXP_CPU_MODE 0x00045000 5035 #define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) 5036 #define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) 5037 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5038 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5039 #define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 5040 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5041 #define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) 5042 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5043 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5044 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5045 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5046 5047 #define BCE_TXP_CPU_STATE 0x00045004 5048 #define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) 5049 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5050 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5051 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5052 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5053 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5054 #define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5055 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5056 #define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 5057 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5058 #define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) 5059 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5060 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5061 #define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 5062 5063 #define BCE_TXP_CPU_EVENT_MASK 0x00045008 5064 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5065 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5066 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5067 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5068 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5069 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5070 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5071 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5072 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5073 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5074 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5075 5076 #define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c 5077 #define BCE_TXP_CPU_INSTRUCTION 0x00045020 5078 #define BCE_TXP_CPU_DATA_ACCESS 0x00045024 5079 #define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 5080 #define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 5081 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 5082 #define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 5083 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5084 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5085 5086 #define BCE_TXP_CPU_REG_FILE 0x00045200 5087 #define BCE_TXP_FTQ_DATA 0x000453c0 5088 #define BCE_TXP_FTQ_CMD 0x000453f8 5089 #define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5090 #define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) 5091 #define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 5092 #define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 5093 #define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) 5094 #define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) 5095 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 5096 #define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) 5097 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 5098 #define BCE_TXP_FTQ_CMD_POP (1L<<30) 5099 #define BCE_TXP_FTQ_CMD_BUSY (1L<<31) 5100 5101 #define BCE_TXP_FTQ_CTL 0x000453fc 5102 #define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) 5103 #define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) 5104 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5105 #define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5106 #define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5107 5108 #define BCE_TXP_SCRATCH 0x00060000 5109 5110 5111 /* 5112 * tpat_reg definition 5113 * offset: 0x80000 5114 */ 5115 #define BCE_TPAT_CPU_MODE 0x00085000 5116 #define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 5117 #define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) 5118 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5119 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5120 #define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 5121 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 5122 #define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 5123 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5124 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5125 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5126 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5127 5128 #define BCE_TPAT_CPU_STATE 0x00085004 5129 #define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 5130 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 5131 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5132 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5133 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5134 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 5135 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 5136 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5137 #define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 5138 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5139 #define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 5140 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5141 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 5142 #define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 5143 5144 #define BCE_TPAT_CPU_EVENT_MASK 0x00085008 5145 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5146 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5147 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5148 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5149 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5150 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5151 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5152 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5153 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5154 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5155 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5156 5157 #define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 5158 #define BCE_TPAT_CPU_INSTRUCTION 0x00085020 5159 #define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 5160 #define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 5161 #define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 5162 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 5163 #define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 5164 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5165 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5166 5167 #define BCE_TPAT_CPU_REG_FILE 0x00085200 5168 #define BCE_TPAT_FTQ_DATA 0x000853c0 5169 #define BCE_TPAT_FTQ_CMD 0x000853f8 5170 #define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 5171 #define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) 5172 #define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 5173 #define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 5174 #define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 5175 #define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) 5176 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 5177 #define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 5178 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 5179 #define BCE_TPAT_FTQ_CMD_POP (1L<<30) 5180 #define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) 5181 5182 #define BCE_TPAT_FTQ_CTL 0x000853fc 5183 #define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) 5184 #define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 5185 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5186 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5187 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5188 5189 #define BCE_TPAT_SCRATCH 0x000a0000 5190 5191 5192 /* 5193 * rxp_reg definition 5194 * offset: 0xc0000 5195 */ 5196 #define BCE_RXP_CPU_MODE 0x000c5000 5197 #define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) 5198 #define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) 5199 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5200 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5201 #define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 5202 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5203 #define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) 5204 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5205 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5206 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5207 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5208 5209 #define BCE_RXP_CPU_STATE 0x000c5004 5210 #define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) 5211 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5212 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5213 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5214 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5215 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5216 #define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 5217 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5218 #define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 5219 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5220 #define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) 5221 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5222 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5223 #define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 5224 5225 #define BCE_RXP_CPU_EVENT_MASK 0x000c5008 5226 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5227 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5228 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5229 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5230 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5231 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5232 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5233 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5234 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5235 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5236 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5237 5238 #define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c 5239 #define BCE_RXP_CPU_INSTRUCTION 0x000c5020 5240 #define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 5241 #define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 5242 #define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 5243 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 5244 #define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 5245 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5246 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5247 5248 #define BCE_RXP_CPU_REG_FILE 0x000c5200 5249 #define BCE_RXP_CFTQ_DATA 0x000c5380 5250 #define BCE_RXP_CFTQ_CMD 0x000c53b8 5251 #define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 5252 #define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) 5253 #define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 5254 #define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 5255 #define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 5256 #define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) 5257 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 5258 #define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 5259 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 5260 #define BCE_RXP_CFTQ_CMD_POP (1L<<30) 5261 #define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) 5262 5263 #define BCE_RXP_CFTQ_CTL 0x000c53bc 5264 #define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) 5265 #define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 5266 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 5267 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5268 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5269 5270 #define BCE_RXP_FTQ_DATA 0x000c53c0 5271 #define BCE_RXP_FTQ_CMD 0x000c53f8 5272 #define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 5273 #define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) 5274 #define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 5275 #define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 5276 #define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) 5277 #define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) 5278 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 5279 #define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) 5280 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 5281 #define BCE_RXP_FTQ_CMD_POP (1L<<30) 5282 #define BCE_RXP_FTQ_CMD_BUSY (1L<<31) 5283 5284 #define BCE_RXP_FTQ_CTL 0x000c53fc 5285 #define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) 5286 #define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) 5287 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5288 #define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5289 #define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5290 5291 #define BCE_RXP_SCRATCH 0x000e0000 5292 #define BCE_RXP_SCRATCH_RXP_FLOOD 0x000e0024 5293 #define BCE_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038 5294 #define BCE_RXP_SCRATCH_RSS_TBL 0x000e003c 5295 #define BCE_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES 128 5296 5297 5298 /* 5299 * com_reg definition 5300 * offset: 0x100000 5301 */ 5302 #define BCE_COM_CPU_MODE 0x00105000 5303 #define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) 5304 #define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) 5305 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5306 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5307 #define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) 5308 #define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 5309 #define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) 5310 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5311 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5312 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5313 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5314 5315 #define BCE_COM_CPU_STATE 0x00105004 5316 #define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) 5317 #define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 5318 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5319 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5320 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5321 #define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 5322 #define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 5323 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5324 #define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) 5325 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5326 #define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) 5327 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5328 #define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 5329 #define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) 5330 5331 #define BCE_COM_CPU_EVENT_MASK 0x00105008 5332 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5333 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5334 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5335 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5336 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5337 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5338 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5339 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5340 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5341 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5342 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5343 5344 #define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c 5345 #define BCE_COM_CPU_INSTRUCTION 0x00105020 5346 #define BCE_COM_CPU_DATA_ACCESS 0x00105024 5347 #define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 5348 #define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c 5349 #define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 5350 #define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 5351 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5352 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5353 5354 #define BCE_COM_CPU_REG_FILE 0x00105200 5355 #define BCE_COM_COMXQ_FTQ_DATA 0x00105340 5356 #define BCE_COM_COMXQ_FTQ_CMD 0x00105378 5357 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5358 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 5359 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5360 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5361 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 5362 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 5363 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5364 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 5365 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5366 #define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) 5367 #define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 5368 5369 #define BCE_COM_COMXQ_FTQ_CTL 0x0010537c 5370 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 5371 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 5372 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5373 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5374 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5375 5376 #define BCE_COM_COMTQ_FTQ_DATA 0x00105380 5377 #define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 5378 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5379 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 5380 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5381 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5382 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 5383 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 5384 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5385 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 5386 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5387 #define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) 5388 #define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 5389 5390 #define BCE_COM_COMTQ_FTQ_CTL 0x001053bc 5391 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 5392 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 5393 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5394 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5395 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5396 5397 #define BCE_COM_COMQ_FTQ_DATA 0x001053c0 5398 #define BCE_COM_COMQ_FTQ_CMD 0x001053f8 5399 #define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5400 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 5401 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5402 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5403 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 5404 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 5405 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5406 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 5407 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5408 #define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) 5409 #define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 5410 5411 #define BCE_COM_COMQ_FTQ_CTL 0x001053fc 5412 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 5413 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 5414 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5415 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5416 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5417 5418 #define BCE_COM_SCRATCH 0x00120000 5419 5420 5421 /* 5422 * cp_reg definition 5423 * offset: 0x180000 5424 */ 5425 #define BCE_CP_CPU_MODE 0x00185000 5426 #define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) 5427 #define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) 5428 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5429 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5430 #define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) 5431 #define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5432 #define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) 5433 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5434 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5435 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5436 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5437 5438 #define BCE_CP_CPU_STATE 0x00185004 5439 #define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) 5440 #define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5441 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5442 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5443 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5444 #define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5445 #define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 5446 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5447 #define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) 5448 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5449 #define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) 5450 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5451 #define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5452 #define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) 5453 5454 #define BCE_CP_CPU_EVENT_MASK 0x00185008 5455 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5456 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5457 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5458 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5459 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5460 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5461 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5462 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5463 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5464 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5465 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5466 5467 #define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c 5468 #define BCE_CP_CPU_INSTRUCTION 0x00185020 5469 #define BCE_CP_CPU_DATA_ACCESS 0x00185024 5470 #define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 5471 #define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c 5472 #define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 5473 #define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 5474 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5475 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5476 5477 #define BCE_CP_CPU_REG_FILE 0x00185200 5478 #define BCE_CP_CPQ_FTQ_DATA 0x001853c0 5479 #define BCE_CP_CPQ_FTQ_CMD 0x001853f8 5480 #define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5481 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 5482 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5483 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5484 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 5485 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 5486 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5487 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 5488 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5489 #define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) 5490 #define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 5491 5492 #define BCE_CP_CPQ_FTQ_CTL 0x001853fc 5493 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 5494 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 5495 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5496 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5497 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5498 5499 #define BCE_CP_SCRATCH 0x001a0000 5500 5501 5502 /* 5503 * mcp_reg definition 5504 * offset: 0x140000 5505 */ 5506 #define BCE_MCP_CPU_MODE 0x00145000 5507 #define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) 5508 #define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) 5509 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 5510 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 5511 #define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 5512 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 5513 #define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) 5514 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 5515 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 5516 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 5517 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 5518 5519 #define BCE_MCP_CPU_STATE 0x00145004 5520 #define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) 5521 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 5522 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 5523 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 5524 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 5525 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 5526 #define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 5527 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 5528 #define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 5529 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 5530 #define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) 5531 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 5532 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 5533 #define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 5534 5535 #define BCE_MCP_CPU_EVENT_MASK 0x00145008 5536 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 5537 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 5538 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 5539 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 5540 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 5541 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 5542 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 5543 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 5544 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 5545 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 5546 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 5547 5548 #define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c 5549 #define BCE_MCP_CPU_INSTRUCTION 0x00145020 5550 #define BCE_MCP_CPU_DATA_ACCESS 0x00145024 5551 #define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 5552 #define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 5553 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 5554 #define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 5555 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 5556 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 5557 5558 #define BCE_MCP_CPU_REG_FILE 0x00145200 5559 #define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 5560 #define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 5561 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 5562 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 5563 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 5564 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 5565 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 5566 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 5567 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 5568 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 5569 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 5570 #define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 5571 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 5572 5573 #define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc 5574 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 5575 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 5576 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 5577 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 5578 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 5579 5580 #define BCE_MCP_ROM 0x00150000 5581 #define BCE_MCP_SCRATCH 0x00160000 5582 5583 #define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH 5584 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 5585 #define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 5586 #define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 5587 #define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 5588 5589 #define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 5590 #define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 5591 5592 /****************************************************************************/ 5593 /* End machine generated definitions. */ 5594 /****************************************************************************/ 5595 5596 /****************************************************************************/ 5597 /* Begin firmware definitions. */ 5598 /****************************************************************************/ 5599 /* The following definitions refer to pre-defined locations in processor */ 5600 /* memory space which allows the driver to enable particular functionality */ 5601 /* within the firmware or read specfic information about the running */ 5602 /* firmware. */ 5603 /****************************************************************************/ 5604 5605 /* 5606 * Perfect match control register. 5607 * 0 = Default. All received unicst packets matching MAC address 5608 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue 5609 * 0, all other perfect match registers are reserved. 5610 * 1 = All received unicast packets matching MAC address 5611 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0, 5612 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc. 5613 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register 5614 * are sent to receive queue 0. 5615 */ 5616 #define BCE_RXP_PM_CTRL 0x0e00d0 5617 5618 /* 5619 * This firmware statistic records the number of frames that 5620 * were dropped because there were no buffers available in the 5621 * receive chain. 5622 */ 5623 #define BCE_COM_NO_BUFFERS 0x120084 5624 /****************************************************************************/ 5625 /* End firmware definitions. */ 5626 /****************************************************************************/ 5627 5628 #define NUM_MC_HASH_REGISTERS 8 5629 5630 5631 #define DMA_READ_CHANS 5 5632 #define DMA_WRITE_CHANS 3 5633 5634 /* Use the natural page size of the host CPU. */ 5635 /* XXX: This has only been tested on x86_64/i386 systems using 4KB pages. */ 5636 #define BCM_PAGE_BITS PAGE_SHIFT 5637 #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) 5638 5639 #define BCE_TX_BD_SHIFT 4 /* struct tx_bd */ 5640 #define BCE_TX_BD_PAGE_SHIFT (BCM_PAGE_BITS - BCE_TX_BD_SHIFT) 5641 5642 #define BCE_RX_BD_SHIFT 4 /* struct rx_bd */ 5643 #define BCE_RX_BD_PAGE_SHIFT (BCM_PAGE_BITS - BCE_RX_BD_SHIFT) 5644 5645 #define TX_PAGES_DEFAULT 2 5646 #define TX_PAGES_MAX 256 5647 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 5648 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 5649 #define TOTAL_TX_BD(txr) (TOTAL_TX_BD_PER_PAGE * (txr)->tx_pages) 5650 #define USABLE_TX_BD(txr) (USABLE_TX_BD_PER_PAGE * (txr)->tx_pages) 5651 #define MAX_TX_BD(txr) (TOTAL_TX_BD((txr)) - 1) 5652 #define BCE_TX_SPARE_SPACE 33 5653 5654 #define RX_PAGES_DEFAULT 2 5655 #define RX_PAGES_MAX 256 5656 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 5657 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 5658 #define TOTAL_RX_BD(rxr) (TOTAL_RX_BD_PER_PAGE * (rxr)->rx_pages) 5659 #define USABLE_RX_BD(rxr) (USABLE_RX_BD_PER_PAGE * (rxr)->rx_pages) 5660 #define MAX_RX_BD(rxr) (TOTAL_RX_BD((rxr)) - 1) 5661 5662 /* Advance to the next tx_bd, skipping any next page pointers. */ 5663 #define NEXT_TX_BD(x) \ 5664 (((x) & USABLE_TX_BD_PER_PAGE) == (USABLE_TX_BD_PER_PAGE - 1)) ? \ 5665 (x) + 2 : (x) + 1 5666 5667 #define TX_CHAIN_IDX(txr, x) ((x) & MAX_TX_BD((txr))) 5668 5669 #define TX_PAGE(x) \ 5670 (((x) & ~USABLE_TX_BD_PER_PAGE) >> BCE_TX_BD_PAGE_SHIFT) 5671 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 5672 5673 /* Advance to the next rx_bd, skipping any next page pointers. */ 5674 #define NEXT_RX_BD(x) \ 5675 (((x) & USABLE_RX_BD_PER_PAGE) == (USABLE_RX_BD_PER_PAGE - 1)) ? \ 5676 (x) + 2 : (x) + 1 5677 5678 #define RX_CHAIN_IDX(rxr, x) ((x) & MAX_RX_BD(rxr)) 5679 5680 #define RX_PAGE(x) \ 5681 (((x) & ~USABLE_RX_BD_PER_PAGE) >> BCE_RX_BD_PAGE_SHIFT) 5682 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 5683 5684 /* Context size. */ 5685 #define CTX_SHIFT 7 5686 #define CTX_SIZE (1 << CTX_SHIFT) 5687 #define CTX_MASK (CTX_SIZE - 1) 5688 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 5689 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 5690 5691 #define PHY_CTX_SHIFT 6 5692 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 5693 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 5694 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 5695 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 5696 5697 #define MB_KERNEL_CTX_SHIFT 8 5698 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 5699 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 5700 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 5701 5702 #define MAX_CID_CNT 0x4000 5703 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 5704 #define INVALID_CID_ADDR 0xffffffff 5705 5706 #define TX_TSS_CID 32 5707 #define TX_CID 16 5708 #define RX_RSS_CID 4 5709 #define RX_CID 0 5710 5711 /****************************************************************************/ 5712 /* BCE Processor Firmwware Load Definitions */ 5713 /****************************************************************************/ 5714 5715 struct cpu_reg { 5716 uint32_t mode; 5717 uint32_t mode_value_halt; 5718 uint32_t mode_value_sstep; 5719 5720 uint32_t state; 5721 uint32_t state_value_clear; 5722 5723 uint32_t gpr0; 5724 uint32_t evmask; 5725 uint32_t pc; 5726 uint32_t inst; 5727 uint32_t bp; 5728 5729 uint32_t spad_base; 5730 5731 uint32_t mips_view_base; 5732 }; 5733 5734 struct fw_info { 5735 uint32_t ver_major; 5736 uint32_t ver_minor; 5737 uint32_t ver_fix; 5738 5739 uint32_t start_addr; 5740 5741 /* Text section. */ 5742 uint32_t text_addr; 5743 uint32_t text_len; 5744 uint32_t text_index; 5745 uint32_t *text; 5746 5747 /* Data section. */ 5748 uint32_t data_addr; 5749 uint32_t data_len; 5750 uint32_t data_index; 5751 uint32_t *data; 5752 5753 /* SBSS section. */ 5754 uint32_t sbss_addr; 5755 uint32_t sbss_len; 5756 uint32_t sbss_index; 5757 uint32_t *sbss; 5758 5759 /* BSS section. */ 5760 uint32_t bss_addr; 5761 uint32_t bss_len; 5762 uint32_t bss_index; 5763 uint32_t *bss; 5764 5765 /* Read-only section. */ 5766 uint32_t rodata_addr; 5767 uint32_t rodata_len; 5768 uint32_t rodata_index; 5769 uint32_t *rodata; 5770 }; 5771 5772 #define RV2P_PROC1 0 5773 #define RV2P_PROC2 1 5774 5775 #define BCE_MIREG(x) ((x & 0x1F) << 16) 5776 #define BCE_MIPHY(x) ((x & 0x1F) << 21) 5777 #define BCE_PHY_TIMEOUT 50 5778 5779 #define BCE_NVRAM_SIZE 0x200 5780 #define BCE_NVRAM_MAGIC 0x669955aa 5781 #define BCE_CRC32_RESIDUAL 0xdebb20e3 5782 5783 #define BCE_TX_TIMEOUT 5 5784 5785 #define BCE_MAX_SEGMENTS 40 5786 #define BCE_DMA_ALIGN 8 5787 #define BCE_DMA_RX_ALIGN 16 5788 #define BCE_DMA_BOUNDARY 0 5789 5790 /* The BCM5708 has a problem with addresses greater that 40bits. */ 5791 /* Handle the sizing issue in an architecture agnostic fashion. */ 5792 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 5793 #define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR 5794 #else 5795 #define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF 5796 #endif 5797 5798 /* 5799 * XXX Checksum offload involving IP fragments seems to cause problems on 5800 * transmit. Disable it for now, hopefully there will be a more elegant 5801 * solution later. 5802 */ 5803 #ifdef BCE_IP_CSUM 5804 #define BCE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 5805 #else 5806 #define BCE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 5807 #endif 5808 5809 /* NOTE: This hardware also can do VLAN csum offload */ 5810 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ 5811 IFCAP_VLAN_HWTAGGING | \ 5812 IFCAP_HWCSUM | \ 5813 IFCAP_TSO) 5814 5815 #define BCE_MIN_MTU 60 5816 #define BCE_MIN_ETHER_MTU 64 5817 5818 #define BCE_MAX_STD_MTU 1500 5819 #define BCE_MAX_STD_ETHER_MTU 1518 5820 #define BCE_MAX_STD_ETHER_MTU_VLAN 1522 5821 5822 #define BCE_MAX_JUMBO_MTU 9000 5823 #define BCE_MAX_JUMBO_ETHER_MTU 9018 5824 #define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 5825 5826 #if 0 5827 #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + EVL_ENCAPLEN /* 9022 */ 5828 #endif 5829 5830 /****************************************************************************/ 5831 /* BCE Device State Data Structure */ 5832 /****************************************************************************/ 5833 5834 #define BCE_STATUS_BLK_SZ sizeof(struct status_block) 5835 #define BCE_STATS_BLK_SZ sizeof(struct statistics_block) 5836 #define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 5837 #define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 5838 #define BCE_CTX_BLK_SZ 0x2000 5839 5840 struct bce_tx_buf { 5841 bus_dmamap_t tx_mbuf_map; 5842 struct mbuf *tx_mbuf_ptr; 5843 }; 5844 5845 struct bce_tx_ring { 5846 struct lwkt_serialize tx_serialize; 5847 struct bce_softc *sc; 5848 uint32_t tx_cid; 5849 volatile uint16_t *tx_hw_cons; 5850 struct ifaltq_subque *ifsq; 5851 int tx_pages; 5852 int tx_wreg; 5853 uint16_t tx_prod; 5854 uint16_t tx_cons; 5855 uint32_t tx_prod_bseq; /* Counts the bytes used. */ 5856 5857 uint16_t used_tx_bd; 5858 uint16_t max_tx_bd; 5859 5860 /* H/W maintained TX buffer descriptor chain structure. */ 5861 struct tx_bd **tx_bd_chain; /* tx_pages */ 5862 5863 /* S/W maintained mbuf TX chain structure. */ 5864 bus_dma_tag_t tx_mbuf_tag; 5865 struct bce_tx_buf *tx_bufs; /* TOTAL_TX_BD */ 5866 5867 struct ifsubq_watchdog tx_watchdog; 5868 5869 u_long tx_pkts; 5870 5871 bus_dma_tag_t tx_bd_chain_tag; 5872 bus_dmamap_t *tx_bd_chain_map; /* tx_pages */ 5873 bus_addr_t *tx_bd_chain_paddr; /* tx_pages */ 5874 } __cachealign; 5875 5876 struct bce_msix_data { 5877 struct lwkt_serialize *msix_serialize; 5878 5879 driver_intr_t *msix_func; 5880 void *msix_arg; 5881 5882 int msix_cpuid; 5883 char msix_desc[32]; 5884 int msix_rid; 5885 struct resource *msix_res; 5886 void *msix_handle; 5887 }; 5888 5889 #define BCE_RX_RING_MAX 8 5890 #define BCE_TX_RING_MAX 8 5891 #define BCE_MSIX_MAX 9 5892 5893 struct bce_rx_buf { 5894 bus_dmamap_t rx_mbuf_map; 5895 struct mbuf *rx_mbuf_ptr; 5896 bus_addr_t rx_mbuf_paddr; 5897 }; 5898 5899 struct bce_rx_ring { 5900 struct lwkt_serialize rx_serialize; 5901 struct bce_softc *sc; 5902 int idx; 5903 5904 volatile uint16_t *hw_status_idx; 5905 uint16_t last_status_idx; 5906 5907 uint32_t rx_cid; 5908 volatile uint16_t *rx_hw_cons; 5909 int rx_pages; 5910 uint16_t rx_prod; 5911 uint16_t rx_cons; 5912 uint32_t rx_prod_bseq; /* Counts the bytes used. */ 5913 5914 uint16_t free_rx_bd; 5915 uint16_t max_rx_bd; 5916 5917 /* H/W maintained RX buffer descriptor chain structure. */ 5918 struct rx_bd **rx_bd_chain; /* rx_pages */ 5919 5920 /* S/W maintained mbuf RX chain structure. */ 5921 bus_dma_tag_t rx_mbuf_tag; 5922 bus_dmamap_t rx_mbuf_tmpmap; 5923 struct bce_rx_buf *rx_bufs; /* TOTAL_RX_BD */ 5924 5925 u_long rx_pkts; 5926 5927 bus_dma_tag_t rx_bd_chain_tag; 5928 bus_dmamap_t *rx_bd_chain_map; /* rx_pages */ 5929 bus_addr_t *rx_bd_chain_paddr; /* rx_pages */ 5930 } __cachealign; 5931 5932 struct bce_softc { 5933 struct arpcom arpcom; 5934 device_t bce_dev; 5935 struct resource *bce_res_mem; /* Device resource handle */ 5936 bus_space_tag_t bce_btag; /* Device bus tag */ 5937 bus_space_handle_t bce_bhandle; /* Device bus handle */ 5938 struct resource *bce_res_irq; /* IRQ Resource Handle */ 5939 void *bce_intrhand; /* Interrupt handler */ 5940 int bce_irq_type; 5941 int bce_irq_rid; 5942 5943 /* ASIC Chip ID. */ 5944 uint32_t bce_chipid; 5945 5946 /* General controller flags. */ 5947 uint32_t bce_flags; 5948 #define BCE_PCIX_FLAG 0x00000001 5949 #define BCE_PCI_32BIT_FLAG 0x00000002 5950 #define BCE_CHECK_MSI_FLAG 0x00000004 5951 #define BCE_NO_WOL_FLAG 0x00000008 5952 #define BCE_USING_DAC_FLAG 0x00000010 5953 #define BCE_MFW_ENABLE_FLAG 0x00000040 /* Management F/W is enabled */ 5954 #define BCE_PCIE_FLAG 0x00000200 5955 #define BCE_ONESHOT_MSI_FLAG 0x00000400 5956 5957 uint32_t bce_cap_flags; 5958 #define BCE_PCIE_CAPABLE_FLAG 0x00000004 5959 #define BCE_PCIX_CAPABLE_FLAG 0x00000008 5960 5961 /* PHY specific flags. */ 5962 uint32_t bce_phy_flags; 5963 #define BCE_PHY_SERDES_FLAG 0x001 5964 #define BCE_PHY_CRC_FIX_FLAG 0x002 5965 #define BCE_PHY_PARALLEL_DETECT_FLAG 0x004 5966 #define BCE_PHY_2_5G_CAPABLE_FLAG 0x008 5967 #define BCE_PHY_INT_MODE_MASK_FLAG 0x300 5968 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 5969 #define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x200 5970 5971 uint16_t bus_speed_mhz; /* PCI bus speed */ 5972 uint16_t link_width; /* PCIe link width */ 5973 uint16_t link_speed; /* PCIe link speed */ 5974 const struct flash_spec *bce_flash_info;/* Flash NVRAM settings */ 5975 uint32_t bce_flash_size; /* Flash NVRAM size */ 5976 uint32_t bce_shmem_base; /* Shared Memory base address */ 5977 uint32_t hc_command; /* BCE_HC_COMMAND cache */ 5978 uint32_t bc_state; /* Bootcode state */ 5979 5980 /* Tracks the version of bootcode firmware. */ 5981 char bce_bc_ver[32]; 5982 char bce_mfw_ver[32]; 5983 5984 /* 5985 * Tracks the state of the firmware. 0 = Running while any 5986 * other value indicates that the firmware is not responding. 5987 */ 5988 int bce_fw_timed_out; 5989 5990 /* Tracks whether firmware has lost the driver's pulse. */ 5991 int bce_drv_cardiac_arrest; 5992 5993 /* 5994 * An incrementing sequence used to coordinate messages passed 5995 * from the driver to the firmware. 5996 */ 5997 uint16_t bce_fw_wr_seq; 5998 5999 /* 6000 * An incrementing sequence used to let the firmware know that 6001 * the driver is still operating. Without the pulse, management 6002 * firmware such as IPMI or UMP will operate in OS absent state. 6003 */ 6004 uint16_t bce_fw_drv_pulse_wr_seq; 6005 6006 u_char eaddr[6]; /* Ethernet MAC address. */ 6007 6008 /* 6009 * These setting are used by the host coalescing (HC) block to 6010 * to control how often the status block, statistics block and 6011 * interrupts are generated. 6012 */ 6013 uint32_t bce_tx_quick_cons_trip_int; 6014 uint32_t bce_tx_quick_cons_trip; 6015 uint32_t bce_rx_quick_cons_trip_int; 6016 uint32_t bce_rx_quick_cons_trip; 6017 uint16_t bce_comp_prod_trip_int; 6018 uint16_t bce_comp_prod_trip; 6019 uint32_t bce_tx_ticks_int; 6020 uint32_t bce_tx_ticks; 6021 uint32_t bce_rx_ticks_int; 6022 uint32_t bce_rx_ticks; 6023 uint16_t bce_com_ticks_int; 6024 uint16_t bce_com_ticks; 6025 uint16_t bce_cmd_ticks_int; 6026 uint16_t bce_cmd_ticks; 6027 uint32_t bce_stats_ticks; 6028 uint32_t bce_coalchg_mask; /* BCE_COALMASK_ */ 6029 6030 /* The address of the integrated PHY on the MII bus. */ 6031 int bce_phy_addr; 6032 6033 /* The device handle for the MII bus child device. */ 6034 device_t bce_miibus; 6035 6036 int bce_link; 6037 int bce_timer_cpuid; 6038 struct callout bce_tick_callout; 6039 struct callout bce_pulse_callout; 6040 6041 boolean_t bce_msi_maylose; 6042 uint16_t bce_check_rx_cons; 6043 uint16_t bce_check_tx_cons; 6044 uint16_t bce_check_status_idx; 6045 struct callout bce_ckmsi_callout; 6046 6047 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 6048 uint32_t rx_mode; 6049 6050 /* Bus tag for the bce controller. */ 6051 bus_dma_tag_t parent_tag; 6052 6053 /* H/W maintained status block. */ 6054 bus_dma_tag_t status_tag; 6055 bus_dmamap_t status_map; 6056 struct status_block *status_block; /* virtual address */ 6057 bus_addr_t status_block_paddr; /* Physical address */ 6058 6059 /* H/W maintained statistics block. */ 6060 bus_dma_tag_t stats_tag; 6061 bus_dmamap_t stats_map; 6062 struct statistics_block *stats_block; /* Virtual address */ 6063 bus_addr_t stats_block_paddr; /* Physical address */ 6064 6065 #define BCE_CTX_PAGES 4 6066 /* H/W maintained context block. */ 6067 int ctx_pages; 6068 bus_dma_tag_t ctx_tag; 6069 /* DRC - Fix hard coded value. */ 6070 bus_dmamap_t ctx_map[BCE_CTX_PAGES]; 6071 void *ctx_block[BCE_CTX_PAGES]; /* Virtual address */ 6072 bus_addr_t ctx_paddr[BCE_CTX_PAGES]; /* Physical address */ 6073 6074 int serialize_cnt; 6075 struct lwkt_serialize **serializes; 6076 struct lwkt_serialize main_serialize; 6077 6078 int rss_debug; 6079 int npoll_ofs; 6080 int tx_ring_cnt; 6081 int rx_ring_cnt; 6082 int rx_ring_cnt2; 6083 struct bce_tx_ring *tx_rings; 6084 struct bce_rx_ring *rx_rings; 6085 6086 int bce_if_flags; 6087 6088 /* Provides access to hardware statistics through sysctl. */ 6089 uint64_t stat_IfHCInOctets; 6090 uint64_t stat_IfHCInBadOctets; 6091 uint64_t stat_IfHCOutOctets; 6092 uint64_t stat_IfHCOutBadOctets; 6093 uint64_t stat_IfHCInUcastPkts; 6094 uint64_t stat_IfHCInMulticastPkts; 6095 uint64_t stat_IfHCInBroadcastPkts; 6096 uint64_t stat_IfHCOutUcastPkts; 6097 uint64_t stat_IfHCOutMulticastPkts; 6098 uint64_t stat_IfHCOutBroadcastPkts; 6099 6100 uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 6101 uint32_t stat_Dot3StatsCarrierSenseErrors; 6102 uint32_t stat_Dot3StatsFCSErrors; 6103 uint32_t stat_Dot3StatsAlignmentErrors; 6104 uint32_t stat_Dot3StatsSingleCollisionFrames; 6105 uint32_t stat_Dot3StatsMultipleCollisionFrames; 6106 uint32_t stat_Dot3StatsDeferredTransmissions; 6107 uint32_t stat_Dot3StatsExcessiveCollisions; 6108 uint32_t stat_Dot3StatsLateCollisions; 6109 uint32_t stat_EtherStatsCollisions; 6110 uint32_t stat_EtherStatsFragments; 6111 uint32_t stat_EtherStatsJabbers; 6112 uint32_t stat_EtherStatsUndersizePkts; 6113 uint32_t stat_EtherStatsOverrsizePkts; 6114 uint32_t stat_EtherStatsPktsRx64Octets; 6115 uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; 6116 uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; 6117 uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; 6118 uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 6119 uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 6120 uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 6121 uint32_t stat_EtherStatsPktsTx64Octets; 6122 uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; 6123 uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; 6124 uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; 6125 uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 6126 uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 6127 uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 6128 uint32_t stat_XonPauseFramesReceived; 6129 uint32_t stat_XoffPauseFramesReceived; 6130 uint32_t stat_OutXonSent; 6131 uint32_t stat_OutXoffSent; 6132 uint32_t stat_FlowControlDone; 6133 uint32_t stat_MacControlFramesReceived; 6134 uint32_t stat_XoffStateEntered; 6135 uint32_t stat_IfInFramesL2FilterDiscards; 6136 uint32_t stat_IfInRuleCheckerDiscards; 6137 uint32_t stat_IfInFTQDiscards; 6138 uint32_t stat_IfInMBUFDiscards; 6139 uint32_t stat_IfInRuleCheckerP4Hit; 6140 uint32_t stat_CatchupInRuleCheckerDiscards; 6141 uint32_t stat_CatchupInFTQDiscards; 6142 uint32_t stat_CatchupInMBUFDiscards; 6143 uint32_t stat_CatchupInRuleCheckerP4Hit; 6144 6145 /* Provides access to certain firmware statistics. */ 6146 uint32_t com_no_buffers; 6147 6148 struct bce_msix_data bce_msix[BCE_MSIX_MAX]; 6149 }; 6150 6151 #define BCE_COALMASK_TX_BDS_INT 0x01 6152 #define BCE_COALMASK_TX_BDS 0x02 6153 #define BCE_COALMASK_TX_TICKS_INT 0x04 6154 #define BCE_COALMASK_TX_TICKS 0x08 6155 #define BCE_COALMASK_RX_BDS_INT 0x10 6156 #define BCE_COALMASK_RX_BDS 0x20 6157 #define BCE_COALMASK_RX_TICKS_INT 0x40 6158 #define BCE_COALMASK_RX_TICKS 0x80 6159 6160 #endif /* #ifndef _BCE_H_DEFINED */ 6161