1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* $FreeBSD: src/sys/dev/msk/if_msk.c,v 1.26 2007/12/05 09:41:58 remko Exp $ */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/param.h> 104 #include <sys/endian.h> 105 #include <sys/kernel.h> 106 #include <sys/bus.h> 107 #include <sys/in_cksum.h> 108 #include <sys/interrupt.h> 109 #include <sys/malloc.h> 110 #include <sys/proc.h> 111 #include <sys/rman.h> 112 #include <sys/serialize.h> 113 #include <sys/socket.h> 114 #include <sys/sockio.h> 115 #include <sys/sysctl.h> 116 117 #include <net/ethernet.h> 118 #include <net/if.h> 119 #include <net/bpf.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/ifq_var.h> 124 #include <net/vlan/if_vlan_var.h> 125 126 #include <netinet/ip.h> 127 #include <netinet/ip_var.h> 128 129 #include <dev/netif/mii_layer/miivar.h> 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 #include "if_mskreg.h" 135 136 /* "device miibus" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Devices supported by this driver. 143 */ 144 static const struct msk_product { 145 uint16_t msk_vendorid; 146 uint16_t msk_deviceid; 147 const char *msk_name; 148 } msk_products[] = { 149 { VENDORID_SK, DEVICEID_SK_YUKON2, 150 "SK-9Sxx Gigabit Ethernet" }, 151 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 152 "SK-9Exx Gigabit Ethernet"}, 153 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 154 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 155 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 156 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 157 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 158 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 159 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 160 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 161 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 162 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 163 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 164 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 165 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 166 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 167 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 168 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 169 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 170 "Marvell Yukon 88E8035 Fast Ethernet" }, 171 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 172 "Marvell Yukon 88E8036 Fast Ethernet" }, 173 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 174 "Marvell Yukon 88E8038 Fast Ethernet" }, 175 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 176 "Marvell Yukon 88E8039 Fast Ethernet" }, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 178 "Marvell Yukon 88E8040 Fast Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 180 "Marvell Yukon 88E8040T Fast Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 182 "Marvell Yukon 88E8042 Fast Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 184 "Marvell Yukon 88E8048 Fast Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 186 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 188 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 190 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 192 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 194 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 196 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 198 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 200 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 202 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 204 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 206 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 208 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 210 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 211 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 212 "D-Link 550SX Gigabit Ethernet" }, 213 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 214 "D-Link 560T Gigabit Ethernet" }, 215 { 0, 0, NULL } 216 }; 217 218 static const char *model_name[] = { 219 "Yukon XL", 220 "Yukon EC Ultra", 221 "Yukon EX", 222 "Yukon EC", 223 "Yukon FE", 224 "Yukon FE+", 225 "Yukon Supreme", 226 "Yukon Ultra 2", 227 "Yukon Unknown", 228 "Yukon Optima" 229 }; 230 231 static int mskc_probe(device_t); 232 static int mskc_attach(device_t); 233 static int mskc_detach(device_t); 234 static int mskc_shutdown(device_t); 235 static int mskc_suspend(device_t); 236 static int mskc_resume(device_t); 237 static void mskc_intr(void *); 238 239 static void mskc_reset(struct msk_softc *); 240 static void mskc_set_imtimer(struct msk_softc *); 241 static void mskc_intr_hwerr(struct msk_softc *); 242 static int mskc_handle_events(struct msk_softc *); 243 static void mskc_phy_power(struct msk_softc *, int); 244 static int mskc_setup_rambuffer(struct msk_softc *); 245 static int mskc_status_dma_alloc(struct msk_softc *); 246 static void mskc_status_dma_free(struct msk_softc *); 247 static int mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS); 248 static int mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS); 249 250 static int msk_probe(device_t); 251 static int msk_attach(device_t); 252 static int msk_detach(device_t); 253 static int msk_miibus_readreg(device_t, int, int); 254 static int msk_miibus_writereg(device_t, int, int, int); 255 static void msk_miibus_statchg(device_t); 256 257 static void msk_init(void *); 258 static int msk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 259 static void msk_start(struct ifnet *); 260 static void msk_watchdog(struct ifnet *); 261 static int msk_mediachange(struct ifnet *); 262 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 263 264 static void msk_tick(void *); 265 static void msk_intr_phy(struct msk_if_softc *); 266 static void msk_intr_gmac(struct msk_if_softc *); 267 static __inline void 268 msk_rxput(struct msk_if_softc *); 269 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 270 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 271 static void msk_txeof(struct msk_if_softc *, int); 272 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 273 static void msk_set_rambuffer(struct msk_if_softc *); 274 static void msk_stop(struct msk_if_softc *); 275 276 static int msk_txrx_dma_alloc(struct msk_if_softc *); 277 static void msk_txrx_dma_free(struct msk_if_softc *); 278 static int msk_init_rx_ring(struct msk_if_softc *); 279 static void msk_init_tx_ring(struct msk_if_softc *); 280 static __inline void 281 msk_discard_rxbuf(struct msk_if_softc *, int); 282 static int msk_newbuf(struct msk_if_softc *, int, int); 283 static int msk_encap(struct msk_if_softc *, struct mbuf **); 284 285 #ifdef MSK_JUMBO 286 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 287 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 288 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 289 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 290 static void *msk_jalloc(struct msk_if_softc *); 291 static void msk_jfree(void *, void *); 292 #endif 293 294 static int msk_phy_readreg(struct msk_if_softc *, int, int); 295 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 296 297 static void msk_rxfilter(struct msk_if_softc *); 298 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 299 static void msk_set_tx_stfwd(struct msk_if_softc *); 300 301 static int msk_dmamem_create(device_t, bus_size_t, bus_dma_tag_t *, 302 void **, bus_addr_t *, bus_dmamap_t *); 303 static void msk_dmamem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 304 305 static device_method_t mskc_methods[] = { 306 /* Device interface */ 307 DEVMETHOD(device_probe, mskc_probe), 308 DEVMETHOD(device_attach, mskc_attach), 309 DEVMETHOD(device_detach, mskc_detach), 310 DEVMETHOD(device_suspend, mskc_suspend), 311 DEVMETHOD(device_resume, mskc_resume), 312 DEVMETHOD(device_shutdown, mskc_shutdown), 313 314 /* bus interface */ 315 DEVMETHOD(bus_print_child, bus_generic_print_child), 316 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 317 318 { NULL, NULL } 319 }; 320 321 static DEFINE_CLASS_0(mskc, mskc_driver, mskc_methods, sizeof(struct msk_softc)); 322 static devclass_t mskc_devclass; 323 324 static device_method_t msk_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, msk_probe), 327 DEVMETHOD(device_attach, msk_attach), 328 DEVMETHOD(device_detach, msk_detach), 329 DEVMETHOD(device_shutdown, bus_generic_shutdown), 330 331 /* bus interface */ 332 DEVMETHOD(bus_print_child, bus_generic_print_child), 333 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 334 335 /* MII interface */ 336 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 337 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 338 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 339 340 { NULL, NULL } 341 }; 342 343 static DEFINE_CLASS_0(msk, msk_driver, msk_methods, sizeof(struct msk_if_softc)); 344 static devclass_t msk_devclass; 345 346 DECLARE_DUMMY_MODULE(if_msk); 347 DRIVER_MODULE(if_msk, pci, mskc_driver, mskc_devclass, NULL, NULL); 348 DRIVER_MODULE(if_msk, mskc, msk_driver, msk_devclass, NULL, NULL); 349 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL); 350 351 static int mskc_intr_rate = 0; 352 static int mskc_process_limit = MSK_PROC_DEFAULT; 353 354 TUNABLE_INT("hw.mskc.intr_rate", &mskc_intr_rate); 355 TUNABLE_INT("hw.mskc.process_limit", &mskc_process_limit); 356 357 static int 358 msk_miibus_readreg(device_t dev, int phy, int reg) 359 { 360 struct msk_if_softc *sc_if; 361 362 if (phy != PHY_ADDR_MARV) 363 return (0); 364 365 sc_if = device_get_softc(dev); 366 367 return (msk_phy_readreg(sc_if, phy, reg)); 368 } 369 370 static int 371 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 372 { 373 struct msk_softc *sc; 374 int i, val; 375 376 sc = sc_if->msk_softc; 377 378 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 379 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 380 381 for (i = 0; i < MSK_TIMEOUT; i++) { 382 DELAY(1); 383 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 384 if ((val & GM_SMI_CT_RD_VAL) != 0) { 385 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 386 break; 387 } 388 } 389 390 if (i == MSK_TIMEOUT) { 391 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 392 val = 0; 393 } 394 395 return (val); 396 } 397 398 static int 399 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 400 { 401 struct msk_if_softc *sc_if; 402 403 if (phy != PHY_ADDR_MARV) 404 return (0); 405 406 sc_if = device_get_softc(dev); 407 408 return (msk_phy_writereg(sc_if, phy, reg, val)); 409 } 410 411 static int 412 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 413 { 414 struct msk_softc *sc; 415 int i; 416 417 sc = sc_if->msk_softc; 418 419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 420 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 421 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 422 for (i = 0; i < MSK_TIMEOUT; i++) { 423 DELAY(1); 424 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 425 GM_SMI_CT_BUSY) == 0) 426 break; 427 } 428 if (i == MSK_TIMEOUT) 429 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 430 431 return (0); 432 } 433 434 static void 435 msk_miibus_statchg(device_t dev) 436 { 437 struct msk_if_softc *sc_if; 438 struct msk_softc *sc; 439 struct mii_data *mii; 440 struct ifnet *ifp; 441 uint32_t gmac; 442 443 sc_if = device_get_softc(dev); 444 sc = sc_if->msk_softc; 445 446 mii = device_get_softc(sc_if->msk_miibus); 447 ifp = sc_if->msk_ifp; 448 449 sc_if->msk_link = 0; 450 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 451 (IFM_AVALID | IFM_ACTIVE)) { 452 switch (IFM_SUBTYPE(mii->mii_media_active)) { 453 case IFM_10_T: 454 case IFM_100_TX: 455 sc_if->msk_link = 1; 456 break; 457 case IFM_1000_T: 458 case IFM_1000_SX: 459 case IFM_1000_LX: 460 case IFM_1000_CX: 461 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 462 sc_if->msk_link = 1; 463 break; 464 } 465 } 466 467 if (sc_if->msk_link != 0) { 468 /* Enable Tx FIFO Underrun. */ 469 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 470 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 471 /* 472 * Because mii(4) notify msk(4) that it detected link status 473 * change, there is no need to enable automatic 474 * speed/flow-control/duplex updates. 475 */ 476 gmac = GM_GPCR_AU_ALL_DIS; 477 switch (IFM_SUBTYPE(mii->mii_media_active)) { 478 case IFM_1000_SX: 479 case IFM_1000_T: 480 gmac |= GM_GPCR_SPEED_1000; 481 break; 482 case IFM_100_TX: 483 gmac |= GM_GPCR_SPEED_100; 484 break; 485 case IFM_10_T: 486 break; 487 } 488 489 if ((mii->mii_media_active & IFM_GMASK) & IFM_FDX) 490 gmac |= GM_GPCR_DUP_FULL; 491 else 492 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 493 /* Disable Rx flow control. */ 494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 495 gmac |= GM_GPCR_FC_RX_DIS; 496 /* Disable Tx flow control. */ 497 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 498 gmac |= GM_GPCR_FC_TX_DIS; 499 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 500 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 501 /* Read again to ensure writing. */ 502 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 503 504 gmac = GMC_PAUSE_OFF; 505 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) && 506 ((mii->mii_media_active & IFM_GMASK) & IFM_FDX)) 507 gmac = GMC_PAUSE_ON; 508 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 509 510 /* Enable PHY interrupt for FIFO underrun/overflow. */ 511 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 512 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 513 } else { 514 /* 515 * Link state changed to down. 516 * Disable PHY interrupts. 517 */ 518 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 519 /* Disable Rx/Tx MAC. */ 520 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 521 if (gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) { 522 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 523 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 524 /* Read again to ensure writing. */ 525 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 526 } 527 } 528 } 529 530 static void 531 msk_rxfilter(struct msk_if_softc *sc_if) 532 { 533 struct msk_softc *sc; 534 struct ifnet *ifp; 535 struct ifmultiaddr *ifma; 536 uint32_t mchash[2]; 537 uint32_t crc; 538 uint16_t mode; 539 540 sc = sc_if->msk_softc; 541 ifp = sc_if->msk_ifp; 542 543 bzero(mchash, sizeof(mchash)); 544 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 545 if ((ifp->if_flags & IFF_PROMISC) != 0) { 546 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 547 } else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 548 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 549 mchash[0] = 0xffff; 550 mchash[1] = 0xffff; 551 } else { 552 mode |= GM_RXCR_UCF_ENA; 553 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 554 if (ifma->ifma_addr->sa_family != AF_LINK) 555 continue; 556 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 557 ifma->ifma_addr), ETHER_ADDR_LEN); 558 /* Just want the 6 least significant bits. */ 559 crc &= 0x3f; 560 /* Set the corresponding bit in the hash table. */ 561 mchash[crc >> 5] |= 1 << (crc & 0x1f); 562 } 563 if (mchash[0] != 0 || mchash[1] != 0) 564 mode |= GM_RXCR_MCF_ENA; 565 } 566 567 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 568 mchash[0] & 0xffff); 569 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 570 (mchash[0] >> 16) & 0xffff); 571 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 572 mchash[1] & 0xffff); 573 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 574 (mchash[1] >> 16) & 0xffff); 575 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 576 } 577 578 static void 579 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 580 { 581 struct msk_softc *sc; 582 583 sc = sc_if->msk_softc; 584 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 585 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 586 RX_VLAN_STRIP_ON); 587 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 588 TX_VLAN_TAG_ON); 589 } else { 590 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 591 RX_VLAN_STRIP_OFF); 592 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 593 TX_VLAN_TAG_OFF); 594 } 595 } 596 597 static int 598 msk_init_rx_ring(struct msk_if_softc *sc_if) 599 { 600 struct msk_ring_data *rd; 601 struct msk_rxdesc *rxd; 602 int i, prod; 603 604 sc_if->msk_cdata.msk_rx_cons = 0; 605 sc_if->msk_cdata.msk_rx_prod = 0; 606 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 607 608 rd = &sc_if->msk_rdata; 609 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 610 prod = sc_if->msk_cdata.msk_rx_prod; 611 for (i = 0; i < MSK_RX_RING_CNT; i++) { 612 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 613 rxd->rx_m = NULL; 614 rxd->rx_le = &rd->msk_rx_ring[prod]; 615 if (msk_newbuf(sc_if, prod, 1) != 0) 616 return (ENOBUFS); 617 MSK_INC(prod, MSK_RX_RING_CNT); 618 } 619 620 /* Update prefetch unit. */ 621 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 622 CSR_WRITE_2(sc_if->msk_softc, 623 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 624 sc_if->msk_cdata.msk_rx_prod); 625 626 return (0); 627 } 628 629 #ifdef MSK_JUMBO 630 static int 631 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 632 { 633 struct msk_ring_data *rd; 634 struct msk_rxdesc *rxd; 635 int i, prod; 636 637 MSK_IF_LOCK_ASSERT(sc_if); 638 639 sc_if->msk_cdata.msk_rx_cons = 0; 640 sc_if->msk_cdata.msk_rx_prod = 0; 641 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 642 643 rd = &sc_if->msk_rdata; 644 bzero(rd->msk_jumbo_rx_ring, 645 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 646 prod = sc_if->msk_cdata.msk_rx_prod; 647 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 648 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 649 rxd->rx_m = NULL; 650 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 651 if (msk_jumbo_newbuf(sc_if, prod) != 0) 652 return (ENOBUFS); 653 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 654 } 655 656 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 657 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 659 660 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 661 CSR_WRITE_2(sc_if->msk_softc, 662 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 663 sc_if->msk_cdata.msk_rx_prod); 664 665 return (0); 666 } 667 #endif 668 669 static void 670 msk_init_tx_ring(struct msk_if_softc *sc_if) 671 { 672 struct msk_ring_data *rd; 673 struct msk_txdesc *txd; 674 int i; 675 676 sc_if->msk_cdata.msk_tx_prod = 0; 677 sc_if->msk_cdata.msk_tx_cons = 0; 678 sc_if->msk_cdata.msk_tx_cnt = 0; 679 680 rd = &sc_if->msk_rdata; 681 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 682 for (i = 0; i < MSK_TX_RING_CNT; i++) { 683 txd = &sc_if->msk_cdata.msk_txdesc[i]; 684 txd->tx_m = NULL; 685 txd->tx_le = &rd->msk_tx_ring[i]; 686 } 687 } 688 689 static __inline void 690 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 691 { 692 struct msk_rx_desc *rx_le; 693 struct msk_rxdesc *rxd; 694 struct mbuf *m; 695 696 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 697 m = rxd->rx_m; 698 rx_le = rxd->rx_le; 699 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 700 } 701 702 #ifdef MSK_JUMBO 703 static __inline void 704 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 705 { 706 struct msk_rx_desc *rx_le; 707 struct msk_rxdesc *rxd; 708 struct mbuf *m; 709 710 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 711 m = rxd->rx_m; 712 rx_le = rxd->rx_le; 713 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 714 } 715 #endif 716 717 static int 718 msk_newbuf(struct msk_if_softc *sc_if, int idx, int init) 719 { 720 struct msk_rx_desc *rx_le; 721 struct msk_rxdesc *rxd; 722 struct mbuf *m; 723 bus_dma_segment_t seg; 724 bus_dmamap_t map; 725 int error, nseg; 726 727 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 728 if (m == NULL) 729 return (ENOBUFS); 730 731 m->m_len = m->m_pkthdr.len = MCLBYTES; 732 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 733 m_adj(m, ETHER_ALIGN); 734 735 error = bus_dmamap_load_mbuf_segment(sc_if->msk_cdata.msk_rx_tag, 736 sc_if->msk_cdata.msk_rx_sparemap, 737 m, &seg, 1, &nseg, BUS_DMA_NOWAIT); 738 if (error) { 739 m_freem(m); 740 if (init) 741 if_printf(&sc_if->arpcom.ac_if, "can't load RX mbuf\n"); 742 return (error); 743 } 744 745 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 746 if (rxd->rx_m != NULL) { 747 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 748 BUS_DMASYNC_POSTREAD); 749 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 750 } 751 752 map = rxd->rx_dmamap; 753 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 754 sc_if->msk_cdata.msk_rx_sparemap = map; 755 756 rxd->rx_m = m; 757 rx_le = rxd->rx_le; 758 rx_le->msk_addr = htole32(MSK_ADDR_LO(seg.ds_addr)); 759 rx_le->msk_control = htole32(seg.ds_len | OP_PACKET | HW_OWNER); 760 761 return (0); 762 } 763 764 #ifdef MSK_JUMBO 765 static int 766 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 767 { 768 struct msk_rx_desc *rx_le; 769 struct msk_rxdesc *rxd; 770 struct mbuf *m; 771 bus_dma_segment_t segs[1]; 772 bus_dmamap_t map; 773 int nsegs; 774 void *buf; 775 776 MGETHDR(m, MB_DONTWAIT, MT_DATA); 777 if (m == NULL) 778 return (ENOBUFS); 779 buf = msk_jalloc(sc_if); 780 if (buf == NULL) { 781 m_freem(m); 782 return (ENOBUFS); 783 } 784 /* Attach the buffer to the mbuf. */ 785 MEXTADD(m, buf, MSK_JLEN, msk_jfree, sc_if, 0, EXT_NET_DRV); 786 if ((m->m_flags & M_EXT) == 0) { 787 m_freem(m); 788 return (ENOBUFS); 789 } 790 m->m_pkthdr.len = m->m_len = MSK_JLEN; 791 m_adj(m, ETHER_ALIGN); 792 793 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 794 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 795 BUS_DMA_NOWAIT) != 0) { 796 m_freem(m); 797 return (ENOBUFS); 798 } 799 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 800 801 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 802 if (rxd->rx_m != NULL) { 803 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 804 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 805 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 806 rxd->rx_dmamap); 807 } 808 map = rxd->rx_dmamap; 809 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 810 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 811 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 812 BUS_DMASYNC_PREREAD); 813 rxd->rx_m = m; 814 rx_le = rxd->rx_le; 815 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 816 rx_le->msk_control = 817 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 818 819 return (0); 820 } 821 #endif 822 823 /* 824 * Set media options. 825 */ 826 static int 827 msk_mediachange(struct ifnet *ifp) 828 { 829 struct msk_if_softc *sc_if = ifp->if_softc; 830 struct mii_data *mii; 831 int error; 832 833 mii = device_get_softc(sc_if->msk_miibus); 834 error = mii_mediachg(mii); 835 836 return (error); 837 } 838 839 /* 840 * Report current media status. 841 */ 842 static void 843 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 844 { 845 struct msk_if_softc *sc_if = ifp->if_softc; 846 struct mii_data *mii; 847 848 mii = device_get_softc(sc_if->msk_miibus); 849 mii_pollstat(mii); 850 851 ifmr->ifm_active = mii->mii_media_active; 852 ifmr->ifm_status = mii->mii_media_status; 853 } 854 855 static int 856 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 857 { 858 struct msk_if_softc *sc_if; 859 struct ifreq *ifr; 860 struct mii_data *mii; 861 int error, mask; 862 863 sc_if = ifp->if_softc; 864 ifr = (struct ifreq *)data; 865 error = 0; 866 867 switch(command) { 868 case SIOCSIFMTU: 869 #ifdef MSK_JUMBO 870 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 871 error = EINVAL; 872 break; 873 } 874 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 875 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 876 error = EINVAL; 877 break; 878 } 879 ifp->if_mtu = ifr->ifr_mtu; 880 if ((ifp->if_flags & IFF_RUNNING) != 0) 881 msk_init(sc_if); 882 #else 883 error = EOPNOTSUPP; 884 #endif 885 break; 886 887 case SIOCSIFFLAGS: 888 if (ifp->if_flags & IFF_UP) { 889 if (ifp->if_flags & IFF_RUNNING) { 890 if (((ifp->if_flags ^ sc_if->msk_if_flags) 891 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 892 msk_rxfilter(sc_if); 893 } else { 894 if (sc_if->msk_detach == 0) 895 msk_init(sc_if); 896 } 897 } else { 898 if (ifp->if_flags & IFF_RUNNING) 899 msk_stop(sc_if); 900 } 901 sc_if->msk_if_flags = ifp->if_flags; 902 break; 903 904 case SIOCADDMULTI: 905 case SIOCDELMULTI: 906 if (ifp->if_flags & IFF_RUNNING) 907 msk_rxfilter(sc_if); 908 break; 909 910 case SIOCGIFMEDIA: 911 case SIOCSIFMEDIA: 912 mii = device_get_softc(sc_if->msk_miibus); 913 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 914 break; 915 916 case SIOCSIFCAP: 917 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 918 if ((mask & IFCAP_TXCSUM) != 0) { 919 ifp->if_capenable ^= IFCAP_TXCSUM; 920 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 921 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 922 ifp->if_hwassist |= MSK_CSUM_FEATURES; 923 else 924 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 925 } 926 #ifdef notyet 927 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 928 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 929 msk_setvlan(sc_if, ifp); 930 } 931 #endif 932 933 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 934 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 935 /* 936 * In Yukon EC Ultra, TSO & checksum offload is not 937 * supported for jumbo frame. 938 */ 939 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 940 ifp->if_capenable &= ~IFCAP_TXCSUM; 941 } 942 break; 943 944 default: 945 error = ether_ioctl(ifp, command, data); 946 break; 947 } 948 949 return (error); 950 } 951 952 static int 953 mskc_probe(device_t dev) 954 { 955 const struct msk_product *mp; 956 uint16_t vendor, devid; 957 958 vendor = pci_get_vendor(dev); 959 devid = pci_get_device(dev); 960 for (mp = msk_products; mp->msk_name != NULL; ++mp) { 961 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 962 device_set_desc(dev, mp->msk_name); 963 return (0); 964 } 965 } 966 return (ENXIO); 967 } 968 969 static int 970 mskc_setup_rambuffer(struct msk_softc *sc) 971 { 972 int next; 973 int i; 974 975 /* Get adapter SRAM size. */ 976 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 977 if (bootverbose) { 978 device_printf(sc->msk_dev, 979 "RAM buffer size : %dKB\n", sc->msk_ramsize); 980 } 981 if (sc->msk_ramsize == 0) 982 return (0); 983 sc->msk_pflags |= MSK_FLAG_RAMBUF; 984 985 /* 986 * Give receiver 2/3 of memory and round down to the multiple 987 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 988 * of 1024. 989 */ 990 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 991 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 992 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 993 sc->msk_rxqstart[i] = next; 994 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 995 next = sc->msk_rxqend[i] + 1; 996 sc->msk_txqstart[i] = next; 997 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 998 next = sc->msk_txqend[i] + 1; 999 if (bootverbose) { 1000 device_printf(sc->msk_dev, 1001 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1002 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1003 sc->msk_rxqend[i]); 1004 device_printf(sc->msk_dev, 1005 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1006 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1007 sc->msk_txqend[i]); 1008 } 1009 } 1010 1011 return (0); 1012 } 1013 1014 static void 1015 mskc_phy_power(struct msk_softc *sc, int mode) 1016 { 1017 uint32_t our, val; 1018 int i; 1019 1020 switch (mode) { 1021 case MSK_PHY_POWERUP: 1022 /* Switch power to VCC (WA for VAUX problem). */ 1023 CSR_WRITE_1(sc, B0_POWER_CTRL, 1024 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1025 /* Disable Core Clock Division, set Clock Select to 0. */ 1026 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1027 1028 val = 0; 1029 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1030 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1031 /* Enable bits are inverted. */ 1032 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1033 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1034 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1035 } 1036 /* 1037 * Enable PCI & Core Clock, enable clock gating for both Links. 1038 */ 1039 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1040 1041 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1042 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1043 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1044 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1045 /* Deassert Low Power for 1st PHY. */ 1046 our |= PCI_Y2_PHY1_COMA; 1047 if (sc->msk_num_port > 1) 1048 our |= PCI_Y2_PHY2_COMA; 1049 } 1050 } 1051 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1052 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1053 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1054 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1055 val &= (PCI_FORCE_ASPM_REQUEST | 1056 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1057 PCI_ASPM_CLKRUN_REQUEST); 1058 /* Set all bits to 0 except bits 15..12. */ 1059 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1060 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1061 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1062 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1063 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1064 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1065 /* 1066 * Disable status race, workaround for 1067 * Yukon EC Ultra & Yukon EX. 1068 */ 1069 val = CSR_READ_4(sc, B2_GP_IO); 1070 val |= GLB_GPIO_STAT_RACE_DIS; 1071 CSR_WRITE_4(sc, B2_GP_IO, val); 1072 CSR_READ_4(sc, B2_GP_IO); 1073 } 1074 /* Release PHY from PowerDown/COMA mode. */ 1075 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1076 1077 for (i = 0; i < sc->msk_num_port; i++) { 1078 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1079 GMLC_RST_SET); 1080 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1081 GMLC_RST_CLR); 1082 } 1083 break; 1084 case MSK_PHY_POWERDOWN: 1085 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1086 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1087 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1088 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1089 val &= ~PCI_Y2_PHY1_COMA; 1090 if (sc->msk_num_port > 1) 1091 val &= ~PCI_Y2_PHY2_COMA; 1092 } 1093 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1094 1095 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1096 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1097 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1098 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1099 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1100 /* Enable bits are inverted. */ 1101 val = 0; 1102 } 1103 /* 1104 * Disable PCI & Core Clock, disable clock gating for 1105 * both Links. 1106 */ 1107 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1108 CSR_WRITE_1(sc, B0_POWER_CTRL, 1109 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1110 break; 1111 default: 1112 break; 1113 } 1114 } 1115 1116 static void 1117 mskc_reset(struct msk_softc *sc) 1118 { 1119 bus_addr_t addr; 1120 uint16_t status; 1121 uint32_t val; 1122 int i; 1123 1124 /* Disable ASF. */ 1125 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1126 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1127 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1128 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1129 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1130 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1131 /* Clear AHB bridge & microcontroller reset. */ 1132 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1133 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1134 /* Clear ASF microcontroller state. */ 1135 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1136 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1137 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1138 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1139 } else { 1140 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1141 } 1142 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1143 /* 1144 * Since we disabled ASF, S/W reset is required for 1145 * Power Management. 1146 */ 1147 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1148 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1149 } 1150 1151 /* Clear all error bits in the PCI status register. */ 1152 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1153 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1154 1155 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1156 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1157 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1158 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1159 1160 switch (sc->msk_bustype) { 1161 case MSK_PEX_BUS: 1162 /* Clear all PEX errors. */ 1163 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1164 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1165 if ((val & PEX_RX_OV) != 0) { 1166 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1167 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1168 } 1169 break; 1170 case MSK_PCI_BUS: 1171 case MSK_PCIX_BUS: 1172 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1173 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1174 if (val == 0) 1175 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1176 if (sc->msk_bustype == MSK_PCIX_BUS) { 1177 /* Set Cache Line Size opt. */ 1178 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1179 val |= PCI_CLS_OPT; 1180 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1181 } 1182 break; 1183 } 1184 /* Set PHY power state. */ 1185 mskc_phy_power(sc, MSK_PHY_POWERUP); 1186 1187 /* Reset GPHY/GMAC Control */ 1188 for (i = 0; i < sc->msk_num_port; i++) { 1189 /* GPHY Control reset. */ 1190 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1191 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1192 /* GMAC Control reset. */ 1193 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1194 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1195 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1196 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1197 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1198 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1199 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1200 GMC_BYP_RETR_ON); 1201 } 1202 } 1203 1204 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1205 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1206 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1207 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1208 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1209 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1210 } 1211 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1212 1213 /* LED On. */ 1214 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1215 1216 /* Clear TWSI IRQ. */ 1217 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1218 1219 /* Turn off hardware timer. */ 1220 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1221 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1222 1223 /* Turn off descriptor polling. */ 1224 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1225 1226 /* Turn off time stamps. */ 1227 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1228 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1229 1230 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1231 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1232 sc->msk_hw_id == CHIP_ID_YUKON_FE) { 1233 /* Configure timeout values. */ 1234 for (i = 0; i < sc->msk_num_port; i++) { 1235 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), 1236 RI_RST_SET); 1237 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), 1238 RI_RST_CLR); 1239 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1240 MSK_RI_TO_53); 1241 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1242 MSK_RI_TO_53); 1243 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1244 MSK_RI_TO_53); 1245 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1246 MSK_RI_TO_53); 1247 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1248 MSK_RI_TO_53); 1249 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1250 MSK_RI_TO_53); 1251 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1252 MSK_RI_TO_53); 1253 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1254 MSK_RI_TO_53); 1255 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1256 MSK_RI_TO_53); 1257 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1258 MSK_RI_TO_53); 1259 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1260 MSK_RI_TO_53); 1261 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1262 MSK_RI_TO_53); 1263 } 1264 } 1265 1266 /* Disable all interrupts. */ 1267 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1268 CSR_READ_4(sc, B0_HWE_IMSK); 1269 CSR_WRITE_4(sc, B0_IMSK, 0); 1270 CSR_READ_4(sc, B0_IMSK); 1271 1272 /* 1273 * On dual port PCI-X card, there is an problem where status 1274 * can be received out of order due to split transactions. 1275 */ 1276 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1277 uint16_t pcix_cmd; 1278 1279 pcix_cmd = pci_read_config(sc->msk_dev, 1280 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1281 /* Clear Max Outstanding Split Transactions. */ 1282 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1283 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1284 pci_write_config(sc->msk_dev, 1285 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1286 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1287 } 1288 if (sc->msk_pciecap != 0) { 1289 /* Change Max. Read Request Size to 2048 bytes. */ 1290 if (pcie_get_max_readrq(sc->msk_dev) == 1291 PCIEM_DEVCTL_MAX_READRQ_512) { 1292 pcie_set_max_readrq(sc->msk_dev, 1293 PCIEM_DEVCTL_MAX_READRQ_2048); 1294 } 1295 } 1296 1297 /* Clear status list. */ 1298 bzero(sc->msk_stat_ring, 1299 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1300 sc->msk_stat_cons = 0; 1301 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1302 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1303 /* Set the status list base address. */ 1304 addr = sc->msk_stat_ring_paddr; 1305 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1306 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1307 /* Set the status list last index. */ 1308 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1309 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1310 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1311 /* WA for dev. #4.3 */ 1312 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1313 /* WA for dev. #4.18 */ 1314 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1315 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1316 } else { 1317 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1318 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1319 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1320 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1321 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1322 else 1323 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1324 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1325 } 1326 /* 1327 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1328 */ 1329 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1330 1331 /* Enable status unit. */ 1332 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1333 1334 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1335 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1336 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1337 } 1338 1339 static int 1340 msk_probe(device_t dev) 1341 { 1342 struct msk_softc *sc = device_get_softc(device_get_parent(dev)); 1343 char desc[100]; 1344 1345 /* 1346 * Not much to do here. We always know there will be 1347 * at least one GMAC present, and if there are two, 1348 * mskc_attach() will create a second device instance 1349 * for us. 1350 */ 1351 ksnprintf(desc, sizeof(desc), 1352 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1353 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1354 sc->msk_hw_rev); 1355 device_set_desc_copy(dev, desc); 1356 1357 return (0); 1358 } 1359 1360 static int 1361 msk_attach(device_t dev) 1362 { 1363 struct msk_softc *sc = device_get_softc(device_get_parent(dev)); 1364 struct msk_if_softc *sc_if = device_get_softc(dev); 1365 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1366 int i, port, error; 1367 uint8_t eaddr[ETHER_ADDR_LEN]; 1368 1369 port = *(int *)device_get_ivars(dev); 1370 KKASSERT(port == MSK_PORT_A || port == MSK_PORT_B); 1371 1372 kfree(device_get_ivars(dev), M_DEVBUF); 1373 device_set_ivars(dev, NULL); 1374 1375 callout_init(&sc_if->msk_tick_ch); 1376 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1377 1378 sc_if->msk_if_dev = dev; 1379 sc_if->msk_port = port; 1380 sc_if->msk_softc = sc; 1381 sc_if->msk_ifp = ifp; 1382 sc_if->msk_flags = sc->msk_pflags; 1383 sc->msk_if[port] = sc_if; 1384 1385 /* Setup Tx/Rx queue register offsets. */ 1386 if (port == MSK_PORT_A) { 1387 sc_if->msk_txq = Q_XA1; 1388 sc_if->msk_txsq = Q_XS1; 1389 sc_if->msk_rxq = Q_R1; 1390 } else { 1391 sc_if->msk_txq = Q_XA2; 1392 sc_if->msk_txsq = Q_XS2; 1393 sc_if->msk_rxq = Q_R2; 1394 } 1395 1396 error = msk_txrx_dma_alloc(sc_if); 1397 if (error) 1398 goto fail; 1399 1400 ifp->if_softc = sc_if; 1401 ifp->if_mtu = ETHERMTU; 1402 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1403 ifp->if_init = msk_init; 1404 ifp->if_ioctl = msk_ioctl; 1405 ifp->if_start = msk_start; 1406 ifp->if_watchdog = msk_watchdog; 1407 ifq_set_maxlen(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1408 ifq_set_ready(&ifp->if_snd); 1409 1410 #ifdef notyet 1411 /* 1412 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1413 * has serious bug in Rx checksum offload for all Yukon II family 1414 * hardware. It seems there is a workaround to make it work somtimes. 1415 * However, the workaround also have to check OP code sequences to 1416 * verify whether the OP code is correct. Sometimes it should compute 1417 * IP/TCP/UDP checksum in driver in order to verify correctness of 1418 * checksum computed by hardware. If you have to compute checksum 1419 * with software to verify the hardware's checksum why have hardware 1420 * compute the checksum? I think there is no reason to spend time to 1421 * make Rx checksum offload work on Yukon II hardware. 1422 */ 1423 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU | 1424 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1425 ifp->if_hwassist = MSK_CSUM_FEATURES; 1426 ifp->if_capenable = ifp->if_capabilities; 1427 #endif 1428 1429 /* 1430 * Get station address for this interface. Note that 1431 * dual port cards actually come with three station 1432 * addresses: one for each port, plus an extra. The 1433 * extra one is used by the SysKonnect driver software 1434 * as a 'virtual' station address for when both ports 1435 * are operating in failover mode. Currently we don't 1436 * use this extra address. 1437 */ 1438 for (i = 0; i < ETHER_ADDR_LEN; i++) 1439 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1440 1441 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN; 1442 1443 /* 1444 * Do miibus setup. 1445 */ 1446 error = mii_phy_probe(dev, &sc_if->msk_miibus, 1447 msk_mediachange, msk_mediastatus); 1448 if (error) { 1449 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1450 goto fail; 1451 } 1452 1453 /* 1454 * Call MI attach routine. Can't hold locks when calling into ether_*. 1455 */ 1456 ether_ifattach(ifp, eaddr, &sc->msk_serializer); 1457 #if 0 1458 /* 1459 * Tell the upper layer(s) we support long frames. 1460 * Must appear after the call to ether_ifattach() because 1461 * ether_ifattach() sets ifi_hdrlen to the default value. 1462 */ 1463 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1464 #endif 1465 1466 return 0; 1467 fail: 1468 msk_detach(dev); 1469 sc->msk_if[port] = NULL; 1470 return (error); 1471 } 1472 1473 /* 1474 * Attach the interface. Allocate softc structures, do ifmedia 1475 * setup and ethernet/BPF attach. 1476 */ 1477 static int 1478 mskc_attach(device_t dev) 1479 { 1480 struct msk_softc *sc; 1481 int error, *port, cpuid; 1482 1483 sc = device_get_softc(dev); 1484 sc->msk_dev = dev; 1485 lwkt_serialize_init(&sc->msk_serializer); 1486 1487 /* 1488 * Initailize sysctl variables 1489 */ 1490 sc->msk_process_limit = mskc_process_limit; 1491 sc->msk_intr_rate = mskc_intr_rate; 1492 1493 #ifndef BURN_BRIDGES 1494 /* 1495 * Handle power management nonsense. 1496 */ 1497 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1498 uint32_t irq, bar0, bar1; 1499 1500 /* Save important PCI config data. */ 1501 bar0 = pci_read_config(dev, PCIR_BAR(0), 4); 1502 bar1 = pci_read_config(dev, PCIR_BAR(1), 4); 1503 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1504 1505 /* Reset the power state. */ 1506 device_printf(dev, "chip is in D%d power mode " 1507 "-- setting to D0\n", pci_get_powerstate(dev)); 1508 1509 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1510 1511 /* Restore PCI config data. */ 1512 pci_write_config(dev, PCIR_BAR(0), bar0, 4); 1513 pci_write_config(dev, PCIR_BAR(1), bar1, 4); 1514 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1515 } 1516 #endif /* BURN_BRIDGES */ 1517 1518 /* 1519 * Map control/status registers. 1520 */ 1521 pci_enable_busmaster(dev); 1522 1523 /* 1524 * Allocate I/O resource 1525 */ 1526 #ifdef MSK_USEIOSPACE 1527 sc->msk_res_type = SYS_RES_IOPORT; 1528 sc->msk_res_rid = PCIR_BAR(1); 1529 #else 1530 sc->msk_res_type = SYS_RES_MEMORY; 1531 sc->msk_res_rid = PCIR_BAR(0); 1532 #endif 1533 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type, 1534 &sc->msk_res_rid, RF_ACTIVE); 1535 if (sc->msk_res == NULL) { 1536 if (sc->msk_res_type == SYS_RES_MEMORY) { 1537 sc->msk_res_type = SYS_RES_IOPORT; 1538 sc->msk_res_rid = PCIR_BAR(1); 1539 } else { 1540 sc->msk_res_type = SYS_RES_MEMORY; 1541 sc->msk_res_rid = PCIR_BAR(0); 1542 } 1543 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type, 1544 &sc->msk_res_rid, 1545 RF_ACTIVE); 1546 if (sc->msk_res == NULL) { 1547 device_printf(dev, "couldn't allocate %s resources\n", 1548 sc->msk_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 1549 return (ENXIO); 1550 } 1551 } 1552 sc->msk_res_bt = rman_get_bustag(sc->msk_res); 1553 sc->msk_res_bh = rman_get_bushandle(sc->msk_res); 1554 1555 /* 1556 * Allocate IRQ 1557 */ 1558 sc->msk_irq_rid = 0; 1559 sc->msk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1560 &sc->msk_irq_rid, 1561 RF_SHAREABLE | RF_ACTIVE); 1562 if (sc->msk_irq == NULL) { 1563 device_printf(dev, "couldn't allocate IRQ resources\n"); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 /* Enable all clocks before accessing any registers. */ 1569 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1570 1571 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1572 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1573 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1574 /* Bail out if chip is not recognized. */ 1575 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1576 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1577 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1578 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1579 sc->msk_hw_id, sc->msk_hw_rev); 1580 error = ENXIO; 1581 goto fail; 1582 } 1583 1584 /* 1585 * Create sysctl tree 1586 */ 1587 sysctl_ctx_init(&sc->msk_sysctl_ctx); 1588 sc->msk_sysctl_tree = SYSCTL_ADD_NODE(&sc->msk_sysctl_ctx, 1589 SYSCTL_STATIC_CHILDREN(_hw), 1590 OID_AUTO, 1591 device_get_nameunit(dev), 1592 CTLFLAG_RD, 0, ""); 1593 if (sc->msk_sysctl_tree == NULL) { 1594 device_printf(dev, "can't add sysctl node\n"); 1595 error = ENXIO; 1596 goto fail; 1597 } 1598 1599 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx, 1600 SYSCTL_CHILDREN(sc->msk_sysctl_tree), 1601 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1602 &sc->msk_process_limit, 0, mskc_sysctl_proc_limit, 1603 "I", "max number of Rx events to process"); 1604 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx, 1605 SYSCTL_CHILDREN(sc->msk_sysctl_tree), 1606 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW, 1607 sc, 0, mskc_sysctl_intr_rate, 1608 "I", "max number of interrupt per second"); 1609 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1610 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1611 "defrag_avoided", CTLFLAG_RW, &sc->msk_defrag_avoided, 1612 0, "# of avoided m_defrag on TX path"); 1613 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1614 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1615 "leading_copied", CTLFLAG_RW, &sc->msk_leading_copied, 1616 0, "# of leading copies on TX path"); 1617 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1618 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1619 "trailing_copied", CTLFLAG_RW, &sc->msk_trailing_copied, 1620 0, "# of trailing copies on TX path"); 1621 1622 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1623 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1624 sc->msk_coppertype = 0; 1625 else 1626 sc->msk_coppertype = 1; 1627 /* Check number of MACs. */ 1628 sc->msk_num_port = 1; 1629 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1630 CFG_DUAL_MAC_MSK) { 1631 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1632 sc->msk_num_port++; 1633 } 1634 1635 /* Check bus type. */ 1636 if (pci_is_pcie(sc->msk_dev) == 0) { 1637 sc->msk_bustype = MSK_PEX_BUS; 1638 sc->msk_pciecap = pci_get_pciecap_ptr(sc->msk_dev); 1639 } else if (pci_is_pcix(sc->msk_dev) == 0) { 1640 sc->msk_bustype = MSK_PCIX_BUS; 1641 sc->msk_pcixcap = pci_get_pcixcap_ptr(sc->msk_dev); 1642 } else { 1643 sc->msk_bustype = MSK_PCI_BUS; 1644 } 1645 1646 switch (sc->msk_hw_id) { 1647 case CHIP_ID_YUKON_EC: 1648 case CHIP_ID_YUKON_EC_U: 1649 sc->msk_clock = 125; /* 125 Mhz */ 1650 break; 1651 case CHIP_ID_YUKON_EX: 1652 sc->msk_clock = 125; /* 125 Mhz */ 1653 break; 1654 case CHIP_ID_YUKON_FE: 1655 sc->msk_clock = 100; /* 100 Mhz */ 1656 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1657 break; 1658 case CHIP_ID_YUKON_FE_P: 1659 sc->msk_clock = 50; /* 50 Mhz */ 1660 /* DESCV2 */ 1661 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1662 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1663 /* 1664 * XXX 1665 * FE+ A0 has status LE writeback bug so msk(4) 1666 * does not rely on status word of received frame 1667 * in msk_rxeof() which in turn disables all 1668 * hardware assistance bits reported by the status 1669 * word as well as validity of the recevied frame. 1670 * Just pass received frames to upper stack with 1671 * minimal test and let upper stack handle them. 1672 */ 1673 sc->msk_pflags |= MSK_FLAG_NORXCHK; 1674 } 1675 break; 1676 case CHIP_ID_YUKON_XL: 1677 sc->msk_clock = 156; /* 156 Mhz */ 1678 break; 1679 case CHIP_ID_YUKON_SUPR: 1680 sc->msk_clock = 125; /* 125 MHz */ 1681 break; 1682 case CHIP_ID_YUKON_UL_2: 1683 sc->msk_clock = 125; /* 125 Mhz */ 1684 break; 1685 case CHIP_ID_YUKON_OPT: 1686 sc->msk_clock = 125; /* 125 MHz */ 1687 break; 1688 default: 1689 sc->msk_clock = 156; /* 156 Mhz */ 1690 break; 1691 } 1692 1693 error = mskc_status_dma_alloc(sc); 1694 if (error) 1695 goto fail; 1696 1697 /* Set base interrupt mask. */ 1698 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1699 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1700 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1701 1702 /* Reset the adapter. */ 1703 mskc_reset(sc); 1704 1705 error = mskc_setup_rambuffer(sc); 1706 if (error) 1707 goto fail; 1708 1709 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1710 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1711 device_printf(dev, "failed to add child for PORT_A\n"); 1712 error = ENXIO; 1713 goto fail; 1714 } 1715 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1716 *port = MSK_PORT_A; 1717 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1718 1719 if (sc->msk_num_port > 1) { 1720 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1721 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1722 device_printf(dev, "failed to add child for PORT_B\n"); 1723 error = ENXIO; 1724 goto fail; 1725 } 1726 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1727 *port = MSK_PORT_B; 1728 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1729 } 1730 1731 bus_generic_attach(dev); 1732 1733 error = bus_setup_intr(dev, sc->msk_irq, INTR_MPSAFE, 1734 mskc_intr, sc, &sc->msk_intrhand, 1735 &sc->msk_serializer); 1736 if (error) { 1737 device_printf(dev, "couldn't set up interrupt handler\n"); 1738 goto fail; 1739 } 1740 1741 cpuid = rman_get_cpuid(sc->msk_irq); 1742 KKASSERT(cpuid >= 0 && cpuid < ncpus); 1743 1744 if (sc->msk_if[0] != NULL) 1745 sc->msk_if[0]->msk_ifp->if_cpuid = cpuid; 1746 if (sc->msk_if[1] != NULL) 1747 sc->msk_if[1]->msk_ifp->if_cpuid = cpuid; 1748 return 0; 1749 fail: 1750 mskc_detach(dev); 1751 return (error); 1752 } 1753 1754 /* 1755 * Shutdown hardware and free up resources. This can be called any 1756 * time after the mutex has been initialized. It is called in both 1757 * the error case in attach and the normal detach case so it needs 1758 * to be careful about only freeing resources that have actually been 1759 * allocated. 1760 */ 1761 static int 1762 msk_detach(device_t dev) 1763 { 1764 struct msk_if_softc *sc_if = device_get_softc(dev); 1765 1766 if (device_is_attached(dev)) { 1767 struct msk_softc *sc = sc_if->msk_softc; 1768 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1769 1770 lwkt_serialize_enter(ifp->if_serializer); 1771 1772 if (sc->msk_intrhand != NULL) { 1773 if (sc->msk_if[MSK_PORT_A] != NULL) 1774 msk_stop(sc->msk_if[MSK_PORT_A]); 1775 if (sc->msk_if[MSK_PORT_B] != NULL) 1776 msk_stop(sc->msk_if[MSK_PORT_B]); 1777 1778 bus_teardown_intr(sc->msk_dev, sc->msk_irq, 1779 sc->msk_intrhand); 1780 sc->msk_intrhand = NULL; 1781 } 1782 1783 lwkt_serialize_exit(ifp->if_serializer); 1784 1785 ether_ifdetach(ifp); 1786 } 1787 1788 if (sc_if->msk_miibus != NULL) 1789 device_delete_child(dev, sc_if->msk_miibus); 1790 1791 msk_txrx_dma_free(sc_if); 1792 return (0); 1793 } 1794 1795 static int 1796 mskc_detach(device_t dev) 1797 { 1798 struct msk_softc *sc = device_get_softc(dev); 1799 int *port, i; 1800 1801 #ifdef INVARIANTS 1802 if (device_is_attached(dev)) { 1803 KASSERT(sc->msk_intrhand == NULL, 1804 ("intr is not torn down yet")); 1805 } 1806 #endif 1807 1808 for (i = 0; i < sc->msk_num_port; ++i) { 1809 if (sc->msk_devs[i] != NULL) { 1810 port = device_get_ivars(sc->msk_devs[i]); 1811 if (port != NULL) { 1812 kfree(port, M_DEVBUF); 1813 device_set_ivars(sc->msk_devs[i], NULL); 1814 } 1815 device_delete_child(dev, sc->msk_devs[i]); 1816 } 1817 } 1818 1819 /* Disable all interrupts. */ 1820 CSR_WRITE_4(sc, B0_IMSK, 0); 1821 CSR_READ_4(sc, B0_IMSK); 1822 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1823 CSR_READ_4(sc, B0_HWE_IMSK); 1824 1825 /* LED Off. */ 1826 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1827 1828 /* Put hardware reset. */ 1829 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1830 1831 mskc_status_dma_free(sc); 1832 1833 if (sc->msk_irq != NULL) { 1834 bus_release_resource(dev, SYS_RES_IRQ, sc->msk_irq_rid, 1835 sc->msk_irq); 1836 } 1837 if (sc->msk_res != NULL) { 1838 bus_release_resource(dev, sc->msk_res_type, sc->msk_res_rid, 1839 sc->msk_res); 1840 } 1841 1842 if (sc->msk_sysctl_tree != NULL) 1843 sysctl_ctx_free(&sc->msk_sysctl_ctx); 1844 1845 return (0); 1846 } 1847 1848 /* Create status DMA region. */ 1849 static int 1850 mskc_status_dma_alloc(struct msk_softc *sc) 1851 { 1852 bus_dmamem_t dmem; 1853 int error; 1854 1855 error = bus_dmamem_coherent(NULL/* XXX parent */, MSK_STAT_ALIGN, 0, 1856 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1857 MSK_STAT_RING_SZ, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1858 if (error) { 1859 device_printf(sc->msk_dev, 1860 "failed to create status coherent DMA memory\n"); 1861 return error; 1862 } 1863 sc->msk_stat_tag = dmem.dmem_tag; 1864 sc->msk_stat_map = dmem.dmem_map; 1865 sc->msk_stat_ring = dmem.dmem_addr; 1866 sc->msk_stat_ring_paddr = dmem.dmem_busaddr; 1867 1868 return (0); 1869 } 1870 1871 static void 1872 mskc_status_dma_free(struct msk_softc *sc) 1873 { 1874 /* Destroy status block. */ 1875 if (sc->msk_stat_tag) { 1876 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1877 bus_dmamem_free(sc->msk_stat_tag, sc->msk_stat_ring, 1878 sc->msk_stat_map); 1879 bus_dma_tag_destroy(sc->msk_stat_tag); 1880 sc->msk_stat_tag = NULL; 1881 } 1882 } 1883 1884 static int 1885 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1886 { 1887 int error, i, j; 1888 #ifdef MSK_JUMBO 1889 struct msk_rxdesc *jrxd; 1890 struct msk_jpool_entry *entry; 1891 uint8_t *ptr; 1892 #endif 1893 bus_size_t rxalign; 1894 1895 /* Create parent DMA tag. */ 1896 /* 1897 * XXX 1898 * It seems that Yukon II supports full 64bits DMA operations. But 1899 * it needs two descriptors(list elements) for 64bits DMA operations. 1900 * Since we don't know what DMA address mappings(32bits or 64bits) 1901 * would be used in advance for each mbufs, we limits its DMA space 1902 * to be in range of 32bits address space. Otherwise, we should check 1903 * what DMA address is used and chain another descriptor for the 1904 * 64bits DMA operation. This also means descriptor ring size is 1905 * variable. Limiting DMA address to be in 32bit address space greatly 1906 * simplyfies descriptor handling and possibly would increase 1907 * performance a bit due to efficient handling of descriptors. 1908 * Apart from harassing checksum offloading mechanisms, it seems 1909 * it's really bad idea to use a seperate descriptor for 64bit 1910 * DMA operation to save small descriptor memory. Anyway, I've 1911 * never seen these exotic scheme on ethernet interface hardware. 1912 */ 1913 error = bus_dma_tag_create( 1914 NULL, /* parent */ 1915 1, 0, /* alignment, boundary */ 1916 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1917 BUS_SPACE_MAXADDR, /* highaddr */ 1918 NULL, NULL, /* filter, filterarg */ 1919 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1920 0, /* nsegments */ 1921 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1922 0, /* flags */ 1923 &sc_if->msk_cdata.msk_parent_tag); 1924 if (error) { 1925 device_printf(sc_if->msk_if_dev, 1926 "failed to create parent DMA tag\n"); 1927 return error; 1928 } 1929 1930 /* Create DMA stuffs for Tx ring. */ 1931 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_TX_RING_SZ, 1932 &sc_if->msk_cdata.msk_tx_ring_tag, 1933 (void *)&sc_if->msk_rdata.msk_tx_ring, 1934 &sc_if->msk_rdata.msk_tx_ring_paddr, 1935 &sc_if->msk_cdata.msk_tx_ring_map); 1936 if (error) { 1937 device_printf(sc_if->msk_if_dev, 1938 "failed to create TX ring DMA stuffs\n"); 1939 return error; 1940 } 1941 1942 /* Create DMA stuffs for Rx ring. */ 1943 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_RX_RING_SZ, 1944 &sc_if->msk_cdata.msk_rx_ring_tag, 1945 (void *)&sc_if->msk_rdata.msk_rx_ring, 1946 &sc_if->msk_rdata.msk_rx_ring_paddr, 1947 &sc_if->msk_cdata.msk_rx_ring_map); 1948 if (error) { 1949 device_printf(sc_if->msk_if_dev, 1950 "failed to create RX ring DMA stuffs\n"); 1951 return error; 1952 } 1953 1954 /* Create tag for Tx buffers. */ 1955 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 1956 1, 0, /* alignment, boundary */ 1957 BUS_SPACE_MAXADDR, /* lowaddr */ 1958 BUS_SPACE_MAXADDR, /* highaddr */ 1959 NULL, NULL, /* filter, filterarg */ 1960 MSK_JUMBO_FRAMELEN, /* maxsize */ 1961 MSK_MAXTXSEGS, /* nsegments */ 1962 MSK_MAXSGSIZE, /* maxsegsize */ 1963 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 1964 BUS_DMA_ONEBPAGE, /* flags */ 1965 &sc_if->msk_cdata.msk_tx_tag); 1966 if (error) { 1967 device_printf(sc_if->msk_if_dev, 1968 "failed to create Tx DMA tag\n"); 1969 return error; 1970 } 1971 1972 /* Create DMA maps for Tx buffers. */ 1973 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1974 struct msk_txdesc *txd = &sc_if->msk_cdata.msk_txdesc[i]; 1975 1976 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 1977 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1978 &txd->tx_dmamap); 1979 if (error) { 1980 device_printf(sc_if->msk_if_dev, 1981 "failed to create %dth Tx dmamap\n", i); 1982 1983 for (j = 0; j < i; ++j) { 1984 txd = &sc_if->msk_cdata.msk_txdesc[j]; 1985 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 1986 txd->tx_dmamap); 1987 } 1988 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 1989 sc_if->msk_cdata.msk_tx_tag = NULL; 1990 1991 return error; 1992 } 1993 } 1994 1995 /* 1996 * Workaround hardware hang which seems to happen when Rx buffer 1997 * is not aligned on multiple of FIFO word(8 bytes). 1998 */ 1999 if (sc_if->msk_flags & MSK_FLAG_RAMBUF) 2000 rxalign = MSK_RX_BUF_ALIGN; 2001 else 2002 rxalign = 1; 2003 2004 /* Create tag for Rx buffers. */ 2005 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2006 rxalign, 0, /* alignment, boundary */ 2007 BUS_SPACE_MAXADDR, /* lowaddr */ 2008 BUS_SPACE_MAXADDR, /* highaddr */ 2009 NULL, NULL, /* filter, filterarg */ 2010 MCLBYTES, /* maxsize */ 2011 1, /* nsegments */ 2012 MCLBYTES, /* maxsegsize */ 2013 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED | 2014 BUS_DMA_WAITOK, /* flags */ 2015 &sc_if->msk_cdata.msk_rx_tag); 2016 if (error) { 2017 device_printf(sc_if->msk_if_dev, 2018 "failed to create Rx DMA tag\n"); 2019 return error; 2020 } 2021 2022 /* Create DMA maps for Rx buffers. */ 2023 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, BUS_DMA_WAITOK, 2024 &sc_if->msk_cdata.msk_rx_sparemap); 2025 if (error) { 2026 device_printf(sc_if->msk_if_dev, 2027 "failed to create spare Rx dmamap\n"); 2028 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2029 sc_if->msk_cdata.msk_rx_tag = NULL; 2030 return error; 2031 } 2032 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2033 struct msk_rxdesc *rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2034 2035 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 2036 BUS_DMA_WAITOK, &rxd->rx_dmamap); 2037 if (error) { 2038 device_printf(sc_if->msk_if_dev, 2039 "failed to create %dth Rx dmamap\n", i); 2040 2041 for (j = 0; j < i; ++j) { 2042 rxd = &sc_if->msk_cdata.msk_rxdesc[j]; 2043 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2044 rxd->rx_dmamap); 2045 } 2046 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2047 sc_if->msk_cdata.msk_rx_sparemap); 2048 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2049 sc_if->msk_cdata.msk_rx_tag = NULL; 2050 2051 return error; 2052 } 2053 } 2054 2055 #ifdef MSK_JUMBO 2056 SLIST_INIT(&sc_if->msk_jfree_listhead); 2057 SLIST_INIT(&sc_if->msk_jinuse_listhead); 2058 2059 /* Create tag for jumbo Rx ring. */ 2060 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2061 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2062 BUS_SPACE_MAXADDR, /* lowaddr */ 2063 BUS_SPACE_MAXADDR, /* highaddr */ 2064 NULL, NULL, /* filter, filterarg */ 2065 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2066 1, /* nsegments */ 2067 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2068 0, /* flags */ 2069 NULL, NULL, /* lockfunc, lockarg */ 2070 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2071 if (error != 0) { 2072 device_printf(sc_if->msk_if_dev, 2073 "failed to create jumbo Rx ring DMA tag\n"); 2074 goto fail; 2075 } 2076 2077 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2078 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2079 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2080 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2081 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2082 if (error != 0) { 2083 device_printf(sc_if->msk_if_dev, 2084 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2085 goto fail; 2086 } 2087 2088 ctx.msk_busaddr = 0; 2089 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2090 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2091 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2092 msk_dmamap_cb, &ctx, 0); 2093 if (error != 0) { 2094 device_printf(sc_if->msk_if_dev, 2095 "failed to load DMA'able memory for jumbo Rx ring\n"); 2096 goto fail; 2097 } 2098 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2099 2100 /* Create tag for jumbo buffer blocks. */ 2101 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2102 PAGE_SIZE, 0, /* alignment, boundary */ 2103 BUS_SPACE_MAXADDR, /* lowaddr */ 2104 BUS_SPACE_MAXADDR, /* highaddr */ 2105 NULL, NULL, /* filter, filterarg */ 2106 MSK_JMEM, /* maxsize */ 2107 1, /* nsegments */ 2108 MSK_JMEM, /* maxsegsize */ 2109 0, /* flags */ 2110 NULL, NULL, /* lockfunc, lockarg */ 2111 &sc_if->msk_cdata.msk_jumbo_tag); 2112 if (error != 0) { 2113 device_printf(sc_if->msk_if_dev, 2114 "failed to create jumbo Rx buffer block DMA tag\n"); 2115 goto fail; 2116 } 2117 2118 /* Create tag for jumbo Rx buffers. */ 2119 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2120 PAGE_SIZE, 0, /* alignment, boundary */ 2121 BUS_SPACE_MAXADDR, /* lowaddr */ 2122 BUS_SPACE_MAXADDR, /* highaddr */ 2123 NULL, NULL, /* filter, filterarg */ 2124 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2125 MSK_MAXRXSEGS, /* nsegments */ 2126 MSK_JLEN, /* maxsegsize */ 2127 0, /* flags */ 2128 NULL, NULL, /* lockfunc, lockarg */ 2129 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2130 if (error != 0) { 2131 device_printf(sc_if->msk_if_dev, 2132 "failed to create jumbo Rx DMA tag\n"); 2133 goto fail; 2134 } 2135 2136 /* Create DMA maps for jumbo Rx buffers. */ 2137 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2138 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2139 device_printf(sc_if->msk_if_dev, 2140 "failed to create spare jumbo Rx dmamap\n"); 2141 goto fail; 2142 } 2143 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2144 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2145 jrxd->rx_m = NULL; 2146 jrxd->rx_dmamap = NULL; 2147 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2148 &jrxd->rx_dmamap); 2149 if (error != 0) { 2150 device_printf(sc_if->msk_if_dev, 2151 "failed to create jumbo Rx dmamap\n"); 2152 goto fail; 2153 } 2154 } 2155 2156 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2157 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2158 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2159 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2160 &sc_if->msk_cdata.msk_jumbo_map); 2161 if (error != 0) { 2162 device_printf(sc_if->msk_if_dev, 2163 "failed to allocate DMA'able memory for jumbo buf\n"); 2164 goto fail; 2165 } 2166 2167 ctx.msk_busaddr = 0; 2168 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2169 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2170 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2171 if (error != 0) { 2172 device_printf(sc_if->msk_if_dev, 2173 "failed to load DMA'able memory for jumbobuf\n"); 2174 goto fail; 2175 } 2176 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2177 2178 /* 2179 * Now divide it up into 9K pieces and save the addresses 2180 * in an array. 2181 */ 2182 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2183 for (i = 0; i < MSK_JSLOTS; i++) { 2184 sc_if->msk_cdata.msk_jslots[i] = ptr; 2185 ptr += MSK_JLEN; 2186 entry = malloc(sizeof(struct msk_jpool_entry), 2187 M_DEVBUF, M_WAITOK); 2188 if (entry == NULL) { 2189 device_printf(sc_if->msk_if_dev, 2190 "no memory for jumbo buffers!\n"); 2191 error = ENOMEM; 2192 goto fail; 2193 } 2194 entry->slot = i; 2195 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2196 jpool_entries); 2197 } 2198 #endif 2199 return 0; 2200 } 2201 2202 static void 2203 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2204 { 2205 struct msk_txdesc *txd; 2206 struct msk_rxdesc *rxd; 2207 #ifdef MSK_JUMBO 2208 struct msk_rxdesc *jrxd; 2209 struct msk_jpool_entry *entry; 2210 #endif 2211 int i; 2212 2213 #ifdef MSK_JUMBO 2214 MSK_JLIST_LOCK(sc_if); 2215 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2216 device_printf(sc_if->msk_if_dev, 2217 "asked to free buffer that is in use!\n"); 2218 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2219 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2220 jpool_entries); 2221 } 2222 2223 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2224 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2225 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2226 free(entry, M_DEVBUF); 2227 } 2228 MSK_JLIST_UNLOCK(sc_if); 2229 2230 /* Destroy jumbo buffer block. */ 2231 if (sc_if->msk_cdata.msk_jumbo_map) 2232 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2233 sc_if->msk_cdata.msk_jumbo_map); 2234 2235 if (sc_if->msk_rdata.msk_jumbo_buf) { 2236 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2237 sc_if->msk_rdata.msk_jumbo_buf, 2238 sc_if->msk_cdata.msk_jumbo_map); 2239 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2240 sc_if->msk_cdata.msk_jumbo_map = NULL; 2241 } 2242 2243 /* Jumbo Rx ring. */ 2244 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2245 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2246 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2247 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2248 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2249 sc_if->msk_rdata.msk_jumbo_rx_ring) 2250 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2251 sc_if->msk_rdata.msk_jumbo_rx_ring, 2252 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2253 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2254 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2255 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2256 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2257 } 2258 2259 /* Jumbo Rx buffers. */ 2260 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2261 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2262 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2263 if (jrxd->rx_dmamap) { 2264 bus_dmamap_destroy( 2265 sc_if->msk_cdata.msk_jumbo_rx_tag, 2266 jrxd->rx_dmamap); 2267 jrxd->rx_dmamap = NULL; 2268 } 2269 } 2270 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2271 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2272 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2273 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2274 } 2275 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2276 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2277 } 2278 #endif 2279 2280 /* Tx ring. */ 2281 msk_dmamem_destroy(sc_if->msk_cdata.msk_tx_ring_tag, 2282 sc_if->msk_rdata.msk_tx_ring, 2283 sc_if->msk_cdata.msk_tx_ring_map); 2284 2285 /* Rx ring. */ 2286 msk_dmamem_destroy(sc_if->msk_cdata.msk_rx_ring_tag, 2287 sc_if->msk_rdata.msk_rx_ring, 2288 sc_if->msk_cdata.msk_rx_ring_map); 2289 2290 /* Tx buffers. */ 2291 if (sc_if->msk_cdata.msk_tx_tag) { 2292 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2293 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2294 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2295 txd->tx_dmamap); 2296 } 2297 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2298 sc_if->msk_cdata.msk_tx_tag = NULL; 2299 } 2300 2301 /* Rx buffers. */ 2302 if (sc_if->msk_cdata.msk_rx_tag) { 2303 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2304 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2305 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2306 rxd->rx_dmamap); 2307 } 2308 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2309 sc_if->msk_cdata.msk_rx_sparemap); 2310 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2311 sc_if->msk_cdata.msk_rx_tag = NULL; 2312 } 2313 2314 if (sc_if->msk_cdata.msk_parent_tag) { 2315 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2316 sc_if->msk_cdata.msk_parent_tag = NULL; 2317 } 2318 } 2319 2320 #ifdef MSK_JUMBO 2321 /* 2322 * Allocate a jumbo buffer. 2323 */ 2324 static void * 2325 msk_jalloc(struct msk_if_softc *sc_if) 2326 { 2327 struct msk_jpool_entry *entry; 2328 2329 MSK_JLIST_LOCK(sc_if); 2330 2331 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2332 2333 if (entry == NULL) { 2334 MSK_JLIST_UNLOCK(sc_if); 2335 return (NULL); 2336 } 2337 2338 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2339 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2340 2341 MSK_JLIST_UNLOCK(sc_if); 2342 2343 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2344 } 2345 2346 /* 2347 * Release a jumbo buffer. 2348 */ 2349 static void 2350 msk_jfree(void *buf, void *args) 2351 { 2352 struct msk_if_softc *sc_if; 2353 struct msk_jpool_entry *entry; 2354 int i; 2355 2356 /* Extract the softc struct pointer. */ 2357 sc_if = (struct msk_if_softc *)args; 2358 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2359 2360 MSK_JLIST_LOCK(sc_if); 2361 /* Calculate the slot this buffer belongs to. */ 2362 i = ((vm_offset_t)buf 2363 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2364 KASSERT(i >= 0 && i < MSK_JSLOTS, 2365 ("%s: asked to free buffer that we don't manage!", __func__)); 2366 2367 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2368 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2369 entry->slot = i; 2370 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2371 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2372 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2373 wakeup(sc_if); 2374 2375 MSK_JLIST_UNLOCK(sc_if); 2376 } 2377 #endif 2378 2379 static int 2380 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2381 { 2382 struct msk_txdesc *txd, *txd_last; 2383 struct msk_tx_desc *tx_le; 2384 struct mbuf *m; 2385 bus_dmamap_t map; 2386 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2387 uint32_t control, prod, si; 2388 uint16_t offset, tcp_offset; 2389 int error, i, nsegs, maxsegs, defrag; 2390 2391 maxsegs = MSK_TX_RING_CNT - sc_if->msk_cdata.msk_tx_cnt - 2392 MSK_RESERVED_TX_DESC_CNT; 2393 KASSERT(maxsegs >= MSK_SPARE_TX_DESC_CNT, 2394 ("not enough spare TX desc")); 2395 if (maxsegs > MSK_MAXTXSEGS) 2396 maxsegs = MSK_MAXTXSEGS; 2397 2398 /* 2399 * Align TX buffer to 64bytes boundary. This greately improves 2400 * bulk data TX performance on my 88E8053 (+100Mbps) at least. 2401 * Try avoiding m_defrag(), if the mbufs are not chained together 2402 * by m_next (i.e. m->m_len == m->m_pkthdr.len). 2403 */ 2404 2405 #define MSK_TXBUF_ALIGN 64 2406 #define MSK_TXBUF_MASK (MSK_TXBUF_ALIGN - 1) 2407 2408 defrag = 1; 2409 m = *m_head; 2410 if (m->m_len == m->m_pkthdr.len) { 2411 int space; 2412 2413 space = ((uintptr_t)m->m_data & MSK_TXBUF_MASK); 2414 if (space) { 2415 if (M_WRITABLE(m)) { 2416 if (M_TRAILINGSPACE(m) >= space) { 2417 /* e.g. TCP ACKs */ 2418 bcopy(m->m_data, m->m_data + space, 2419 m->m_len); 2420 m->m_data += space; 2421 defrag = 0; 2422 sc_if->msk_softc->msk_trailing_copied++; 2423 } else { 2424 space = MSK_TXBUF_ALIGN - space; 2425 if (M_LEADINGSPACE(m) >= space) { 2426 /* e.g. Small UDP datagrams */ 2427 bcopy(m->m_data, 2428 m->m_data - space, 2429 m->m_len); 2430 m->m_data -= space; 2431 defrag = 0; 2432 sc_if->msk_softc-> 2433 msk_leading_copied++; 2434 } 2435 } 2436 } 2437 } else { 2438 /* e.g. on forwarding path */ 2439 defrag = 0; 2440 } 2441 } 2442 if (defrag) { 2443 m = m_defrag(*m_head, MB_DONTWAIT); 2444 if (m == NULL) { 2445 m_freem(*m_head); 2446 *m_head = NULL; 2447 return ENOBUFS; 2448 } 2449 *m_head = m; 2450 } else { 2451 sc_if->msk_softc->msk_defrag_avoided++; 2452 } 2453 2454 #undef MSK_TXBUF_MASK 2455 #undef MSK_TXBUF_ALIGN 2456 2457 tcp_offset = offset = 0; 2458 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) { 2459 /* 2460 * Since mbuf has no protocol specific structure information 2461 * in it we have to inspect protocol information here to 2462 * setup TSO and checksum offload. I don't know why Marvell 2463 * made a such decision in chip design because other GigE 2464 * hardwares normally takes care of all these chores in 2465 * hardware. However, TSO performance of Yukon II is very 2466 * good such that it's worth to implement it. 2467 */ 2468 struct ether_header *eh; 2469 struct ip *ip; 2470 2471 /* TODO check for M_WRITABLE(m) */ 2472 2473 offset = sizeof(struct ether_header); 2474 m = m_pullup(m, offset); 2475 if (m == NULL) { 2476 *m_head = NULL; 2477 return (ENOBUFS); 2478 } 2479 eh = mtod(m, struct ether_header *); 2480 /* Check if hardware VLAN insertion is off. */ 2481 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2482 offset = sizeof(struct ether_vlan_header); 2483 m = m_pullup(m, offset); 2484 if (m == NULL) { 2485 *m_head = NULL; 2486 return (ENOBUFS); 2487 } 2488 } 2489 m = m_pullup(m, offset + sizeof(struct ip)); 2490 if (m == NULL) { 2491 *m_head = NULL; 2492 return (ENOBUFS); 2493 } 2494 ip = (struct ip *)(mtod(m, char *) + offset); 2495 offset += (ip->ip_hl << 2); 2496 tcp_offset = offset; 2497 /* 2498 * It seems that Yukon II has Tx checksum offload bug for 2499 * small TCP packets that's less than 60 bytes in size 2500 * (e.g. TCP window probe packet, pure ACK packet). 2501 * Common work around like padding with zeros to make the 2502 * frame minimum ethernet frame size didn't work at all. 2503 * Instead of disabling checksum offload completely we 2504 * resort to S/W checksum routine when we encounter short 2505 * TCP frames. 2506 * Short UDP packets appear to be handled correctly by 2507 * Yukon II. 2508 */ 2509 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2510 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2511 uint16_t csum; 2512 2513 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2514 (ip->ip_hl << 2), offset); 2515 *(uint16_t *)(m->m_data + offset + 2516 m->m_pkthdr.csum_data) = csum; 2517 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2518 } 2519 *m_head = m; 2520 } 2521 2522 prod = sc_if->msk_cdata.msk_tx_prod; 2523 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2524 txd_last = txd; 2525 map = txd->tx_dmamap; 2526 2527 error = bus_dmamap_load_mbuf_defrag(sc_if->msk_cdata.msk_tx_tag, map, 2528 m_head, txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2529 if (error) { 2530 m_freem(*m_head); 2531 *m_head = NULL; 2532 return error; 2533 } 2534 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2535 2536 m = *m_head; 2537 control = 0; 2538 tx_le = NULL; 2539 2540 #ifdef notyet 2541 /* Check if we have a VLAN tag to insert. */ 2542 if ((m->m_flags & M_VLANTAG) != 0) { 2543 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2544 tx_le->msk_addr = htole32(0); 2545 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2546 htons(m->m_pkthdr.ether_vtag)); 2547 sc_if->msk_cdata.msk_tx_cnt++; 2548 MSK_INC(prod, MSK_TX_RING_CNT); 2549 control |= INS_VLAN; 2550 } 2551 #endif 2552 /* Check if we have to handle checksum offload. */ 2553 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) { 2554 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2555 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2556 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2557 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2558 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2559 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2560 control |= UDPTCP; 2561 sc_if->msk_cdata.msk_tx_cnt++; 2562 MSK_INC(prod, MSK_TX_RING_CNT); 2563 } 2564 2565 si = prod; 2566 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2567 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2568 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2569 OP_PACKET); 2570 sc_if->msk_cdata.msk_tx_cnt++; 2571 MSK_INC(prod, MSK_TX_RING_CNT); 2572 2573 for (i = 1; i < nsegs; i++) { 2574 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2575 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2576 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2577 OP_BUFFER | HW_OWNER); 2578 sc_if->msk_cdata.msk_tx_cnt++; 2579 MSK_INC(prod, MSK_TX_RING_CNT); 2580 } 2581 /* Update producer index. */ 2582 sc_if->msk_cdata.msk_tx_prod = prod; 2583 2584 /* Set EOP on the last desciptor. */ 2585 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2586 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2587 tx_le->msk_control |= htole32(EOP); 2588 2589 /* Turn the first descriptor ownership to hardware. */ 2590 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2591 tx_le->msk_control |= htole32(HW_OWNER); 2592 2593 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2594 map = txd_last->tx_dmamap; 2595 txd_last->tx_dmamap = txd->tx_dmamap; 2596 txd->tx_dmamap = map; 2597 txd->tx_m = m; 2598 2599 return (0); 2600 } 2601 2602 static void 2603 msk_start(struct ifnet *ifp) 2604 { 2605 struct msk_if_softc *sc_if; 2606 struct mbuf *m_head; 2607 int enq; 2608 2609 sc_if = ifp->if_softc; 2610 2611 ASSERT_SERIALIZED(ifp->if_serializer); 2612 2613 if (!sc_if->msk_link) { 2614 ifq_purge(&ifp->if_snd); 2615 return; 2616 } 2617 2618 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2619 return; 2620 2621 enq = 0; 2622 while (!ifq_is_empty(&ifp->if_snd)) { 2623 if (MSK_IS_OACTIVE(sc_if)) { 2624 ifp->if_flags |= IFF_OACTIVE; 2625 break; 2626 } 2627 2628 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2629 if (m_head == NULL) 2630 break; 2631 2632 /* 2633 * Pack the data into the transmit ring. If we 2634 * don't have room, set the OACTIVE flag and wait 2635 * for the NIC to drain the ring. 2636 */ 2637 if (msk_encap(sc_if, &m_head) != 0) { 2638 ifp->if_oerrors++; 2639 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2640 continue; 2641 } else { 2642 ifp->if_flags |= IFF_OACTIVE; 2643 break; 2644 } 2645 } 2646 enq = 1; 2647 2648 /* 2649 * If there's a BPF listener, bounce a copy of this frame 2650 * to him. 2651 */ 2652 BPF_MTAP(ifp, m_head); 2653 } 2654 2655 if (enq) { 2656 /* Transmit */ 2657 CSR_WRITE_2(sc_if->msk_softc, 2658 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2659 sc_if->msk_cdata.msk_tx_prod); 2660 2661 /* Set a timeout in case the chip goes out to lunch. */ 2662 ifp->if_timer = MSK_TX_TIMEOUT; 2663 } 2664 } 2665 2666 static void 2667 msk_watchdog(struct ifnet *ifp) 2668 { 2669 struct msk_if_softc *sc_if = ifp->if_softc; 2670 uint32_t ridx; 2671 int idx; 2672 2673 ASSERT_SERIALIZED(ifp->if_serializer); 2674 2675 if (sc_if->msk_link == 0) { 2676 if (bootverbose) 2677 if_printf(sc_if->msk_ifp, "watchdog timeout " 2678 "(missed link)\n"); 2679 ifp->if_oerrors++; 2680 msk_init(sc_if); 2681 return; 2682 } 2683 2684 /* 2685 * Reclaim first as there is a possibility of losing Tx completion 2686 * interrupts. 2687 */ 2688 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2689 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2690 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2691 msk_txeof(sc_if, idx); 2692 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2693 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2694 "-- recovering\n"); 2695 if (!ifq_is_empty(&ifp->if_snd)) 2696 if_devstart(ifp); 2697 return; 2698 } 2699 } 2700 2701 if_printf(ifp, "watchdog timeout\n"); 2702 ifp->if_oerrors++; 2703 msk_init(sc_if); 2704 if (!ifq_is_empty(&ifp->if_snd)) 2705 if_devstart(ifp); 2706 } 2707 2708 static int 2709 mskc_shutdown(device_t dev) 2710 { 2711 struct msk_softc *sc = device_get_softc(dev); 2712 int i; 2713 2714 lwkt_serialize_enter(&sc->msk_serializer); 2715 2716 for (i = 0; i < sc->msk_num_port; i++) { 2717 if (sc->msk_if[i] != NULL) 2718 msk_stop(sc->msk_if[i]); 2719 } 2720 2721 /* Put hardware reset. */ 2722 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2723 2724 lwkt_serialize_exit(&sc->msk_serializer); 2725 return (0); 2726 } 2727 2728 static int 2729 mskc_suspend(device_t dev) 2730 { 2731 struct msk_softc *sc = device_get_softc(dev); 2732 int i; 2733 2734 lwkt_serialize_enter(&sc->msk_serializer); 2735 2736 for (i = 0; i < sc->msk_num_port; i++) { 2737 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2738 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_RUNNING) != 0)) 2739 msk_stop(sc->msk_if[i]); 2740 } 2741 2742 /* Disable all interrupts. */ 2743 CSR_WRITE_4(sc, B0_IMSK, 0); 2744 CSR_READ_4(sc, B0_IMSK); 2745 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2746 CSR_READ_4(sc, B0_HWE_IMSK); 2747 2748 mskc_phy_power(sc, MSK_PHY_POWERDOWN); 2749 2750 /* Put hardware reset. */ 2751 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2752 sc->msk_suspended = 1; 2753 2754 lwkt_serialize_exit(&sc->msk_serializer); 2755 2756 return (0); 2757 } 2758 2759 static int 2760 mskc_resume(device_t dev) 2761 { 2762 struct msk_softc *sc = device_get_softc(dev); 2763 int i; 2764 2765 lwkt_serialize_enter(&sc->msk_serializer); 2766 2767 /* Enable all clocks before accessing any registers. */ 2768 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 2769 mskc_reset(sc); 2770 for (i = 0; i < sc->msk_num_port; i++) { 2771 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2772 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2773 msk_init(sc->msk_if[i]); 2774 } 2775 sc->msk_suspended = 0; 2776 2777 lwkt_serialize_exit(&sc->msk_serializer); 2778 2779 return (0); 2780 } 2781 2782 static void 2783 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2784 { 2785 struct mbuf *m; 2786 struct ifnet *ifp; 2787 struct msk_rxdesc *rxd; 2788 int cons, rxlen; 2789 2790 ifp = sc_if->msk_ifp; 2791 2792 cons = sc_if->msk_cdata.msk_rx_cons; 2793 do { 2794 rxlen = status >> 16; 2795 if ((status & GMR_FS_VLAN) != 0 && 2796 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2797 rxlen -= EVL_ENCAPLEN; 2798 if (sc_if->msk_flags & MSK_FLAG_NORXCHK) { 2799 /* 2800 * For controllers that returns bogus status code 2801 * just do minimal check and let upper stack 2802 * handle this frame. 2803 */ 2804 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 2805 ifp->if_ierrors++; 2806 msk_discard_rxbuf(sc_if, cons); 2807 break; 2808 } 2809 } else if (len > sc_if->msk_framesize || 2810 ((status & GMR_FS_ANY_ERR) != 0) || 2811 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2812 /* Don't count flow-control packet as errors. */ 2813 if ((status & GMR_FS_GOOD_FC) == 0) 2814 ifp->if_ierrors++; 2815 msk_discard_rxbuf(sc_if, cons); 2816 break; 2817 } 2818 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2819 m = rxd->rx_m; 2820 if (msk_newbuf(sc_if, cons, 0) != 0) { 2821 ifp->if_iqdrops++; 2822 /* Reuse old buffer. */ 2823 msk_discard_rxbuf(sc_if, cons); 2824 break; 2825 } 2826 m->m_pkthdr.rcvif = ifp; 2827 m->m_pkthdr.len = m->m_len = len; 2828 ifp->if_ipackets++; 2829 #ifdef notyet 2830 /* Check for VLAN tagged packets. */ 2831 if ((status & GMR_FS_VLAN) != 0 && 2832 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2833 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2834 m->m_flags |= M_VLANTAG; 2835 } 2836 #endif 2837 2838 ifp->if_input(ifp, m); 2839 } while (0); 2840 2841 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2842 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2843 } 2844 2845 #ifdef MSK_JUMBO 2846 static void 2847 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2848 { 2849 struct mbuf *m; 2850 struct ifnet *ifp; 2851 struct msk_rxdesc *jrxd; 2852 int cons, rxlen; 2853 2854 ifp = sc_if->msk_ifp; 2855 2856 MSK_IF_LOCK_ASSERT(sc_if); 2857 2858 cons = sc_if->msk_cdata.msk_rx_cons; 2859 do { 2860 rxlen = status >> 16; 2861 if ((status & GMR_FS_VLAN) != 0 && 2862 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2863 rxlen -= ETHER_VLAN_ENCAP_LEN; 2864 if (len > sc_if->msk_framesize || 2865 ((status & GMR_FS_ANY_ERR) != 0) || 2866 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2867 /* Don't count flow-control packet as errors. */ 2868 if ((status & GMR_FS_GOOD_FC) == 0) 2869 ifp->if_ierrors++; 2870 msk_discard_jumbo_rxbuf(sc_if, cons); 2871 break; 2872 } 2873 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 2874 m = jrxd->rx_m; 2875 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 2876 ifp->if_iqdrops++; 2877 /* Reuse old buffer. */ 2878 msk_discard_jumbo_rxbuf(sc_if, cons); 2879 break; 2880 } 2881 m->m_pkthdr.rcvif = ifp; 2882 m->m_pkthdr.len = m->m_len = len; 2883 ifp->if_ipackets++; 2884 /* Check for VLAN tagged packets. */ 2885 if ((status & GMR_FS_VLAN) != 0 && 2886 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2887 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2888 m->m_flags |= M_VLANTAG; 2889 } 2890 MSK_IF_UNLOCK(sc_if); 2891 (*ifp->if_input)(ifp, m); 2892 MSK_IF_LOCK(sc_if); 2893 } while (0); 2894 2895 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 2896 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 2897 } 2898 #endif 2899 2900 static void 2901 msk_txeof(struct msk_if_softc *sc_if, int idx) 2902 { 2903 struct msk_txdesc *txd; 2904 struct msk_tx_desc *cur_tx; 2905 struct ifnet *ifp; 2906 uint32_t control; 2907 int cons, prog; 2908 2909 ifp = sc_if->msk_ifp; 2910 2911 /* 2912 * Go through our tx ring and free mbufs for those 2913 * frames that have been sent. 2914 */ 2915 cons = sc_if->msk_cdata.msk_tx_cons; 2916 prog = 0; 2917 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 2918 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 2919 break; 2920 prog++; 2921 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 2922 control = le32toh(cur_tx->msk_control); 2923 sc_if->msk_cdata.msk_tx_cnt--; 2924 if ((control & EOP) == 0) 2925 continue; 2926 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 2927 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 2928 2929 ifp->if_opackets++; 2930 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 2931 __func__)); 2932 m_freem(txd->tx_m); 2933 txd->tx_m = NULL; 2934 } 2935 2936 if (prog > 0) { 2937 sc_if->msk_cdata.msk_tx_cons = cons; 2938 if (!MSK_IS_OACTIVE(sc_if)) 2939 ifp->if_flags &= ~IFF_OACTIVE; 2940 if (sc_if->msk_cdata.msk_tx_cnt == 0) 2941 ifp->if_timer = 0; 2942 /* No need to sync LEs as we didn't update LEs. */ 2943 } 2944 } 2945 2946 static void 2947 msk_tick(void *xsc_if) 2948 { 2949 struct msk_if_softc *sc_if = xsc_if; 2950 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2951 struct mii_data *mii; 2952 2953 lwkt_serialize_enter(ifp->if_serializer); 2954 2955 mii = device_get_softc(sc_if->msk_miibus); 2956 2957 mii_tick(mii); 2958 if (!sc_if->msk_link) 2959 msk_miibus_statchg(sc_if->msk_if_dev); 2960 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 2961 2962 lwkt_serialize_exit(ifp->if_serializer); 2963 } 2964 2965 static void 2966 msk_intr_phy(struct msk_if_softc *sc_if) 2967 { 2968 uint16_t status; 2969 2970 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 2971 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 2972 /* Handle FIFO Underrun/Overflow? */ 2973 if (status & PHY_M_IS_FIFO_ERROR) { 2974 device_printf(sc_if->msk_if_dev, 2975 "PHY FIFO underrun/overflow.\n"); 2976 } 2977 } 2978 2979 static void 2980 msk_intr_gmac(struct msk_if_softc *sc_if) 2981 { 2982 struct msk_softc *sc; 2983 uint8_t status; 2984 2985 sc = sc_if->msk_softc; 2986 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 2987 2988 /* GMAC Rx FIFO overrun. */ 2989 if ((status & GM_IS_RX_FF_OR) != 0) { 2990 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 2991 GMF_CLI_RX_FO); 2992 } 2993 /* GMAC Tx FIFO underrun. */ 2994 if ((status & GM_IS_TX_FF_UR) != 0) { 2995 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 2996 GMF_CLI_TX_FU); 2997 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 2998 /* 2999 * XXX 3000 * In case of Tx underrun, we may need to flush/reset 3001 * Tx MAC but that would also require resynchronization 3002 * with status LEs. Reintializing status LEs would 3003 * affect other port in dual MAC configuration so it 3004 * should be avoided as possible as we can. 3005 * Due to lack of documentation it's all vague guess but 3006 * it needs more investigation. 3007 */ 3008 } 3009 } 3010 3011 static void 3012 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3013 { 3014 struct msk_softc *sc; 3015 3016 sc = sc_if->msk_softc; 3017 if ((status & Y2_IS_PAR_RD1) != 0) { 3018 device_printf(sc_if->msk_if_dev, 3019 "RAM buffer read parity error\n"); 3020 /* Clear IRQ. */ 3021 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3022 RI_CLR_RD_PERR); 3023 } 3024 if ((status & Y2_IS_PAR_WR1) != 0) { 3025 device_printf(sc_if->msk_if_dev, 3026 "RAM buffer write parity error\n"); 3027 /* Clear IRQ. */ 3028 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3029 RI_CLR_WR_PERR); 3030 } 3031 if ((status & Y2_IS_PAR_MAC1) != 0) { 3032 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3033 /* Clear IRQ. */ 3034 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3035 GMF_CLI_TX_PE); 3036 } 3037 if ((status & Y2_IS_PAR_RX1) != 0) { 3038 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3039 /* Clear IRQ. */ 3040 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3041 } 3042 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3043 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3044 /* Clear IRQ. */ 3045 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3046 } 3047 } 3048 3049 static void 3050 mskc_intr_hwerr(struct msk_softc *sc) 3051 { 3052 uint32_t status; 3053 uint32_t tlphead[4]; 3054 3055 status = CSR_READ_4(sc, B0_HWE_ISRC); 3056 /* Time Stamp timer overflow. */ 3057 if ((status & Y2_IS_TIST_OV) != 0) 3058 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3059 if ((status & Y2_IS_PCI_NEXP) != 0) { 3060 /* 3061 * PCI Express Error occured which is not described in PEX 3062 * spec. 3063 * This error is also mapped either to Master Abort( 3064 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3065 * can only be cleared there. 3066 */ 3067 device_printf(sc->msk_dev, 3068 "PCI Express protocol violation error\n"); 3069 } 3070 3071 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3072 uint16_t v16; 3073 3074 if ((status & Y2_IS_MST_ERR) != 0) 3075 device_printf(sc->msk_dev, 3076 "unexpected IRQ Status error\n"); 3077 else 3078 device_printf(sc->msk_dev, 3079 "unexpected IRQ Master error\n"); 3080 /* Reset all bits in the PCI status register. */ 3081 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3082 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3083 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3084 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3085 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3086 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3087 } 3088 3089 /* Check for PCI Express Uncorrectable Error. */ 3090 if ((status & Y2_IS_PCI_EXP) != 0) { 3091 uint32_t v32; 3092 3093 /* 3094 * On PCI Express bus bridges are called root complexes (RC). 3095 * PCI Express errors are recognized by the root complex too, 3096 * which requests the system to handle the problem. After 3097 * error occurence it may be that no access to the adapter 3098 * may be performed any longer. 3099 */ 3100 3101 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3102 if ((v32 & PEX_UNSUP_REQ) != 0) { 3103 /* Ignore unsupported request error. */ 3104 if (bootverbose) { 3105 device_printf(sc->msk_dev, 3106 "Uncorrectable PCI Express error\n"); 3107 } 3108 } 3109 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3110 int i; 3111 3112 /* Get TLP header form Log Registers. */ 3113 for (i = 0; i < 4; i++) 3114 tlphead[i] = CSR_PCI_READ_4(sc, 3115 PEX_HEADER_LOG + i * 4); 3116 /* Check for vendor defined broadcast message. */ 3117 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3118 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3119 CSR_WRITE_4(sc, B0_HWE_IMSK, 3120 sc->msk_intrhwemask); 3121 CSR_READ_4(sc, B0_HWE_IMSK); 3122 } 3123 } 3124 /* Clear the interrupt. */ 3125 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3126 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3127 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3128 } 3129 3130 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3131 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3132 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3133 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3134 } 3135 3136 static __inline void 3137 msk_rxput(struct msk_if_softc *sc_if) 3138 { 3139 struct msk_softc *sc; 3140 3141 sc = sc_if->msk_softc; 3142 #ifdef MSK_JUMBO 3143 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3144 bus_dmamap_sync( 3145 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3146 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3147 BUS_DMASYNC_PREWRITE); 3148 } 3149 #endif 3150 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3151 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3152 } 3153 3154 static int 3155 mskc_handle_events(struct msk_softc *sc) 3156 { 3157 struct msk_if_softc *sc_if; 3158 int rxput[2]; 3159 struct msk_stat_desc *sd; 3160 uint32_t control, status; 3161 int cons, idx, len, port, rxprog; 3162 3163 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3164 if (idx == sc->msk_stat_cons) 3165 return (0); 3166 3167 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3168 3169 rxprog = 0; 3170 for (cons = sc->msk_stat_cons; cons != idx;) { 3171 sd = &sc->msk_stat_ring[cons]; 3172 control = le32toh(sd->msk_control); 3173 if ((control & HW_OWNER) == 0) 3174 break; 3175 /* 3176 * Marvell's FreeBSD driver updates status LE after clearing 3177 * HW_OWNER. However we don't have a way to sync single LE 3178 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3179 * an entire DMA map. So don't sync LE until we have a better 3180 * way to sync LEs. 3181 */ 3182 control &= ~HW_OWNER; 3183 sd->msk_control = htole32(control); 3184 status = le32toh(sd->msk_status); 3185 len = control & STLE_LEN_MASK; 3186 port = (control >> 16) & 0x01; 3187 sc_if = sc->msk_if[port]; 3188 if (sc_if == NULL) { 3189 device_printf(sc->msk_dev, "invalid port opcode " 3190 "0x%08x\n", control & STLE_OP_MASK); 3191 continue; 3192 } 3193 3194 switch (control & STLE_OP_MASK) { 3195 case OP_RXVLAN: 3196 sc_if->msk_vtag = ntohs(len); 3197 break; 3198 case OP_RXCHKSVLAN: 3199 sc_if->msk_vtag = ntohs(len); 3200 break; 3201 case OP_RXSTAT: 3202 if ((sc_if->msk_ifp->if_flags & IFF_RUNNING) == 0) 3203 break; 3204 #ifdef MSK_JUMBO 3205 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3206 msk_jumbo_rxeof(sc_if, status, len); 3207 else 3208 #endif 3209 msk_rxeof(sc_if, status, len); 3210 rxprog++; 3211 /* 3212 * Because there is no way to sync single Rx LE 3213 * put the DMA sync operation off until the end of 3214 * event processing. 3215 */ 3216 rxput[port]++; 3217 /* Update prefetch unit if we've passed water mark. */ 3218 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3219 msk_rxput(sc_if); 3220 rxput[port] = 0; 3221 } 3222 break; 3223 case OP_TXINDEXLE: 3224 if (sc->msk_if[MSK_PORT_A] != NULL) { 3225 msk_txeof(sc->msk_if[MSK_PORT_A], 3226 status & STLE_TXA1_MSKL); 3227 } 3228 if (sc->msk_if[MSK_PORT_B] != NULL) { 3229 msk_txeof(sc->msk_if[MSK_PORT_B], 3230 ((status & STLE_TXA2_MSKL) >> 3231 STLE_TXA2_SHIFTL) | 3232 ((len & STLE_TXA2_MSKH) << 3233 STLE_TXA2_SHIFTH)); 3234 } 3235 break; 3236 default: 3237 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3238 control & STLE_OP_MASK); 3239 break; 3240 } 3241 MSK_INC(cons, MSK_STAT_RING_CNT); 3242 if (rxprog > sc->msk_process_limit) 3243 break; 3244 } 3245 3246 sc->msk_stat_cons = cons; 3247 /* XXX We should sync status LEs here. See above notes. */ 3248 3249 if (rxput[MSK_PORT_A] > 0) 3250 msk_rxput(sc->msk_if[MSK_PORT_A]); 3251 if (rxput[MSK_PORT_B] > 0) 3252 msk_rxput(sc->msk_if[MSK_PORT_B]); 3253 3254 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3255 } 3256 3257 /* Legacy interrupt handler for shared interrupt. */ 3258 static void 3259 mskc_intr(void *xsc) 3260 { 3261 struct msk_softc *sc; 3262 struct msk_if_softc *sc_if0, *sc_if1; 3263 struct ifnet *ifp0, *ifp1; 3264 uint32_t status; 3265 3266 sc = xsc; 3267 ASSERT_SERIALIZED(&sc->msk_serializer); 3268 3269 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3270 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3271 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3272 (status & sc->msk_intrmask) == 0) { 3273 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3274 return; 3275 } 3276 3277 sc_if0 = sc->msk_if[MSK_PORT_A]; 3278 sc_if1 = sc->msk_if[MSK_PORT_B]; 3279 ifp0 = ifp1 = NULL; 3280 if (sc_if0 != NULL) 3281 ifp0 = sc_if0->msk_ifp; 3282 if (sc_if1 != NULL) 3283 ifp1 = sc_if1->msk_ifp; 3284 3285 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3286 msk_intr_phy(sc_if0); 3287 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3288 msk_intr_phy(sc_if1); 3289 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3290 msk_intr_gmac(sc_if0); 3291 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3292 msk_intr_gmac(sc_if1); 3293 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3294 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3295 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3296 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3297 CSR_READ_4(sc, B0_IMSK); 3298 } 3299 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3300 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3301 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3302 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3303 CSR_READ_4(sc, B0_IMSK); 3304 } 3305 if ((status & Y2_IS_HW_ERR) != 0) 3306 mskc_intr_hwerr(sc); 3307 3308 while (mskc_handle_events(sc) != 0) 3309 ; 3310 if ((status & Y2_IS_STAT_BMU) != 0) 3311 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3312 3313 /* Reenable interrupts. */ 3314 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3315 3316 if (ifp0 != NULL && (ifp0->if_flags & IFF_RUNNING) != 0 && 3317 !ifq_is_empty(&ifp0->if_snd)) 3318 if_devstart(ifp0); 3319 if (ifp1 != NULL && (ifp1->if_flags & IFF_RUNNING) != 0 && 3320 !ifq_is_empty(&ifp1->if_snd)) 3321 if_devstart(ifp1); 3322 } 3323 3324 static void 3325 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3326 { 3327 struct msk_softc *sc = sc_if->msk_softc; 3328 struct ifnet *ifp = sc_if->msk_ifp; 3329 3330 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3331 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3332 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3333 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3334 TX_STFW_ENA); 3335 } else { 3336 if (ifp->if_mtu > ETHERMTU) { 3337 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3338 CSR_WRITE_4(sc, 3339 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3340 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3341 /* Disable Store & Forward mode for Tx. */ 3342 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3343 TX_STFW_DIS); 3344 } else { 3345 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3346 TX_STFW_ENA); 3347 } 3348 } 3349 } 3350 3351 static void 3352 msk_init(void *xsc) 3353 { 3354 struct msk_if_softc *sc_if = xsc; 3355 struct msk_softc *sc = sc_if->msk_softc; 3356 struct ifnet *ifp = sc_if->msk_ifp; 3357 struct mii_data *mii; 3358 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3359 uint16_t gmac; 3360 uint32_t reg; 3361 int error, i; 3362 3363 ASSERT_SERIALIZED(ifp->if_serializer); 3364 3365 mii = device_get_softc(sc_if->msk_miibus); 3366 3367 error = 0; 3368 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3369 msk_stop(sc_if); 3370 3371 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN; 3372 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3373 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3374 /* 3375 * In Yukon EC Ultra, TSO & checksum offload is not 3376 * supported for jumbo frame. 3377 */ 3378 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 3379 ifp->if_capenable &= ~IFCAP_TXCSUM; 3380 } 3381 3382 /* GMAC Control reset. */ 3383 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3384 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3385 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3386 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3387 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 3388 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3389 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3390 GMC_BYP_RETR_ON); 3391 } 3392 3393 /* 3394 * Initialize GMAC first such that speed/duplex/flow-control 3395 * parameters are renegotiated when interface is brought up. 3396 */ 3397 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3398 3399 /* Dummy read the Interrupt Source Register. */ 3400 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3401 3402 /* Set MIB Clear Counter Mode. */ 3403 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3404 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3405 /* Read all MIB Counters with Clear Mode set. */ 3406 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3407 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3408 /* Clear MIB Clear Counter Mode. */ 3409 gmac &= ~GM_PAR_MIB_CLR; 3410 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3411 3412 /* Disable FCS. */ 3413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3414 3415 /* Setup Transmit Control Register. */ 3416 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3417 3418 /* Setup Transmit Flow Control Register. */ 3419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3420 3421 /* Setup Transmit Parameter Register. */ 3422 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3423 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3424 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3425 3426 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3427 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3428 3429 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3430 gmac |= GM_SMOD_JUMBO_ENA; 3431 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3432 3433 /* Set station address. */ 3434 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3435 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3436 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3437 eaddr[i]); 3438 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3439 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3440 eaddr[i]); 3441 3442 /* Disable interrupts for counter overflows. */ 3443 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3444 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3445 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3446 3447 /* Configure Rx MAC FIFO. */ 3448 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3449 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3450 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3451 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3452 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3453 reg |= GMF_RX_OVER_ON; 3454 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3455 3456 /* Set receive filter. */ 3457 msk_rxfilter(sc_if); 3458 3459 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3460 /* Clear flush mask - HW bug. */ 3461 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3462 } else { 3463 /* Flush Rx MAC FIFO on any flow control or error. */ 3464 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3465 GMR_FS_ANY_ERR); 3466 } 3467 3468 /* 3469 * Set Rx FIFO flush threshold to 64 bytes 1 FIFO word 3470 * due to hardware hang on receipt of pause frames. 3471 */ 3472 reg = RX_GMF_FL_THR_DEF + 1; 3473 /* Another magic for Yukon FE+ - From Linux. */ 3474 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3475 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3476 reg = 0x178; 3477 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3478 3479 3480 /* Configure Tx MAC FIFO. */ 3481 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3482 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3483 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3484 3485 /* Configure hardware VLAN tag insertion/stripping. */ 3486 msk_setvlan(sc_if, ifp); 3487 3488 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3489 /* Set Rx Pause threshould. */ 3490 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3491 MSK_ECU_LLPP); 3492 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3493 MSK_ECU_ULPP); 3494 /* Configure store-and-forward for Tx. */ 3495 msk_set_tx_stfwd(sc_if); 3496 } 3497 3498 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3499 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3500 /* Disable dynamic watermark - from Linux. */ 3501 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3502 reg &= ~0x03; 3503 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3504 } 3505 3506 /* 3507 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3508 * arbiter as we don't use Sync Tx queue. 3509 */ 3510 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3511 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3512 /* Enable the RAM Interface Arbiter. */ 3513 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3514 3515 /* Setup RAM buffer. */ 3516 msk_set_rambuffer(sc_if); 3517 3518 /* Disable Tx sync Queue. */ 3519 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3520 3521 /* Setup Tx Queue Bus Memory Interface. */ 3522 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3523 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3524 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3525 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3526 switch (sc->msk_hw_id) { 3527 case CHIP_ID_YUKON_EC_U: 3528 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3529 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3530 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3531 MSK_ECU_TXFF_LEV); 3532 } 3533 break; 3534 case CHIP_ID_YUKON_EX: 3535 /* 3536 * Yukon Extreme seems to have silicon bug for 3537 * automatic Tx checksum calculation capability. 3538 */ 3539 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) { 3540 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3541 F_TX_CHK_AUTO_OFF); 3542 } 3543 break; 3544 } 3545 3546 /* Setup Rx Queue Bus Memory Interface. */ 3547 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3548 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3549 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3550 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3551 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3552 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3553 /* MAC Rx RAM Read is controlled by hardware. */ 3554 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3555 } 3556 3557 msk_set_prefetch(sc, sc_if->msk_txq, 3558 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3559 msk_init_tx_ring(sc_if); 3560 3561 /* Disable Rx checksum offload and RSS hash. */ 3562 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3563 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3564 #ifdef MSK_JUMBO 3565 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3566 msk_set_prefetch(sc, sc_if->msk_rxq, 3567 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3568 MSK_JUMBO_RX_RING_CNT - 1); 3569 error = msk_init_jumbo_rx_ring(sc_if); 3570 } else 3571 #endif 3572 { 3573 msk_set_prefetch(sc, sc_if->msk_rxq, 3574 sc_if->msk_rdata.msk_rx_ring_paddr, 3575 MSK_RX_RING_CNT - 1); 3576 error = msk_init_rx_ring(sc_if); 3577 } 3578 if (error != 0) { 3579 device_printf(sc_if->msk_if_dev, 3580 "initialization failed: no memory for Rx buffers\n"); 3581 msk_stop(sc_if); 3582 return; 3583 } 3584 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3585 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 3586 /* Disable flushing of non-ASF packets. */ 3587 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3588 GMF_RX_MACSEC_FLUSH_OFF); 3589 } 3590 3591 /* Configure interrupt handling. */ 3592 if (sc_if->msk_port == MSK_PORT_A) { 3593 sc->msk_intrmask |= Y2_IS_PORT_A; 3594 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3595 } else { 3596 sc->msk_intrmask |= Y2_IS_PORT_B; 3597 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3598 } 3599 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3600 CSR_READ_4(sc, B0_HWE_IMSK); 3601 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3602 CSR_READ_4(sc, B0_IMSK); 3603 3604 sc_if->msk_link = 0; 3605 mii_mediachg(mii); 3606 3607 mskc_set_imtimer(sc); 3608 3609 ifp->if_flags |= IFF_RUNNING; 3610 ifp->if_flags &= ~IFF_OACTIVE; 3611 3612 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3613 } 3614 3615 static void 3616 msk_set_rambuffer(struct msk_if_softc *sc_if) 3617 { 3618 struct msk_softc *sc; 3619 int ltpp, utpp; 3620 3621 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3622 return; 3623 3624 sc = sc_if->msk_softc; 3625 3626 /* Setup Rx Queue. */ 3627 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3628 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3629 sc->msk_rxqstart[sc_if->msk_port] / 8); 3630 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3631 sc->msk_rxqend[sc_if->msk_port] / 8); 3632 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3633 sc->msk_rxqstart[sc_if->msk_port] / 8); 3634 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3635 sc->msk_rxqstart[sc_if->msk_port] / 8); 3636 3637 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3638 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3639 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3640 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3641 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3642 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3643 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3644 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3645 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3646 3647 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3648 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3649 3650 /* Setup Tx Queue. */ 3651 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3652 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3653 sc->msk_txqstart[sc_if->msk_port] / 8); 3654 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3655 sc->msk_txqend[sc_if->msk_port] / 8); 3656 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3657 sc->msk_txqstart[sc_if->msk_port] / 8); 3658 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3659 sc->msk_txqstart[sc_if->msk_port] / 8); 3660 /* Enable Store & Forward for Tx side. */ 3661 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3662 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3663 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3664 } 3665 3666 static void 3667 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3668 uint32_t count) 3669 { 3670 3671 /* Reset the prefetch unit. */ 3672 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3673 PREF_UNIT_RST_SET); 3674 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3675 PREF_UNIT_RST_CLR); 3676 /* Set LE base address. */ 3677 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3678 MSK_ADDR_LO(addr)); 3679 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3680 MSK_ADDR_HI(addr)); 3681 /* Set the list last index. */ 3682 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3683 count); 3684 /* Turn on prefetch unit. */ 3685 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3686 PREF_UNIT_OP_ON); 3687 /* Dummy read to ensure write. */ 3688 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3689 } 3690 3691 static void 3692 msk_stop(struct msk_if_softc *sc_if) 3693 { 3694 struct msk_softc *sc = sc_if->msk_softc; 3695 struct ifnet *ifp = sc_if->msk_ifp; 3696 struct msk_txdesc *txd; 3697 struct msk_rxdesc *rxd; 3698 #ifdef MSK_JUMBO 3699 struct msk_rxdesc *jrxd; 3700 #endif 3701 uint32_t val; 3702 int i; 3703 3704 ASSERT_SERIALIZED(ifp->if_serializer); 3705 3706 callout_stop(&sc_if->msk_tick_ch); 3707 ifp->if_timer = 0; 3708 3709 /* Disable interrupts. */ 3710 if (sc_if->msk_port == MSK_PORT_A) { 3711 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3712 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3713 } else { 3714 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3715 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3716 } 3717 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3718 CSR_READ_4(sc, B0_HWE_IMSK); 3719 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3720 CSR_READ_4(sc, B0_IMSK); 3721 3722 /* Disable Tx/Rx MAC. */ 3723 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3724 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3725 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3726 /* Read again to ensure writing. */ 3727 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3728 3729 /* Stop Tx BMU. */ 3730 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3731 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3732 for (i = 0; i < MSK_TIMEOUT; i++) { 3733 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3734 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3735 BMU_STOP); 3736 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3737 } else 3738 break; 3739 DELAY(1); 3740 } 3741 if (i == MSK_TIMEOUT) 3742 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3743 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3744 RB_RST_SET | RB_DIS_OP_MD); 3745 3746 /* Disable all GMAC interrupt. */ 3747 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3748 /* Disable PHY interrupt. */ 3749 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3750 3751 /* Disable the RAM Interface Arbiter. */ 3752 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3753 3754 /* Reset the PCI FIFO of the async Tx queue */ 3755 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3756 BMU_RST_SET | BMU_FIFO_RST); 3757 3758 /* Reset the Tx prefetch units. */ 3759 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3760 PREF_UNIT_RST_SET); 3761 3762 /* Reset the RAM Buffer async Tx queue. */ 3763 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3764 3765 /* Reset Tx MAC FIFO. */ 3766 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3767 /* Set Pause Off. */ 3768 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3769 3770 /* 3771 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3772 * reach the end of packet and since we can't make sure that we have 3773 * incoming data, we must reset the BMU while it is not during a DMA 3774 * transfer. Since it is possible that the Rx path is still active, 3775 * the Rx RAM buffer will be stopped first, so any possible incoming 3776 * data will not trigger a DMA. After the RAM buffer is stopped, the 3777 * BMU is polled until any DMA in progress is ended and only then it 3778 * will be reset. 3779 */ 3780 3781 /* Disable the RAM Buffer receive queue. */ 3782 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3783 for (i = 0; i < MSK_TIMEOUT; i++) { 3784 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3785 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3786 break; 3787 DELAY(1); 3788 } 3789 if (i == MSK_TIMEOUT) 3790 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3791 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3792 BMU_RST_SET | BMU_FIFO_RST); 3793 /* Reset the Rx prefetch unit. */ 3794 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3795 PREF_UNIT_RST_SET); 3796 /* Reset the RAM Buffer receive queue. */ 3797 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3798 /* Reset Rx MAC FIFO. */ 3799 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3800 3801 /* Free Rx and Tx mbufs still in the queues. */ 3802 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3803 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3804 if (rxd->rx_m != NULL) { 3805 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3806 rxd->rx_dmamap); 3807 m_freem(rxd->rx_m); 3808 rxd->rx_m = NULL; 3809 } 3810 } 3811 #ifdef MSK_JUMBO 3812 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3813 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3814 if (jrxd->rx_m != NULL) { 3815 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3816 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3817 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3818 jrxd->rx_dmamap); 3819 m_freem(jrxd->rx_m); 3820 jrxd->rx_m = NULL; 3821 } 3822 } 3823 #endif 3824 for (i = 0; i < MSK_TX_RING_CNT; i++) { 3825 txd = &sc_if->msk_cdata.msk_txdesc[i]; 3826 if (txd->tx_m != NULL) { 3827 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 3828 txd->tx_dmamap); 3829 m_freem(txd->tx_m); 3830 txd->tx_m = NULL; 3831 } 3832 } 3833 3834 /* 3835 * Mark the interface down. 3836 */ 3837 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3838 sc_if->msk_link = 0; 3839 } 3840 3841 static int 3842 mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS) 3843 { 3844 return sysctl_int_range(oidp, arg1, arg2, req, 3845 MSK_PROC_MIN, MSK_PROC_MAX); 3846 } 3847 3848 static int 3849 mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS) 3850 { 3851 struct msk_softc *sc = arg1; 3852 struct lwkt_serialize *serializer = &sc->msk_serializer; 3853 int error = 0, v; 3854 3855 lwkt_serialize_enter(serializer); 3856 3857 v = sc->msk_intr_rate; 3858 error = sysctl_handle_int(oidp, &v, 0, req); 3859 if (error || req->newptr == NULL) 3860 goto back; 3861 if (v < 0) { 3862 error = EINVAL; 3863 goto back; 3864 } 3865 3866 if (sc->msk_intr_rate != v) { 3867 int flag = 0, i; 3868 3869 sc->msk_intr_rate = v; 3870 for (i = 0; i < 2; ++i) { 3871 if (sc->msk_if[i] != NULL) { 3872 flag |= sc->msk_if[i]-> 3873 arpcom.ac_if.if_flags & IFF_RUNNING; 3874 } 3875 } 3876 if (flag) 3877 mskc_set_imtimer(sc); 3878 } 3879 back: 3880 lwkt_serialize_exit(serializer); 3881 return error; 3882 } 3883 3884 static int 3885 msk_dmamem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag, 3886 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap) 3887 { 3888 struct msk_if_softc *sc_if = device_get_softc(dev); 3889 bus_dmamem_t dmem; 3890 int error; 3891 3892 error = bus_dmamem_coherent(sc_if->msk_cdata.msk_parent_tag, 3893 MSK_RING_ALIGN, 0, 3894 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3895 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3896 if (error) { 3897 device_printf(dev, "can't create coherent DMA memory\n"); 3898 return error; 3899 } 3900 3901 *dtag = dmem.dmem_tag; 3902 *dmap = dmem.dmem_map; 3903 *addr = dmem.dmem_addr; 3904 *paddr = dmem.dmem_busaddr; 3905 3906 return 0; 3907 } 3908 3909 static void 3910 msk_dmamem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 3911 { 3912 if (dtag != NULL) { 3913 bus_dmamap_unload(dtag, dmap); 3914 bus_dmamem_free(dtag, addr, dmap); 3915 bus_dma_tag_destroy(dtag); 3916 } 3917 } 3918 3919 static void 3920 mskc_set_imtimer(struct msk_softc *sc) 3921 { 3922 if (sc->msk_intr_rate > 0) { 3923 /* 3924 * XXX myk(4) seems to use 125MHz for EC/FE/XL 3925 * and 78.125MHz for rest of chip types 3926 */ 3927 CSR_WRITE_4(sc, B2_IRQM_INI, 3928 MSK_USECS(sc, 1000000 / sc->msk_intr_rate)); 3929 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3930 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_START); 3931 } else { 3932 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_STOP); 3933 } 3934 } 3935