1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* $FreeBSD: src/sys/dev/msk/if_msk.c,v 1.26 2007/12/05 09:41:58 remko Exp $ */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/param.h> 104 #include <sys/endian.h> 105 #include <sys/kernel.h> 106 #include <sys/bus.h> 107 #include <sys/in_cksum.h> 108 #include <sys/interrupt.h> 109 #include <sys/malloc.h> 110 #include <sys/proc.h> 111 #include <sys/rman.h> 112 #include <sys/serialize.h> 113 #include <sys/socket.h> 114 #include <sys/sockio.h> 115 #include <sys/sysctl.h> 116 117 #include <net/ethernet.h> 118 #include <net/if.h> 119 #include <net/bpf.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/ifq_var.h> 124 #include <net/vlan/if_vlan_var.h> 125 126 #include <netinet/ip.h> 127 #include <netinet/ip_var.h> 128 129 #include <dev/netif/mii_layer/miivar.h> 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 #include "if_mskreg.h" 135 136 /* "device miibus" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Devices supported by this driver. 143 */ 144 static const struct msk_product { 145 uint16_t msk_vendorid; 146 uint16_t msk_deviceid; 147 const char *msk_name; 148 } msk_products[] = { 149 { VENDORID_SK, DEVICEID_SK_YUKON2, 150 "SK-9Sxx Gigabit Ethernet" }, 151 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 152 "SK-9Exx Gigabit Ethernet"}, 153 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 154 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 155 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 156 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 157 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 158 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 159 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 160 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 161 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 162 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 163 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 164 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 165 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 166 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 167 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 168 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 169 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 170 "Marvell Yukon 88E8035 Fast Ethernet" }, 171 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 172 "Marvell Yukon 88E8036 Fast Ethernet" }, 173 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 174 "Marvell Yukon 88E8038 Fast Ethernet" }, 175 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 176 "Marvell Yukon 88E8039 Fast Ethernet" }, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 178 "Marvell Yukon 88E8040 Fast Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 180 "Marvell Yukon 88E8040T Fast Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 182 "Marvell Yukon 88E8042 Fast Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 184 "Marvell Yukon 88E8048 Fast Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 186 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 188 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 190 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 192 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 194 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 196 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 198 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 200 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 202 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 204 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 206 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 208 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 210 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 211 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 212 "D-Link 550SX Gigabit Ethernet" }, 213 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 214 "D-Link 560T Gigabit Ethernet" }, 215 { 0, 0, NULL } 216 }; 217 218 static const char *model_name[] = { 219 "Yukon XL", 220 "Yukon EC Ultra", 221 "Yukon EX", 222 "Yukon EC", 223 "Yukon FE", 224 "Yukon FE+", 225 "Yukon Supreme", 226 "Yukon Ultra 2", 227 "Yukon Unknown", 228 "Yukon Optima" 229 }; 230 231 static int mskc_probe(device_t); 232 static int mskc_attach(device_t); 233 static int mskc_detach(device_t); 234 static int mskc_shutdown(device_t); 235 static int mskc_suspend(device_t); 236 static int mskc_resume(device_t); 237 static void mskc_intr(void *); 238 239 static void mskc_reset(struct msk_softc *); 240 static void mskc_set_imtimer(struct msk_softc *); 241 static void mskc_intr_hwerr(struct msk_softc *); 242 static int mskc_handle_events(struct msk_softc *); 243 static void mskc_phy_power(struct msk_softc *, int); 244 static int mskc_setup_rambuffer(struct msk_softc *); 245 static int mskc_status_dma_alloc(struct msk_softc *); 246 static void mskc_status_dma_free(struct msk_softc *); 247 static int mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS); 248 static int mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS); 249 250 static int msk_probe(device_t); 251 static int msk_attach(device_t); 252 static int msk_detach(device_t); 253 static int msk_miibus_readreg(device_t, int, int); 254 static int msk_miibus_writereg(device_t, int, int, int); 255 static void msk_miibus_statchg(device_t); 256 257 static void msk_init(void *); 258 static int msk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 259 static void msk_start(struct ifnet *, struct ifaltq_subque *); 260 static void msk_watchdog(struct ifnet *); 261 static int msk_mediachange(struct ifnet *); 262 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 263 264 static void msk_tick(void *); 265 static void msk_intr_phy(struct msk_if_softc *); 266 static void msk_intr_gmac(struct msk_if_softc *); 267 static __inline void 268 msk_rxput(struct msk_if_softc *); 269 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 270 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 271 static void msk_txeof(struct msk_if_softc *, int); 272 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 273 static void msk_set_rambuffer(struct msk_if_softc *); 274 static void msk_stop(struct msk_if_softc *); 275 276 static int msk_txrx_dma_alloc(struct msk_if_softc *); 277 static void msk_txrx_dma_free(struct msk_if_softc *); 278 static int msk_init_rx_ring(struct msk_if_softc *); 279 static void msk_init_tx_ring(struct msk_if_softc *); 280 static __inline void 281 msk_discard_rxbuf(struct msk_if_softc *, int); 282 static int msk_newbuf(struct msk_if_softc *, int, int); 283 static int msk_encap(struct msk_if_softc *, struct mbuf **); 284 285 #ifdef MSK_JUMBO 286 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 287 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 288 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 289 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 290 static void *msk_jalloc(struct msk_if_softc *); 291 static void msk_jfree(void *, void *); 292 #endif 293 294 static int msk_phy_readreg(struct msk_if_softc *, int, int); 295 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 296 297 static void msk_rxfilter(struct msk_if_softc *); 298 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 299 static void msk_set_tx_stfwd(struct msk_if_softc *); 300 301 static int msk_dmamem_create(device_t, bus_size_t, bus_dma_tag_t *, 302 void **, bus_addr_t *, bus_dmamap_t *); 303 static void msk_dmamem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 304 305 static device_method_t mskc_methods[] = { 306 /* Device interface */ 307 DEVMETHOD(device_probe, mskc_probe), 308 DEVMETHOD(device_attach, mskc_attach), 309 DEVMETHOD(device_detach, mskc_detach), 310 DEVMETHOD(device_suspend, mskc_suspend), 311 DEVMETHOD(device_resume, mskc_resume), 312 DEVMETHOD(device_shutdown, mskc_shutdown), 313 314 /* bus interface */ 315 DEVMETHOD(bus_print_child, bus_generic_print_child), 316 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 317 318 { NULL, NULL } 319 }; 320 321 static DEFINE_CLASS_0(mskc, mskc_driver, mskc_methods, sizeof(struct msk_softc)); 322 static devclass_t mskc_devclass; 323 324 static device_method_t msk_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, msk_probe), 327 DEVMETHOD(device_attach, msk_attach), 328 DEVMETHOD(device_detach, msk_detach), 329 DEVMETHOD(device_shutdown, bus_generic_shutdown), 330 331 /* bus interface */ 332 DEVMETHOD(bus_print_child, bus_generic_print_child), 333 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 334 335 /* MII interface */ 336 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 337 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 338 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 339 340 { NULL, NULL } 341 }; 342 343 static DEFINE_CLASS_0(msk, msk_driver, msk_methods, sizeof(struct msk_if_softc)); 344 static devclass_t msk_devclass; 345 346 DECLARE_DUMMY_MODULE(if_msk); 347 DRIVER_MODULE(if_msk, pci, mskc_driver, mskc_devclass, NULL, NULL); 348 DRIVER_MODULE(if_msk, mskc, msk_driver, msk_devclass, NULL, NULL); 349 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL); 350 351 static int mskc_intr_rate = 0; 352 static int mskc_process_limit = MSK_PROC_DEFAULT; 353 354 TUNABLE_INT("hw.mskc.intr_rate", &mskc_intr_rate); 355 TUNABLE_INT("hw.mskc.process_limit", &mskc_process_limit); 356 357 static int 358 msk_miibus_readreg(device_t dev, int phy, int reg) 359 { 360 struct msk_if_softc *sc_if; 361 362 if (phy != PHY_ADDR_MARV) 363 return (0); 364 365 sc_if = device_get_softc(dev); 366 367 return (msk_phy_readreg(sc_if, phy, reg)); 368 } 369 370 static int 371 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 372 { 373 struct msk_softc *sc; 374 int i, val; 375 376 sc = sc_if->msk_softc; 377 378 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 379 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 380 381 for (i = 0; i < MSK_TIMEOUT; i++) { 382 DELAY(1); 383 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 384 if ((val & GM_SMI_CT_RD_VAL) != 0) { 385 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 386 break; 387 } 388 } 389 390 if (i == MSK_TIMEOUT) { 391 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 392 val = 0; 393 } 394 395 return (val); 396 } 397 398 static int 399 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 400 { 401 struct msk_if_softc *sc_if; 402 403 if (phy != PHY_ADDR_MARV) 404 return (0); 405 406 sc_if = device_get_softc(dev); 407 408 return (msk_phy_writereg(sc_if, phy, reg, val)); 409 } 410 411 static int 412 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 413 { 414 struct msk_softc *sc; 415 int i; 416 417 sc = sc_if->msk_softc; 418 419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 420 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 421 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 422 for (i = 0; i < MSK_TIMEOUT; i++) { 423 DELAY(1); 424 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 425 GM_SMI_CT_BUSY) == 0) 426 break; 427 } 428 if (i == MSK_TIMEOUT) 429 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 430 431 return (0); 432 } 433 434 static void 435 msk_miibus_statchg(device_t dev) 436 { 437 struct msk_if_softc *sc_if; 438 struct msk_softc *sc; 439 struct mii_data *mii; 440 uint32_t gmac; 441 442 sc_if = device_get_softc(dev); 443 sc = sc_if->msk_softc; 444 445 mii = device_get_softc(sc_if->msk_miibus); 446 447 sc_if->msk_link = 0; 448 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 449 (IFM_AVALID | IFM_ACTIVE)) { 450 switch (IFM_SUBTYPE(mii->mii_media_active)) { 451 case IFM_10_T: 452 case IFM_100_TX: 453 sc_if->msk_link = 1; 454 break; 455 case IFM_1000_T: 456 case IFM_1000_SX: 457 case IFM_1000_LX: 458 case IFM_1000_CX: 459 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 460 sc_if->msk_link = 1; 461 break; 462 } 463 } 464 465 if (sc_if->msk_link != 0) { 466 /* Enable Tx FIFO Underrun. */ 467 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 468 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 469 /* 470 * Because mii(4) notify msk(4) that it detected link status 471 * change, there is no need to enable automatic 472 * speed/flow-control/duplex updates. 473 */ 474 gmac = GM_GPCR_AU_ALL_DIS; 475 switch (IFM_SUBTYPE(mii->mii_media_active)) { 476 case IFM_1000_SX: 477 case IFM_1000_T: 478 gmac |= GM_GPCR_SPEED_1000; 479 break; 480 case IFM_100_TX: 481 gmac |= GM_GPCR_SPEED_100; 482 break; 483 case IFM_10_T: 484 break; 485 } 486 487 if ((mii->mii_media_active & IFM_GMASK) & IFM_FDX) 488 gmac |= GM_GPCR_DUP_FULL; 489 else 490 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 491 /* Disable Rx flow control. */ 492 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 493 gmac |= GM_GPCR_FC_RX_DIS; 494 /* Disable Tx flow control. */ 495 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 496 gmac |= GM_GPCR_FC_TX_DIS; 497 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 498 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 499 /* Read again to ensure writing. */ 500 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 501 502 gmac = GMC_PAUSE_OFF; 503 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) && 504 ((mii->mii_media_active & IFM_GMASK) & IFM_FDX)) 505 gmac = GMC_PAUSE_ON; 506 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 507 508 /* Enable PHY interrupt for FIFO underrun/overflow. */ 509 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 510 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 511 } else { 512 /* 513 * Link state changed to down. 514 * Disable PHY interrupts. 515 */ 516 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 517 /* Disable Rx/Tx MAC. */ 518 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 519 if (gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) { 520 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 521 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 522 /* Read again to ensure writing. */ 523 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 524 } 525 } 526 } 527 528 static void 529 msk_rxfilter(struct msk_if_softc *sc_if) 530 { 531 struct msk_softc *sc; 532 struct ifnet *ifp; 533 struct ifmultiaddr *ifma; 534 uint32_t mchash[2]; 535 uint32_t crc; 536 uint16_t mode; 537 538 sc = sc_if->msk_softc; 539 ifp = sc_if->msk_ifp; 540 541 bzero(mchash, sizeof(mchash)); 542 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 543 if ((ifp->if_flags & IFF_PROMISC) != 0) { 544 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 545 } else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 546 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 547 mchash[0] = 0xffff; 548 mchash[1] = 0xffff; 549 } else { 550 mode |= GM_RXCR_UCF_ENA; 551 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 552 if (ifma->ifma_addr->sa_family != AF_LINK) 553 continue; 554 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 555 ifma->ifma_addr), ETHER_ADDR_LEN); 556 /* Just want the 6 least significant bits. */ 557 crc &= 0x3f; 558 /* Set the corresponding bit in the hash table. */ 559 mchash[crc >> 5] |= 1 << (crc & 0x1f); 560 } 561 if (mchash[0] != 0 || mchash[1] != 0) 562 mode |= GM_RXCR_MCF_ENA; 563 } 564 565 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 566 mchash[0] & 0xffff); 567 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 568 (mchash[0] >> 16) & 0xffff); 569 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 570 mchash[1] & 0xffff); 571 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 572 (mchash[1] >> 16) & 0xffff); 573 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 574 } 575 576 static void 577 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 578 { 579 struct msk_softc *sc; 580 581 sc = sc_if->msk_softc; 582 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 583 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 584 RX_VLAN_STRIP_ON); 585 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 586 TX_VLAN_TAG_ON); 587 } else { 588 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 589 RX_VLAN_STRIP_OFF); 590 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 591 TX_VLAN_TAG_OFF); 592 } 593 } 594 595 static int 596 msk_init_rx_ring(struct msk_if_softc *sc_if) 597 { 598 struct msk_ring_data *rd; 599 struct msk_rxdesc *rxd; 600 int i, prod; 601 602 sc_if->msk_cdata.msk_rx_cons = 0; 603 sc_if->msk_cdata.msk_rx_prod = 0; 604 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 605 606 rd = &sc_if->msk_rdata; 607 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 608 prod = sc_if->msk_cdata.msk_rx_prod; 609 for (i = 0; i < MSK_RX_RING_CNT; i++) { 610 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 611 rxd->rx_m = NULL; 612 rxd->rx_le = &rd->msk_rx_ring[prod]; 613 if (msk_newbuf(sc_if, prod, 1) != 0) 614 return (ENOBUFS); 615 MSK_INC(prod, MSK_RX_RING_CNT); 616 } 617 618 /* Update prefetch unit. */ 619 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 620 CSR_WRITE_2(sc_if->msk_softc, 621 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 622 sc_if->msk_cdata.msk_rx_prod); 623 624 return (0); 625 } 626 627 #ifdef MSK_JUMBO 628 static int 629 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 630 { 631 struct msk_ring_data *rd; 632 struct msk_rxdesc *rxd; 633 int i, prod; 634 635 MSK_IF_LOCK_ASSERT(sc_if); 636 637 sc_if->msk_cdata.msk_rx_cons = 0; 638 sc_if->msk_cdata.msk_rx_prod = 0; 639 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 640 641 rd = &sc_if->msk_rdata; 642 bzero(rd->msk_jumbo_rx_ring, 643 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 644 prod = sc_if->msk_cdata.msk_rx_prod; 645 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 646 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 647 rxd->rx_m = NULL; 648 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 649 if (msk_jumbo_newbuf(sc_if, prod) != 0) 650 return (ENOBUFS); 651 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 652 } 653 654 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 655 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 656 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 657 658 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 659 CSR_WRITE_2(sc_if->msk_softc, 660 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 661 sc_if->msk_cdata.msk_rx_prod); 662 663 return (0); 664 } 665 #endif 666 667 static void 668 msk_init_tx_ring(struct msk_if_softc *sc_if) 669 { 670 struct msk_ring_data *rd; 671 struct msk_txdesc *txd; 672 int i; 673 674 sc_if->msk_cdata.msk_tx_prod = 0; 675 sc_if->msk_cdata.msk_tx_cons = 0; 676 sc_if->msk_cdata.msk_tx_cnt = 0; 677 678 rd = &sc_if->msk_rdata; 679 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 680 for (i = 0; i < MSK_TX_RING_CNT; i++) { 681 txd = &sc_if->msk_cdata.msk_txdesc[i]; 682 txd->tx_m = NULL; 683 txd->tx_le = &rd->msk_tx_ring[i]; 684 } 685 } 686 687 static __inline void 688 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 689 { 690 struct msk_rx_desc *rx_le; 691 struct msk_rxdesc *rxd; 692 struct mbuf *m; 693 694 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 695 m = rxd->rx_m; 696 rx_le = rxd->rx_le; 697 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 698 } 699 700 #ifdef MSK_JUMBO 701 static __inline void 702 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 703 { 704 struct msk_rx_desc *rx_le; 705 struct msk_rxdesc *rxd; 706 struct mbuf *m; 707 708 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 709 m = rxd->rx_m; 710 rx_le = rxd->rx_le; 711 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 712 } 713 #endif 714 715 static int 716 msk_newbuf(struct msk_if_softc *sc_if, int idx, int init) 717 { 718 struct msk_rx_desc *rx_le; 719 struct msk_rxdesc *rxd; 720 struct mbuf *m; 721 bus_dma_segment_t seg; 722 bus_dmamap_t map; 723 int error, nseg; 724 725 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 726 if (m == NULL) 727 return (ENOBUFS); 728 729 m->m_len = m->m_pkthdr.len = MCLBYTES; 730 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 731 m_adj(m, ETHER_ALIGN); 732 733 error = bus_dmamap_load_mbuf_segment(sc_if->msk_cdata.msk_rx_tag, 734 sc_if->msk_cdata.msk_rx_sparemap, 735 m, &seg, 1, &nseg, BUS_DMA_NOWAIT); 736 if (error) { 737 m_freem(m); 738 if (init) 739 if_printf(&sc_if->arpcom.ac_if, "can't load RX mbuf\n"); 740 return (error); 741 } 742 743 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 744 if (rxd->rx_m != NULL) { 745 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 746 BUS_DMASYNC_POSTREAD); 747 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 748 } 749 750 map = rxd->rx_dmamap; 751 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 752 sc_if->msk_cdata.msk_rx_sparemap = map; 753 754 rxd->rx_m = m; 755 rx_le = rxd->rx_le; 756 rx_le->msk_addr = htole32(MSK_ADDR_LO(seg.ds_addr)); 757 rx_le->msk_control = htole32(seg.ds_len | OP_PACKET | HW_OWNER); 758 759 return (0); 760 } 761 762 #ifdef MSK_JUMBO 763 static int 764 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 765 { 766 struct msk_rx_desc *rx_le; 767 struct msk_rxdesc *rxd; 768 struct mbuf *m; 769 bus_dma_segment_t segs[1]; 770 bus_dmamap_t map; 771 int nsegs; 772 void *buf; 773 774 MGETHDR(m, MB_DONTWAIT, MT_DATA); 775 if (m == NULL) 776 return (ENOBUFS); 777 buf = msk_jalloc(sc_if); 778 if (buf == NULL) { 779 m_freem(m); 780 return (ENOBUFS); 781 } 782 /* Attach the buffer to the mbuf. */ 783 MEXTADD(m, buf, MSK_JLEN, msk_jfree, sc_if, 0, EXT_NET_DRV); 784 if ((m->m_flags & M_EXT) == 0) { 785 m_freem(m); 786 return (ENOBUFS); 787 } 788 m->m_pkthdr.len = m->m_len = MSK_JLEN; 789 m_adj(m, ETHER_ALIGN); 790 791 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 792 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 793 BUS_DMA_NOWAIT) != 0) { 794 m_freem(m); 795 return (ENOBUFS); 796 } 797 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 798 799 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 800 if (rxd->rx_m != NULL) { 801 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 802 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 803 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 804 rxd->rx_dmamap); 805 } 806 map = rxd->rx_dmamap; 807 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 808 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 809 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 810 BUS_DMASYNC_PREREAD); 811 rxd->rx_m = m; 812 rx_le = rxd->rx_le; 813 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 814 rx_le->msk_control = 815 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 816 817 return (0); 818 } 819 #endif 820 821 /* 822 * Set media options. 823 */ 824 static int 825 msk_mediachange(struct ifnet *ifp) 826 { 827 struct msk_if_softc *sc_if = ifp->if_softc; 828 struct mii_data *mii; 829 int error; 830 831 mii = device_get_softc(sc_if->msk_miibus); 832 error = mii_mediachg(mii); 833 834 return (error); 835 } 836 837 /* 838 * Report current media status. 839 */ 840 static void 841 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 842 { 843 struct msk_if_softc *sc_if = ifp->if_softc; 844 struct mii_data *mii; 845 846 mii = device_get_softc(sc_if->msk_miibus); 847 mii_pollstat(mii); 848 849 ifmr->ifm_active = mii->mii_media_active; 850 ifmr->ifm_status = mii->mii_media_status; 851 } 852 853 static int 854 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 855 { 856 struct msk_if_softc *sc_if; 857 struct ifreq *ifr; 858 struct mii_data *mii; 859 int error, mask; 860 861 sc_if = ifp->if_softc; 862 ifr = (struct ifreq *)data; 863 error = 0; 864 865 switch(command) { 866 case SIOCSIFMTU: 867 #ifdef MSK_JUMBO 868 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 869 error = EINVAL; 870 break; 871 } 872 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 873 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 874 error = EINVAL; 875 break; 876 } 877 ifp->if_mtu = ifr->ifr_mtu; 878 if ((ifp->if_flags & IFF_RUNNING) != 0) 879 msk_init(sc_if); 880 #else 881 error = EOPNOTSUPP; 882 #endif 883 break; 884 885 case SIOCSIFFLAGS: 886 if (ifp->if_flags & IFF_UP) { 887 if (ifp->if_flags & IFF_RUNNING) { 888 if (((ifp->if_flags ^ sc_if->msk_if_flags) 889 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 890 msk_rxfilter(sc_if); 891 } else { 892 if (sc_if->msk_detach == 0) 893 msk_init(sc_if); 894 } 895 } else { 896 if (ifp->if_flags & IFF_RUNNING) 897 msk_stop(sc_if); 898 } 899 sc_if->msk_if_flags = ifp->if_flags; 900 break; 901 902 case SIOCADDMULTI: 903 case SIOCDELMULTI: 904 if (ifp->if_flags & IFF_RUNNING) 905 msk_rxfilter(sc_if); 906 break; 907 908 case SIOCGIFMEDIA: 909 case SIOCSIFMEDIA: 910 mii = device_get_softc(sc_if->msk_miibus); 911 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 912 break; 913 914 case SIOCSIFCAP: 915 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 916 if ((mask & IFCAP_TXCSUM) != 0) { 917 ifp->if_capenable ^= IFCAP_TXCSUM; 918 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 919 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 920 ifp->if_hwassist |= MSK_CSUM_FEATURES; 921 else 922 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 923 } 924 #ifdef notyet 925 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 926 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 927 msk_setvlan(sc_if, ifp); 928 } 929 #endif 930 931 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 932 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 933 /* 934 * In Yukon EC Ultra, TSO & checksum offload is not 935 * supported for jumbo frame. 936 */ 937 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 938 ifp->if_capenable &= ~IFCAP_TXCSUM; 939 } 940 break; 941 942 default: 943 error = ether_ioctl(ifp, command, data); 944 break; 945 } 946 947 return (error); 948 } 949 950 static int 951 mskc_probe(device_t dev) 952 { 953 const struct msk_product *mp; 954 uint16_t vendor, devid; 955 956 vendor = pci_get_vendor(dev); 957 devid = pci_get_device(dev); 958 for (mp = msk_products; mp->msk_name != NULL; ++mp) { 959 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 960 device_set_desc(dev, mp->msk_name); 961 return (0); 962 } 963 } 964 return (ENXIO); 965 } 966 967 static int 968 mskc_setup_rambuffer(struct msk_softc *sc) 969 { 970 int next; 971 int i; 972 973 /* Get adapter SRAM size. */ 974 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 975 if (bootverbose) { 976 device_printf(sc->msk_dev, 977 "RAM buffer size : %dKB\n", sc->msk_ramsize); 978 } 979 if (sc->msk_ramsize == 0) 980 return (0); 981 sc->msk_pflags |= MSK_FLAG_RAMBUF; 982 983 /* 984 * Give receiver 2/3 of memory and round down to the multiple 985 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 986 * of 1024. 987 */ 988 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 989 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 990 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 991 sc->msk_rxqstart[i] = next; 992 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 993 next = sc->msk_rxqend[i] + 1; 994 sc->msk_txqstart[i] = next; 995 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 996 next = sc->msk_txqend[i] + 1; 997 if (bootverbose) { 998 device_printf(sc->msk_dev, 999 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1000 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1001 sc->msk_rxqend[i]); 1002 device_printf(sc->msk_dev, 1003 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1004 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1005 sc->msk_txqend[i]); 1006 } 1007 } 1008 1009 return (0); 1010 } 1011 1012 static void 1013 mskc_phy_power(struct msk_softc *sc, int mode) 1014 { 1015 uint32_t our, val; 1016 int i; 1017 1018 switch (mode) { 1019 case MSK_PHY_POWERUP: 1020 /* Switch power to VCC (WA for VAUX problem). */ 1021 CSR_WRITE_1(sc, B0_POWER_CTRL, 1022 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1023 /* Disable Core Clock Division, set Clock Select to 0. */ 1024 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1025 1026 val = 0; 1027 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1028 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1029 /* Enable bits are inverted. */ 1030 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1031 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1032 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1033 } 1034 /* 1035 * Enable PCI & Core Clock, enable clock gating for both Links. 1036 */ 1037 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1038 1039 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1040 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1041 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1042 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1043 /* Deassert Low Power for 1st PHY. */ 1044 our |= PCI_Y2_PHY1_COMA; 1045 if (sc->msk_num_port > 1) 1046 our |= PCI_Y2_PHY2_COMA; 1047 } 1048 } 1049 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1050 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1051 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1052 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1053 val &= (PCI_FORCE_ASPM_REQUEST | 1054 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1055 PCI_ASPM_CLKRUN_REQUEST); 1056 /* Set all bits to 0 except bits 15..12. */ 1057 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1058 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1059 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1060 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1061 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1062 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1063 /* 1064 * Disable status race, workaround for 1065 * Yukon EC Ultra & Yukon EX. 1066 */ 1067 val = CSR_READ_4(sc, B2_GP_IO); 1068 val |= GLB_GPIO_STAT_RACE_DIS; 1069 CSR_WRITE_4(sc, B2_GP_IO, val); 1070 CSR_READ_4(sc, B2_GP_IO); 1071 } 1072 /* Release PHY from PowerDown/COMA mode. */ 1073 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1074 1075 for (i = 0; i < sc->msk_num_port; i++) { 1076 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1077 GMLC_RST_SET); 1078 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1079 GMLC_RST_CLR); 1080 } 1081 break; 1082 case MSK_PHY_POWERDOWN: 1083 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1084 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1085 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1086 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1087 val &= ~PCI_Y2_PHY1_COMA; 1088 if (sc->msk_num_port > 1) 1089 val &= ~PCI_Y2_PHY2_COMA; 1090 } 1091 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1092 1093 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1094 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1095 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1096 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1097 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1098 /* Enable bits are inverted. */ 1099 val = 0; 1100 } 1101 /* 1102 * Disable PCI & Core Clock, disable clock gating for 1103 * both Links. 1104 */ 1105 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1106 CSR_WRITE_1(sc, B0_POWER_CTRL, 1107 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1108 break; 1109 default: 1110 break; 1111 } 1112 } 1113 1114 static void 1115 mskc_reset(struct msk_softc *sc) 1116 { 1117 bus_addr_t addr; 1118 uint16_t status; 1119 uint32_t val; 1120 int i; 1121 1122 /* Disable ASF. */ 1123 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1124 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1125 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1126 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1127 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1128 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1129 /* Clear AHB bridge & microcontroller reset. */ 1130 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1131 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1132 /* Clear ASF microcontroller state. */ 1133 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1134 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1135 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1136 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1137 } else { 1138 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1139 } 1140 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1141 /* 1142 * Since we disabled ASF, S/W reset is required for 1143 * Power Management. 1144 */ 1145 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1146 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1147 } 1148 1149 /* Clear all error bits in the PCI status register. */ 1150 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1151 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1152 1153 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1154 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1155 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1156 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1157 1158 switch (sc->msk_bustype) { 1159 case MSK_PEX_BUS: 1160 /* Clear all PEX errors. */ 1161 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1162 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1163 if ((val & PEX_RX_OV) != 0) { 1164 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1165 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1166 } 1167 break; 1168 case MSK_PCI_BUS: 1169 case MSK_PCIX_BUS: 1170 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1171 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1172 if (val == 0) 1173 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1174 if (sc->msk_bustype == MSK_PCIX_BUS) { 1175 /* Set Cache Line Size opt. */ 1176 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1177 val |= PCI_CLS_OPT; 1178 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1179 } 1180 break; 1181 } 1182 /* Set PHY power state. */ 1183 mskc_phy_power(sc, MSK_PHY_POWERUP); 1184 1185 /* Reset GPHY/GMAC Control */ 1186 for (i = 0; i < sc->msk_num_port; i++) { 1187 /* GPHY Control reset. */ 1188 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1189 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1190 /* GMAC Control reset. */ 1191 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1192 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1193 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1194 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1195 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1196 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1197 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1198 GMC_BYP_RETR_ON); 1199 } 1200 } 1201 1202 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1203 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1204 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1205 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1206 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1207 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1208 } 1209 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1210 1211 /* LED On. */ 1212 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1213 1214 /* Clear TWSI IRQ. */ 1215 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1216 1217 /* Turn off hardware timer. */ 1218 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1219 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1220 1221 /* Turn off descriptor polling. */ 1222 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1223 1224 /* Turn off time stamps. */ 1225 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1226 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1227 1228 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1229 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1230 sc->msk_hw_id == CHIP_ID_YUKON_FE) { 1231 /* Configure timeout values. */ 1232 for (i = 0; i < sc->msk_num_port; i++) { 1233 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), 1234 RI_RST_SET); 1235 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), 1236 RI_RST_CLR); 1237 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1238 MSK_RI_TO_53); 1239 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1240 MSK_RI_TO_53); 1241 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1242 MSK_RI_TO_53); 1243 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1244 MSK_RI_TO_53); 1245 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1246 MSK_RI_TO_53); 1247 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1248 MSK_RI_TO_53); 1249 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1250 MSK_RI_TO_53); 1251 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1252 MSK_RI_TO_53); 1253 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1254 MSK_RI_TO_53); 1255 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1256 MSK_RI_TO_53); 1257 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1258 MSK_RI_TO_53); 1259 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1260 MSK_RI_TO_53); 1261 } 1262 } 1263 1264 /* Disable all interrupts. */ 1265 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1266 CSR_READ_4(sc, B0_HWE_IMSK); 1267 CSR_WRITE_4(sc, B0_IMSK, 0); 1268 CSR_READ_4(sc, B0_IMSK); 1269 1270 /* 1271 * On dual port PCI-X card, there is an problem where status 1272 * can be received out of order due to split transactions. 1273 */ 1274 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1275 uint16_t pcix_cmd; 1276 1277 pcix_cmd = pci_read_config(sc->msk_dev, 1278 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1279 /* Clear Max Outstanding Split Transactions. */ 1280 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1281 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1282 pci_write_config(sc->msk_dev, 1283 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1284 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1285 } 1286 if (sc->msk_pciecap != 0) { 1287 /* Change Max. Read Request Size to 2048 bytes. */ 1288 if (pcie_get_max_readrq(sc->msk_dev) == 1289 PCIEM_DEVCTL_MAX_READRQ_512) { 1290 pcie_set_max_readrq(sc->msk_dev, 1291 PCIEM_DEVCTL_MAX_READRQ_2048); 1292 } 1293 } 1294 1295 /* Clear status list. */ 1296 bzero(sc->msk_stat_ring, 1297 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1298 sc->msk_stat_cons = 0; 1299 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1300 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1301 /* Set the status list base address. */ 1302 addr = sc->msk_stat_ring_paddr; 1303 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1304 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1305 /* Set the status list last index. */ 1306 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1307 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1308 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1309 /* WA for dev. #4.3 */ 1310 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1311 /* WA for dev. #4.18 */ 1312 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1313 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1314 } else { 1315 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1316 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1317 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1318 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1319 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1320 else 1321 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1322 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1323 } 1324 /* 1325 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1326 */ 1327 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1328 1329 /* Enable status unit. */ 1330 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1331 1332 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1333 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1334 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1335 } 1336 1337 static int 1338 msk_probe(device_t dev) 1339 { 1340 struct msk_softc *sc = device_get_softc(device_get_parent(dev)); 1341 char desc[100]; 1342 1343 /* 1344 * Not much to do here. We always know there will be 1345 * at least one GMAC present, and if there are two, 1346 * mskc_attach() will create a second device instance 1347 * for us. 1348 */ 1349 ksnprintf(desc, sizeof(desc), 1350 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1351 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1352 sc->msk_hw_rev); 1353 device_set_desc_copy(dev, desc); 1354 1355 return (0); 1356 } 1357 1358 static int 1359 msk_attach(device_t dev) 1360 { 1361 struct msk_softc *sc = device_get_softc(device_get_parent(dev)); 1362 struct msk_if_softc *sc_if = device_get_softc(dev); 1363 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1364 int i, port, error; 1365 uint8_t eaddr[ETHER_ADDR_LEN]; 1366 1367 port = *(int *)device_get_ivars(dev); 1368 KKASSERT(port == MSK_PORT_A || port == MSK_PORT_B); 1369 1370 kfree(device_get_ivars(dev), M_DEVBUF); 1371 device_set_ivars(dev, NULL); 1372 1373 callout_init(&sc_if->msk_tick_ch); 1374 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1375 1376 sc_if->msk_if_dev = dev; 1377 sc_if->msk_port = port; 1378 sc_if->msk_softc = sc; 1379 sc_if->msk_ifp = ifp; 1380 sc_if->msk_flags = sc->msk_pflags; 1381 sc->msk_if[port] = sc_if; 1382 1383 /* Setup Tx/Rx queue register offsets. */ 1384 if (port == MSK_PORT_A) { 1385 sc_if->msk_txq = Q_XA1; 1386 sc_if->msk_txsq = Q_XS1; 1387 sc_if->msk_rxq = Q_R1; 1388 } else { 1389 sc_if->msk_txq = Q_XA2; 1390 sc_if->msk_txsq = Q_XS2; 1391 sc_if->msk_rxq = Q_R2; 1392 } 1393 1394 error = msk_txrx_dma_alloc(sc_if); 1395 if (error) 1396 goto fail; 1397 1398 ifp->if_softc = sc_if; 1399 ifp->if_mtu = ETHERMTU; 1400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1401 ifp->if_init = msk_init; 1402 ifp->if_ioctl = msk_ioctl; 1403 ifp->if_start = msk_start; 1404 ifp->if_watchdog = msk_watchdog; 1405 ifq_set_maxlen(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1406 ifq_set_ready(&ifp->if_snd); 1407 1408 #ifdef notyet 1409 /* 1410 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1411 * has serious bug in Rx checksum offload for all Yukon II family 1412 * hardware. It seems there is a workaround to make it work somtimes. 1413 * However, the workaround also have to check OP code sequences to 1414 * verify whether the OP code is correct. Sometimes it should compute 1415 * IP/TCP/UDP checksum in driver in order to verify correctness of 1416 * checksum computed by hardware. If you have to compute checksum 1417 * with software to verify the hardware's checksum why have hardware 1418 * compute the checksum? I think there is no reason to spend time to 1419 * make Rx checksum offload work on Yukon II hardware. 1420 */ 1421 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU | 1422 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1423 ifp->if_hwassist = MSK_CSUM_FEATURES; 1424 ifp->if_capenable = ifp->if_capabilities; 1425 #endif 1426 1427 /* 1428 * Get station address for this interface. Note that 1429 * dual port cards actually come with three station 1430 * addresses: one for each port, plus an extra. The 1431 * extra one is used by the SysKonnect driver software 1432 * as a 'virtual' station address for when both ports 1433 * are operating in failover mode. Currently we don't 1434 * use this extra address. 1435 */ 1436 for (i = 0; i < ETHER_ADDR_LEN; i++) 1437 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1438 1439 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN; 1440 1441 /* 1442 * Do miibus setup. 1443 */ 1444 error = mii_phy_probe(dev, &sc_if->msk_miibus, 1445 msk_mediachange, msk_mediastatus); 1446 if (error) { 1447 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1448 goto fail; 1449 } 1450 1451 /* 1452 * Call MI attach routine. Can't hold locks when calling into ether_*. 1453 */ 1454 ether_ifattach(ifp, eaddr, &sc->msk_serializer); 1455 #if 0 1456 /* 1457 * Tell the upper layer(s) we support long frames. 1458 * Must appear after the call to ether_ifattach() because 1459 * ether_ifattach() sets ifi_hdrlen to the default value. 1460 */ 1461 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1462 #endif 1463 1464 return 0; 1465 fail: 1466 msk_detach(dev); 1467 sc->msk_if[port] = NULL; 1468 return (error); 1469 } 1470 1471 /* 1472 * Attach the interface. Allocate softc structures, do ifmedia 1473 * setup and ethernet/BPF attach. 1474 */ 1475 static int 1476 mskc_attach(device_t dev) 1477 { 1478 struct msk_softc *sc; 1479 int error, *port, cpuid; 1480 1481 sc = device_get_softc(dev); 1482 sc->msk_dev = dev; 1483 lwkt_serialize_init(&sc->msk_serializer); 1484 1485 /* 1486 * Initailize sysctl variables 1487 */ 1488 sc->msk_process_limit = mskc_process_limit; 1489 sc->msk_intr_rate = mskc_intr_rate; 1490 1491 #ifndef BURN_BRIDGES 1492 /* 1493 * Handle power management nonsense. 1494 */ 1495 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1496 uint32_t irq, bar0, bar1; 1497 1498 /* Save important PCI config data. */ 1499 bar0 = pci_read_config(dev, PCIR_BAR(0), 4); 1500 bar1 = pci_read_config(dev, PCIR_BAR(1), 4); 1501 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1502 1503 /* Reset the power state. */ 1504 device_printf(dev, "chip is in D%d power mode " 1505 "-- setting to D0\n", pci_get_powerstate(dev)); 1506 1507 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1508 1509 /* Restore PCI config data. */ 1510 pci_write_config(dev, PCIR_BAR(0), bar0, 4); 1511 pci_write_config(dev, PCIR_BAR(1), bar1, 4); 1512 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1513 } 1514 #endif /* BURN_BRIDGES */ 1515 1516 /* 1517 * Map control/status registers. 1518 */ 1519 pci_enable_busmaster(dev); 1520 1521 /* 1522 * Allocate I/O resource 1523 */ 1524 #ifdef MSK_USEIOSPACE 1525 sc->msk_res_type = SYS_RES_IOPORT; 1526 sc->msk_res_rid = PCIR_BAR(1); 1527 #else 1528 sc->msk_res_type = SYS_RES_MEMORY; 1529 sc->msk_res_rid = PCIR_BAR(0); 1530 #endif 1531 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type, 1532 &sc->msk_res_rid, RF_ACTIVE); 1533 if (sc->msk_res == NULL) { 1534 if (sc->msk_res_type == SYS_RES_MEMORY) { 1535 sc->msk_res_type = SYS_RES_IOPORT; 1536 sc->msk_res_rid = PCIR_BAR(1); 1537 } else { 1538 sc->msk_res_type = SYS_RES_MEMORY; 1539 sc->msk_res_rid = PCIR_BAR(0); 1540 } 1541 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type, 1542 &sc->msk_res_rid, 1543 RF_ACTIVE); 1544 if (sc->msk_res == NULL) { 1545 device_printf(dev, "couldn't allocate %s resources\n", 1546 sc->msk_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 1547 return (ENXIO); 1548 } 1549 } 1550 sc->msk_res_bt = rman_get_bustag(sc->msk_res); 1551 sc->msk_res_bh = rman_get_bushandle(sc->msk_res); 1552 1553 /* 1554 * Allocate IRQ 1555 */ 1556 sc->msk_irq_rid = 0; 1557 sc->msk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1558 &sc->msk_irq_rid, 1559 RF_SHAREABLE | RF_ACTIVE); 1560 if (sc->msk_irq == NULL) { 1561 device_printf(dev, "couldn't allocate IRQ resources\n"); 1562 error = ENXIO; 1563 goto fail; 1564 } 1565 1566 /* Enable all clocks before accessing any registers. */ 1567 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1568 1569 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1570 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1571 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1572 /* Bail out if chip is not recognized. */ 1573 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1574 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1575 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1576 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1577 sc->msk_hw_id, sc->msk_hw_rev); 1578 error = ENXIO; 1579 goto fail; 1580 } 1581 1582 /* 1583 * Create sysctl tree 1584 */ 1585 sysctl_ctx_init(&sc->msk_sysctl_ctx); 1586 sc->msk_sysctl_tree = SYSCTL_ADD_NODE(&sc->msk_sysctl_ctx, 1587 SYSCTL_STATIC_CHILDREN(_hw), 1588 OID_AUTO, 1589 device_get_nameunit(dev), 1590 CTLFLAG_RD, 0, ""); 1591 if (sc->msk_sysctl_tree == NULL) { 1592 device_printf(dev, "can't add sysctl node\n"); 1593 error = ENXIO; 1594 goto fail; 1595 } 1596 1597 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx, 1598 SYSCTL_CHILDREN(sc->msk_sysctl_tree), 1599 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1600 &sc->msk_process_limit, 0, mskc_sysctl_proc_limit, 1601 "I", "max number of Rx events to process"); 1602 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx, 1603 SYSCTL_CHILDREN(sc->msk_sysctl_tree), 1604 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW, 1605 sc, 0, mskc_sysctl_intr_rate, 1606 "I", "max number of interrupt per second"); 1607 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1608 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1609 "defrag_avoided", CTLFLAG_RW, &sc->msk_defrag_avoided, 1610 0, "# of avoided m_defrag on TX path"); 1611 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1612 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1613 "leading_copied", CTLFLAG_RW, &sc->msk_leading_copied, 1614 0, "# of leading copies on TX path"); 1615 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx, 1616 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO, 1617 "trailing_copied", CTLFLAG_RW, &sc->msk_trailing_copied, 1618 0, "# of trailing copies on TX path"); 1619 1620 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1621 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1622 sc->msk_coppertype = 0; 1623 else 1624 sc->msk_coppertype = 1; 1625 /* Check number of MACs. */ 1626 sc->msk_num_port = 1; 1627 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1628 CFG_DUAL_MAC_MSK) { 1629 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1630 sc->msk_num_port++; 1631 } 1632 1633 /* Check bus type. */ 1634 if (pci_is_pcie(sc->msk_dev) == 0) { 1635 sc->msk_bustype = MSK_PEX_BUS; 1636 sc->msk_pciecap = pci_get_pciecap_ptr(sc->msk_dev); 1637 } else if (pci_is_pcix(sc->msk_dev) == 0) { 1638 sc->msk_bustype = MSK_PCIX_BUS; 1639 sc->msk_pcixcap = pci_get_pcixcap_ptr(sc->msk_dev); 1640 } else { 1641 sc->msk_bustype = MSK_PCI_BUS; 1642 } 1643 1644 switch (sc->msk_hw_id) { 1645 case CHIP_ID_YUKON_EC: 1646 case CHIP_ID_YUKON_EC_U: 1647 sc->msk_clock = 125; /* 125 Mhz */ 1648 break; 1649 case CHIP_ID_YUKON_EX: 1650 sc->msk_clock = 125; /* 125 Mhz */ 1651 break; 1652 case CHIP_ID_YUKON_FE: 1653 sc->msk_clock = 100; /* 100 Mhz */ 1654 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1655 break; 1656 case CHIP_ID_YUKON_FE_P: 1657 sc->msk_clock = 50; /* 50 Mhz */ 1658 /* DESCV2 */ 1659 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1660 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1661 /* 1662 * XXX 1663 * FE+ A0 has status LE writeback bug so msk(4) 1664 * does not rely on status word of received frame 1665 * in msk_rxeof() which in turn disables all 1666 * hardware assistance bits reported by the status 1667 * word as well as validity of the recevied frame. 1668 * Just pass received frames to upper stack with 1669 * minimal test and let upper stack handle them. 1670 */ 1671 sc->msk_pflags |= MSK_FLAG_NORXCHK; 1672 } 1673 break; 1674 case CHIP_ID_YUKON_XL: 1675 sc->msk_clock = 156; /* 156 Mhz */ 1676 break; 1677 case CHIP_ID_YUKON_SUPR: 1678 sc->msk_clock = 125; /* 125 MHz */ 1679 break; 1680 case CHIP_ID_YUKON_UL_2: 1681 sc->msk_clock = 125; /* 125 Mhz */ 1682 break; 1683 case CHIP_ID_YUKON_OPT: 1684 sc->msk_clock = 125; /* 125 MHz */ 1685 break; 1686 default: 1687 sc->msk_clock = 156; /* 156 Mhz */ 1688 break; 1689 } 1690 1691 error = mskc_status_dma_alloc(sc); 1692 if (error) 1693 goto fail; 1694 1695 /* Set base interrupt mask. */ 1696 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1697 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1698 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1699 1700 /* Reset the adapter. */ 1701 mskc_reset(sc); 1702 1703 error = mskc_setup_rambuffer(sc); 1704 if (error) 1705 goto fail; 1706 1707 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1708 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1709 device_printf(dev, "failed to add child for PORT_A\n"); 1710 error = ENXIO; 1711 goto fail; 1712 } 1713 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1714 *port = MSK_PORT_A; 1715 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1716 1717 if (sc->msk_num_port > 1) { 1718 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1719 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1720 device_printf(dev, "failed to add child for PORT_B\n"); 1721 error = ENXIO; 1722 goto fail; 1723 } 1724 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1725 *port = MSK_PORT_B; 1726 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1727 } 1728 1729 bus_generic_attach(dev); 1730 1731 error = bus_setup_intr(dev, sc->msk_irq, INTR_MPSAFE, 1732 mskc_intr, sc, &sc->msk_intrhand, 1733 &sc->msk_serializer); 1734 if (error) { 1735 device_printf(dev, "couldn't set up interrupt handler\n"); 1736 goto fail; 1737 } 1738 1739 cpuid = rman_get_cpuid(sc->msk_irq); 1740 if (sc->msk_if[0] != NULL) 1741 ifq_set_cpuid(&sc->msk_if[0]->msk_ifp->if_snd, cpuid); 1742 if (sc->msk_if[1] != NULL) 1743 ifq_set_cpuid(&sc->msk_if[1]->msk_ifp->if_snd, cpuid); 1744 return 0; 1745 fail: 1746 mskc_detach(dev); 1747 return (error); 1748 } 1749 1750 /* 1751 * Shutdown hardware and free up resources. This can be called any 1752 * time after the mutex has been initialized. It is called in both 1753 * the error case in attach and the normal detach case so it needs 1754 * to be careful about only freeing resources that have actually been 1755 * allocated. 1756 */ 1757 static int 1758 msk_detach(device_t dev) 1759 { 1760 struct msk_if_softc *sc_if = device_get_softc(dev); 1761 1762 if (device_is_attached(dev)) { 1763 struct msk_softc *sc = sc_if->msk_softc; 1764 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1765 1766 lwkt_serialize_enter(ifp->if_serializer); 1767 1768 if (sc->msk_intrhand != NULL) { 1769 if (sc->msk_if[MSK_PORT_A] != NULL) 1770 msk_stop(sc->msk_if[MSK_PORT_A]); 1771 if (sc->msk_if[MSK_PORT_B] != NULL) 1772 msk_stop(sc->msk_if[MSK_PORT_B]); 1773 1774 bus_teardown_intr(sc->msk_dev, sc->msk_irq, 1775 sc->msk_intrhand); 1776 sc->msk_intrhand = NULL; 1777 } 1778 1779 lwkt_serialize_exit(ifp->if_serializer); 1780 1781 ether_ifdetach(ifp); 1782 } 1783 1784 if (sc_if->msk_miibus != NULL) 1785 device_delete_child(dev, sc_if->msk_miibus); 1786 1787 msk_txrx_dma_free(sc_if); 1788 return (0); 1789 } 1790 1791 static int 1792 mskc_detach(device_t dev) 1793 { 1794 struct msk_softc *sc = device_get_softc(dev); 1795 int *port, i; 1796 1797 #ifdef INVARIANTS 1798 if (device_is_attached(dev)) { 1799 KASSERT(sc->msk_intrhand == NULL, 1800 ("intr is not torn down yet")); 1801 } 1802 #endif 1803 1804 for (i = 0; i < sc->msk_num_port; ++i) { 1805 if (sc->msk_devs[i] != NULL) { 1806 port = device_get_ivars(sc->msk_devs[i]); 1807 if (port != NULL) { 1808 kfree(port, M_DEVBUF); 1809 device_set_ivars(sc->msk_devs[i], NULL); 1810 } 1811 device_delete_child(dev, sc->msk_devs[i]); 1812 } 1813 } 1814 1815 /* Disable all interrupts. */ 1816 CSR_WRITE_4(sc, B0_IMSK, 0); 1817 CSR_READ_4(sc, B0_IMSK); 1818 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1819 CSR_READ_4(sc, B0_HWE_IMSK); 1820 1821 /* LED Off. */ 1822 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1823 1824 /* Put hardware reset. */ 1825 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1826 1827 mskc_status_dma_free(sc); 1828 1829 if (sc->msk_irq != NULL) { 1830 bus_release_resource(dev, SYS_RES_IRQ, sc->msk_irq_rid, 1831 sc->msk_irq); 1832 } 1833 if (sc->msk_res != NULL) { 1834 bus_release_resource(dev, sc->msk_res_type, sc->msk_res_rid, 1835 sc->msk_res); 1836 } 1837 1838 if (sc->msk_sysctl_tree != NULL) 1839 sysctl_ctx_free(&sc->msk_sysctl_ctx); 1840 1841 return (0); 1842 } 1843 1844 /* Create status DMA region. */ 1845 static int 1846 mskc_status_dma_alloc(struct msk_softc *sc) 1847 { 1848 bus_dmamem_t dmem; 1849 int error; 1850 1851 error = bus_dmamem_coherent(NULL/* XXX parent */, MSK_STAT_ALIGN, 0, 1852 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1853 MSK_STAT_RING_SZ, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1854 if (error) { 1855 device_printf(sc->msk_dev, 1856 "failed to create status coherent DMA memory\n"); 1857 return error; 1858 } 1859 sc->msk_stat_tag = dmem.dmem_tag; 1860 sc->msk_stat_map = dmem.dmem_map; 1861 sc->msk_stat_ring = dmem.dmem_addr; 1862 sc->msk_stat_ring_paddr = dmem.dmem_busaddr; 1863 1864 return (0); 1865 } 1866 1867 static void 1868 mskc_status_dma_free(struct msk_softc *sc) 1869 { 1870 /* Destroy status block. */ 1871 if (sc->msk_stat_tag) { 1872 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1873 bus_dmamem_free(sc->msk_stat_tag, sc->msk_stat_ring, 1874 sc->msk_stat_map); 1875 bus_dma_tag_destroy(sc->msk_stat_tag); 1876 sc->msk_stat_tag = NULL; 1877 } 1878 } 1879 1880 static int 1881 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1882 { 1883 int error, i, j; 1884 #ifdef MSK_JUMBO 1885 struct msk_rxdesc *jrxd; 1886 struct msk_jpool_entry *entry; 1887 uint8_t *ptr; 1888 #endif 1889 bus_size_t rxalign; 1890 1891 /* Create parent DMA tag. */ 1892 /* 1893 * XXX 1894 * It seems that Yukon II supports full 64bits DMA operations. But 1895 * it needs two descriptors(list elements) for 64bits DMA operations. 1896 * Since we don't know what DMA address mappings(32bits or 64bits) 1897 * would be used in advance for each mbufs, we limits its DMA space 1898 * to be in range of 32bits address space. Otherwise, we should check 1899 * what DMA address is used and chain another descriptor for the 1900 * 64bits DMA operation. This also means descriptor ring size is 1901 * variable. Limiting DMA address to be in 32bit address space greatly 1902 * simplyfies descriptor handling and possibly would increase 1903 * performance a bit due to efficient handling of descriptors. 1904 * Apart from harassing checksum offloading mechanisms, it seems 1905 * it's really bad idea to use a seperate descriptor for 64bit 1906 * DMA operation to save small descriptor memory. Anyway, I've 1907 * never seen these exotic scheme on ethernet interface hardware. 1908 */ 1909 error = bus_dma_tag_create( 1910 NULL, /* parent */ 1911 1, 0, /* alignment, boundary */ 1912 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1913 BUS_SPACE_MAXADDR, /* highaddr */ 1914 NULL, NULL, /* filter, filterarg */ 1915 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1916 0, /* nsegments */ 1917 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1918 0, /* flags */ 1919 &sc_if->msk_cdata.msk_parent_tag); 1920 if (error) { 1921 device_printf(sc_if->msk_if_dev, 1922 "failed to create parent DMA tag\n"); 1923 return error; 1924 } 1925 1926 /* Create DMA stuffs for Tx ring. */ 1927 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_TX_RING_SZ, 1928 &sc_if->msk_cdata.msk_tx_ring_tag, 1929 (void *)&sc_if->msk_rdata.msk_tx_ring, 1930 &sc_if->msk_rdata.msk_tx_ring_paddr, 1931 &sc_if->msk_cdata.msk_tx_ring_map); 1932 if (error) { 1933 device_printf(sc_if->msk_if_dev, 1934 "failed to create TX ring DMA stuffs\n"); 1935 return error; 1936 } 1937 1938 /* Create DMA stuffs for Rx ring. */ 1939 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_RX_RING_SZ, 1940 &sc_if->msk_cdata.msk_rx_ring_tag, 1941 (void *)&sc_if->msk_rdata.msk_rx_ring, 1942 &sc_if->msk_rdata.msk_rx_ring_paddr, 1943 &sc_if->msk_cdata.msk_rx_ring_map); 1944 if (error) { 1945 device_printf(sc_if->msk_if_dev, 1946 "failed to create RX ring DMA stuffs\n"); 1947 return error; 1948 } 1949 1950 /* Create tag for Tx buffers. */ 1951 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 1952 1, 0, /* alignment, boundary */ 1953 BUS_SPACE_MAXADDR, /* lowaddr */ 1954 BUS_SPACE_MAXADDR, /* highaddr */ 1955 NULL, NULL, /* filter, filterarg */ 1956 MSK_JUMBO_FRAMELEN, /* maxsize */ 1957 MSK_MAXTXSEGS, /* nsegments */ 1958 MSK_MAXSGSIZE, /* maxsegsize */ 1959 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 1960 BUS_DMA_ONEBPAGE, /* flags */ 1961 &sc_if->msk_cdata.msk_tx_tag); 1962 if (error) { 1963 device_printf(sc_if->msk_if_dev, 1964 "failed to create Tx DMA tag\n"); 1965 return error; 1966 } 1967 1968 /* Create DMA maps for Tx buffers. */ 1969 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1970 struct msk_txdesc *txd = &sc_if->msk_cdata.msk_txdesc[i]; 1971 1972 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 1973 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1974 &txd->tx_dmamap); 1975 if (error) { 1976 device_printf(sc_if->msk_if_dev, 1977 "failed to create %dth Tx dmamap\n", i); 1978 1979 for (j = 0; j < i; ++j) { 1980 txd = &sc_if->msk_cdata.msk_txdesc[j]; 1981 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 1982 txd->tx_dmamap); 1983 } 1984 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 1985 sc_if->msk_cdata.msk_tx_tag = NULL; 1986 1987 return error; 1988 } 1989 } 1990 1991 /* 1992 * Workaround hardware hang which seems to happen when Rx buffer 1993 * is not aligned on multiple of FIFO word(8 bytes). 1994 */ 1995 if (sc_if->msk_flags & MSK_FLAG_RAMBUF) 1996 rxalign = MSK_RX_BUF_ALIGN; 1997 else 1998 rxalign = 1; 1999 2000 /* Create tag for Rx buffers. */ 2001 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2002 rxalign, 0, /* alignment, boundary */ 2003 BUS_SPACE_MAXADDR, /* lowaddr */ 2004 BUS_SPACE_MAXADDR, /* highaddr */ 2005 NULL, NULL, /* filter, filterarg */ 2006 MCLBYTES, /* maxsize */ 2007 1, /* nsegments */ 2008 MCLBYTES, /* maxsegsize */ 2009 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED | 2010 BUS_DMA_WAITOK, /* flags */ 2011 &sc_if->msk_cdata.msk_rx_tag); 2012 if (error) { 2013 device_printf(sc_if->msk_if_dev, 2014 "failed to create Rx DMA tag\n"); 2015 return error; 2016 } 2017 2018 /* Create DMA maps for Rx buffers. */ 2019 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, BUS_DMA_WAITOK, 2020 &sc_if->msk_cdata.msk_rx_sparemap); 2021 if (error) { 2022 device_printf(sc_if->msk_if_dev, 2023 "failed to create spare Rx dmamap\n"); 2024 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2025 sc_if->msk_cdata.msk_rx_tag = NULL; 2026 return error; 2027 } 2028 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2029 struct msk_rxdesc *rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2030 2031 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 2032 BUS_DMA_WAITOK, &rxd->rx_dmamap); 2033 if (error) { 2034 device_printf(sc_if->msk_if_dev, 2035 "failed to create %dth Rx dmamap\n", i); 2036 2037 for (j = 0; j < i; ++j) { 2038 rxd = &sc_if->msk_cdata.msk_rxdesc[j]; 2039 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2040 rxd->rx_dmamap); 2041 } 2042 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2043 sc_if->msk_cdata.msk_rx_sparemap); 2044 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2045 sc_if->msk_cdata.msk_rx_tag = NULL; 2046 2047 return error; 2048 } 2049 } 2050 2051 #ifdef MSK_JUMBO 2052 SLIST_INIT(&sc_if->msk_jfree_listhead); 2053 SLIST_INIT(&sc_if->msk_jinuse_listhead); 2054 2055 /* Create tag for jumbo Rx ring. */ 2056 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2057 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2058 BUS_SPACE_MAXADDR, /* lowaddr */ 2059 BUS_SPACE_MAXADDR, /* highaddr */ 2060 NULL, NULL, /* filter, filterarg */ 2061 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2062 1, /* nsegments */ 2063 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2064 0, /* flags */ 2065 NULL, NULL, /* lockfunc, lockarg */ 2066 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2067 if (error != 0) { 2068 device_printf(sc_if->msk_if_dev, 2069 "failed to create jumbo Rx ring DMA tag\n"); 2070 goto fail; 2071 } 2072 2073 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2074 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2075 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2076 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2077 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2078 if (error != 0) { 2079 device_printf(sc_if->msk_if_dev, 2080 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2081 goto fail; 2082 } 2083 2084 ctx.msk_busaddr = 0; 2085 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2086 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2087 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2088 msk_dmamap_cb, &ctx, 0); 2089 if (error != 0) { 2090 device_printf(sc_if->msk_if_dev, 2091 "failed to load DMA'able memory for jumbo Rx ring\n"); 2092 goto fail; 2093 } 2094 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2095 2096 /* Create tag for jumbo buffer blocks. */ 2097 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2098 PAGE_SIZE, 0, /* alignment, boundary */ 2099 BUS_SPACE_MAXADDR, /* lowaddr */ 2100 BUS_SPACE_MAXADDR, /* highaddr */ 2101 NULL, NULL, /* filter, filterarg */ 2102 MSK_JMEM, /* maxsize */ 2103 1, /* nsegments */ 2104 MSK_JMEM, /* maxsegsize */ 2105 0, /* flags */ 2106 NULL, NULL, /* lockfunc, lockarg */ 2107 &sc_if->msk_cdata.msk_jumbo_tag); 2108 if (error != 0) { 2109 device_printf(sc_if->msk_if_dev, 2110 "failed to create jumbo Rx buffer block DMA tag\n"); 2111 goto fail; 2112 } 2113 2114 /* Create tag for jumbo Rx buffers. */ 2115 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2116 PAGE_SIZE, 0, /* alignment, boundary */ 2117 BUS_SPACE_MAXADDR, /* lowaddr */ 2118 BUS_SPACE_MAXADDR, /* highaddr */ 2119 NULL, NULL, /* filter, filterarg */ 2120 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2121 MSK_MAXRXSEGS, /* nsegments */ 2122 MSK_JLEN, /* maxsegsize */ 2123 0, /* flags */ 2124 NULL, NULL, /* lockfunc, lockarg */ 2125 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2126 if (error != 0) { 2127 device_printf(sc_if->msk_if_dev, 2128 "failed to create jumbo Rx DMA tag\n"); 2129 goto fail; 2130 } 2131 2132 /* Create DMA maps for jumbo Rx buffers. */ 2133 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2134 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2135 device_printf(sc_if->msk_if_dev, 2136 "failed to create spare jumbo Rx dmamap\n"); 2137 goto fail; 2138 } 2139 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2140 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2141 jrxd->rx_m = NULL; 2142 jrxd->rx_dmamap = NULL; 2143 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2144 &jrxd->rx_dmamap); 2145 if (error != 0) { 2146 device_printf(sc_if->msk_if_dev, 2147 "failed to create jumbo Rx dmamap\n"); 2148 goto fail; 2149 } 2150 } 2151 2152 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2153 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2154 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2155 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2156 &sc_if->msk_cdata.msk_jumbo_map); 2157 if (error != 0) { 2158 device_printf(sc_if->msk_if_dev, 2159 "failed to allocate DMA'able memory for jumbo buf\n"); 2160 goto fail; 2161 } 2162 2163 ctx.msk_busaddr = 0; 2164 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2165 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2166 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2167 if (error != 0) { 2168 device_printf(sc_if->msk_if_dev, 2169 "failed to load DMA'able memory for jumbobuf\n"); 2170 goto fail; 2171 } 2172 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2173 2174 /* 2175 * Now divide it up into 9K pieces and save the addresses 2176 * in an array. 2177 */ 2178 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2179 for (i = 0; i < MSK_JSLOTS; i++) { 2180 sc_if->msk_cdata.msk_jslots[i] = ptr; 2181 ptr += MSK_JLEN; 2182 entry = malloc(sizeof(struct msk_jpool_entry), 2183 M_DEVBUF, M_WAITOK); 2184 if (entry == NULL) { 2185 device_printf(sc_if->msk_if_dev, 2186 "no memory for jumbo buffers!\n"); 2187 error = ENOMEM; 2188 goto fail; 2189 } 2190 entry->slot = i; 2191 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2192 jpool_entries); 2193 } 2194 #endif 2195 return 0; 2196 } 2197 2198 static void 2199 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2200 { 2201 struct msk_txdesc *txd; 2202 struct msk_rxdesc *rxd; 2203 #ifdef MSK_JUMBO 2204 struct msk_rxdesc *jrxd; 2205 struct msk_jpool_entry *entry; 2206 #endif 2207 int i; 2208 2209 #ifdef MSK_JUMBO 2210 MSK_JLIST_LOCK(sc_if); 2211 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2212 device_printf(sc_if->msk_if_dev, 2213 "asked to free buffer that is in use!\n"); 2214 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2215 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2216 jpool_entries); 2217 } 2218 2219 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2220 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2221 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2222 free(entry, M_DEVBUF); 2223 } 2224 MSK_JLIST_UNLOCK(sc_if); 2225 2226 /* Destroy jumbo buffer block. */ 2227 if (sc_if->msk_cdata.msk_jumbo_map) 2228 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2229 sc_if->msk_cdata.msk_jumbo_map); 2230 2231 if (sc_if->msk_rdata.msk_jumbo_buf) { 2232 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2233 sc_if->msk_rdata.msk_jumbo_buf, 2234 sc_if->msk_cdata.msk_jumbo_map); 2235 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2236 sc_if->msk_cdata.msk_jumbo_map = NULL; 2237 } 2238 2239 /* Jumbo Rx ring. */ 2240 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2241 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2242 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2243 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2244 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2245 sc_if->msk_rdata.msk_jumbo_rx_ring) 2246 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2247 sc_if->msk_rdata.msk_jumbo_rx_ring, 2248 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2249 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2250 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2251 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2252 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2253 } 2254 2255 /* Jumbo Rx buffers. */ 2256 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2257 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2258 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2259 if (jrxd->rx_dmamap) { 2260 bus_dmamap_destroy( 2261 sc_if->msk_cdata.msk_jumbo_rx_tag, 2262 jrxd->rx_dmamap); 2263 jrxd->rx_dmamap = NULL; 2264 } 2265 } 2266 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2267 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2268 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2269 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2270 } 2271 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2272 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2273 } 2274 #endif 2275 2276 /* Tx ring. */ 2277 msk_dmamem_destroy(sc_if->msk_cdata.msk_tx_ring_tag, 2278 sc_if->msk_rdata.msk_tx_ring, 2279 sc_if->msk_cdata.msk_tx_ring_map); 2280 2281 /* Rx ring. */ 2282 msk_dmamem_destroy(sc_if->msk_cdata.msk_rx_ring_tag, 2283 sc_if->msk_rdata.msk_rx_ring, 2284 sc_if->msk_cdata.msk_rx_ring_map); 2285 2286 /* Tx buffers. */ 2287 if (sc_if->msk_cdata.msk_tx_tag) { 2288 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2289 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2290 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2291 txd->tx_dmamap); 2292 } 2293 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2294 sc_if->msk_cdata.msk_tx_tag = NULL; 2295 } 2296 2297 /* Rx buffers. */ 2298 if (sc_if->msk_cdata.msk_rx_tag) { 2299 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2300 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2301 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2302 rxd->rx_dmamap); 2303 } 2304 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2305 sc_if->msk_cdata.msk_rx_sparemap); 2306 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2307 sc_if->msk_cdata.msk_rx_tag = NULL; 2308 } 2309 2310 if (sc_if->msk_cdata.msk_parent_tag) { 2311 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2312 sc_if->msk_cdata.msk_parent_tag = NULL; 2313 } 2314 } 2315 2316 #ifdef MSK_JUMBO 2317 /* 2318 * Allocate a jumbo buffer. 2319 */ 2320 static void * 2321 msk_jalloc(struct msk_if_softc *sc_if) 2322 { 2323 struct msk_jpool_entry *entry; 2324 2325 MSK_JLIST_LOCK(sc_if); 2326 2327 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2328 2329 if (entry == NULL) { 2330 MSK_JLIST_UNLOCK(sc_if); 2331 return (NULL); 2332 } 2333 2334 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2335 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2336 2337 MSK_JLIST_UNLOCK(sc_if); 2338 2339 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2340 } 2341 2342 /* 2343 * Release a jumbo buffer. 2344 */ 2345 static void 2346 msk_jfree(void *buf, void *args) 2347 { 2348 struct msk_if_softc *sc_if; 2349 struct msk_jpool_entry *entry; 2350 int i; 2351 2352 /* Extract the softc struct pointer. */ 2353 sc_if = (struct msk_if_softc *)args; 2354 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2355 2356 MSK_JLIST_LOCK(sc_if); 2357 /* Calculate the slot this buffer belongs to. */ 2358 i = ((vm_offset_t)buf 2359 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2360 KASSERT(i >= 0 && i < MSK_JSLOTS, 2361 ("%s: asked to free buffer that we don't manage!", __func__)); 2362 2363 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2364 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2365 entry->slot = i; 2366 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2367 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2368 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2369 wakeup(sc_if); 2370 2371 MSK_JLIST_UNLOCK(sc_if); 2372 } 2373 #endif 2374 2375 static int 2376 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2377 { 2378 struct msk_txdesc *txd, *txd_last; 2379 struct msk_tx_desc *tx_le; 2380 struct mbuf *m; 2381 bus_dmamap_t map; 2382 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2383 uint32_t control, prod, si; 2384 uint16_t offset, tcp_offset; 2385 int error, i, nsegs, maxsegs, defrag; 2386 2387 maxsegs = MSK_TX_RING_CNT - sc_if->msk_cdata.msk_tx_cnt - 2388 MSK_RESERVED_TX_DESC_CNT; 2389 KASSERT(maxsegs >= MSK_SPARE_TX_DESC_CNT, 2390 ("not enough spare TX desc")); 2391 if (maxsegs > MSK_MAXTXSEGS) 2392 maxsegs = MSK_MAXTXSEGS; 2393 2394 /* 2395 * Align TX buffer to 64bytes boundary. This greately improves 2396 * bulk data TX performance on my 88E8053 (+100Mbps) at least. 2397 * Try avoiding m_defrag(), if the mbufs are not chained together 2398 * by m_next (i.e. m->m_len == m->m_pkthdr.len). 2399 */ 2400 2401 #define MSK_TXBUF_ALIGN 64 2402 #define MSK_TXBUF_MASK (MSK_TXBUF_ALIGN - 1) 2403 2404 defrag = 1; 2405 m = *m_head; 2406 if (m->m_len == m->m_pkthdr.len) { 2407 int space; 2408 2409 space = ((uintptr_t)m->m_data & MSK_TXBUF_MASK); 2410 if (space) { 2411 if (M_WRITABLE(m)) { 2412 if (M_TRAILINGSPACE(m) >= space) { 2413 /* e.g. TCP ACKs */ 2414 bcopy(m->m_data, m->m_data + space, 2415 m->m_len); 2416 m->m_data += space; 2417 defrag = 0; 2418 sc_if->msk_softc->msk_trailing_copied++; 2419 } else { 2420 space = MSK_TXBUF_ALIGN - space; 2421 if (M_LEADINGSPACE(m) >= space) { 2422 /* e.g. Small UDP datagrams */ 2423 bcopy(m->m_data, 2424 m->m_data - space, 2425 m->m_len); 2426 m->m_data -= space; 2427 defrag = 0; 2428 sc_if->msk_softc-> 2429 msk_leading_copied++; 2430 } 2431 } 2432 } 2433 } else { 2434 /* e.g. on forwarding path */ 2435 defrag = 0; 2436 } 2437 } 2438 if (defrag) { 2439 m = m_defrag(*m_head, MB_DONTWAIT); 2440 if (m == NULL) { 2441 m_freem(*m_head); 2442 *m_head = NULL; 2443 return ENOBUFS; 2444 } 2445 *m_head = m; 2446 } else { 2447 sc_if->msk_softc->msk_defrag_avoided++; 2448 } 2449 2450 #undef MSK_TXBUF_MASK 2451 #undef MSK_TXBUF_ALIGN 2452 2453 tcp_offset = offset = 0; 2454 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) { 2455 /* 2456 * Since mbuf has no protocol specific structure information 2457 * in it we have to inspect protocol information here to 2458 * setup TSO and checksum offload. I don't know why Marvell 2459 * made a such decision in chip design because other GigE 2460 * hardwares normally takes care of all these chores in 2461 * hardware. However, TSO performance of Yukon II is very 2462 * good such that it's worth to implement it. 2463 */ 2464 struct ether_header *eh; 2465 struct ip *ip; 2466 2467 /* TODO check for M_WRITABLE(m) */ 2468 2469 offset = sizeof(struct ether_header); 2470 m = m_pullup(m, offset); 2471 if (m == NULL) { 2472 *m_head = NULL; 2473 return (ENOBUFS); 2474 } 2475 eh = mtod(m, struct ether_header *); 2476 /* Check if hardware VLAN insertion is off. */ 2477 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2478 offset = sizeof(struct ether_vlan_header); 2479 m = m_pullup(m, offset); 2480 if (m == NULL) { 2481 *m_head = NULL; 2482 return (ENOBUFS); 2483 } 2484 } 2485 m = m_pullup(m, offset + sizeof(struct ip)); 2486 if (m == NULL) { 2487 *m_head = NULL; 2488 return (ENOBUFS); 2489 } 2490 ip = (struct ip *)(mtod(m, char *) + offset); 2491 offset += (ip->ip_hl << 2); 2492 tcp_offset = offset; 2493 /* 2494 * It seems that Yukon II has Tx checksum offload bug for 2495 * small TCP packets that's less than 60 bytes in size 2496 * (e.g. TCP window probe packet, pure ACK packet). 2497 * Common work around like padding with zeros to make the 2498 * frame minimum ethernet frame size didn't work at all. 2499 * Instead of disabling checksum offload completely we 2500 * resort to S/W checksum routine when we encounter short 2501 * TCP frames. 2502 * Short UDP packets appear to be handled correctly by 2503 * Yukon II. 2504 */ 2505 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2506 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2507 uint16_t csum; 2508 2509 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2510 (ip->ip_hl << 2), offset); 2511 *(uint16_t *)(m->m_data + offset + 2512 m->m_pkthdr.csum_data) = csum; 2513 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2514 } 2515 *m_head = m; 2516 } 2517 2518 prod = sc_if->msk_cdata.msk_tx_prod; 2519 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2520 txd_last = txd; 2521 map = txd->tx_dmamap; 2522 2523 error = bus_dmamap_load_mbuf_defrag(sc_if->msk_cdata.msk_tx_tag, map, 2524 m_head, txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2525 if (error) { 2526 m_freem(*m_head); 2527 *m_head = NULL; 2528 return error; 2529 } 2530 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2531 2532 m = *m_head; 2533 control = 0; 2534 tx_le = NULL; 2535 2536 #ifdef notyet 2537 /* Check if we have a VLAN tag to insert. */ 2538 if ((m->m_flags & M_VLANTAG) != 0) { 2539 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2540 tx_le->msk_addr = htole32(0); 2541 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2542 htons(m->m_pkthdr.ether_vtag)); 2543 sc_if->msk_cdata.msk_tx_cnt++; 2544 MSK_INC(prod, MSK_TX_RING_CNT); 2545 control |= INS_VLAN; 2546 } 2547 #endif 2548 /* Check if we have to handle checksum offload. */ 2549 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) { 2550 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2551 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2552 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2553 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2554 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2555 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2556 control |= UDPTCP; 2557 sc_if->msk_cdata.msk_tx_cnt++; 2558 MSK_INC(prod, MSK_TX_RING_CNT); 2559 } 2560 2561 si = prod; 2562 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2563 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2564 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2565 OP_PACKET); 2566 sc_if->msk_cdata.msk_tx_cnt++; 2567 MSK_INC(prod, MSK_TX_RING_CNT); 2568 2569 for (i = 1; i < nsegs; i++) { 2570 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2571 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2572 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2573 OP_BUFFER | HW_OWNER); 2574 sc_if->msk_cdata.msk_tx_cnt++; 2575 MSK_INC(prod, MSK_TX_RING_CNT); 2576 } 2577 /* Update producer index. */ 2578 sc_if->msk_cdata.msk_tx_prod = prod; 2579 2580 /* Set EOP on the last desciptor. */ 2581 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2582 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2583 tx_le->msk_control |= htole32(EOP); 2584 2585 /* Turn the first descriptor ownership to hardware. */ 2586 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2587 tx_le->msk_control |= htole32(HW_OWNER); 2588 2589 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2590 map = txd_last->tx_dmamap; 2591 txd_last->tx_dmamap = txd->tx_dmamap; 2592 txd->tx_dmamap = map; 2593 txd->tx_m = m; 2594 2595 return (0); 2596 } 2597 2598 static void 2599 msk_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2600 { 2601 struct msk_if_softc *sc_if; 2602 struct mbuf *m_head; 2603 int enq; 2604 2605 sc_if = ifp->if_softc; 2606 2607 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2608 ASSERT_SERIALIZED(ifp->if_serializer); 2609 2610 if (!sc_if->msk_link) { 2611 ifq_purge(&ifp->if_snd); 2612 return; 2613 } 2614 2615 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2616 return; 2617 2618 enq = 0; 2619 while (!ifq_is_empty(&ifp->if_snd)) { 2620 if (MSK_IS_OACTIVE(sc_if)) { 2621 ifq_set_oactive(&ifp->if_snd); 2622 break; 2623 } 2624 2625 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2626 if (m_head == NULL) 2627 break; 2628 2629 /* 2630 * Pack the data into the transmit ring. If we 2631 * don't have room, set the OACTIVE flag and wait 2632 * for the NIC to drain the ring. 2633 */ 2634 if (msk_encap(sc_if, &m_head) != 0) { 2635 ifp->if_oerrors++; 2636 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2637 continue; 2638 } else { 2639 ifq_set_oactive(&ifp->if_snd); 2640 break; 2641 } 2642 } 2643 enq = 1; 2644 2645 /* 2646 * If there's a BPF listener, bounce a copy of this frame 2647 * to him. 2648 */ 2649 BPF_MTAP(ifp, m_head); 2650 } 2651 2652 if (enq) { 2653 /* Transmit */ 2654 CSR_WRITE_2(sc_if->msk_softc, 2655 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2656 sc_if->msk_cdata.msk_tx_prod); 2657 2658 /* Set a timeout in case the chip goes out to lunch. */ 2659 ifp->if_timer = MSK_TX_TIMEOUT; 2660 } 2661 } 2662 2663 static void 2664 msk_watchdog(struct ifnet *ifp) 2665 { 2666 struct msk_if_softc *sc_if = ifp->if_softc; 2667 uint32_t ridx; 2668 int idx; 2669 2670 ASSERT_SERIALIZED(ifp->if_serializer); 2671 2672 if (sc_if->msk_link == 0) { 2673 if (bootverbose) 2674 if_printf(sc_if->msk_ifp, "watchdog timeout " 2675 "(missed link)\n"); 2676 ifp->if_oerrors++; 2677 msk_init(sc_if); 2678 return; 2679 } 2680 2681 /* 2682 * Reclaim first as there is a possibility of losing Tx completion 2683 * interrupts. 2684 */ 2685 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2686 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2687 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2688 msk_txeof(sc_if, idx); 2689 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2690 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2691 "-- recovering\n"); 2692 if (!ifq_is_empty(&ifp->if_snd)) 2693 if_devstart(ifp); 2694 return; 2695 } 2696 } 2697 2698 if_printf(ifp, "watchdog timeout\n"); 2699 ifp->if_oerrors++; 2700 msk_init(sc_if); 2701 if (!ifq_is_empty(&ifp->if_snd)) 2702 if_devstart(ifp); 2703 } 2704 2705 static int 2706 mskc_shutdown(device_t dev) 2707 { 2708 struct msk_softc *sc = device_get_softc(dev); 2709 int i; 2710 2711 lwkt_serialize_enter(&sc->msk_serializer); 2712 2713 for (i = 0; i < sc->msk_num_port; i++) { 2714 if (sc->msk_if[i] != NULL) 2715 msk_stop(sc->msk_if[i]); 2716 } 2717 2718 /* Put hardware reset. */ 2719 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2720 2721 lwkt_serialize_exit(&sc->msk_serializer); 2722 return (0); 2723 } 2724 2725 static int 2726 mskc_suspend(device_t dev) 2727 { 2728 struct msk_softc *sc = device_get_softc(dev); 2729 int i; 2730 2731 lwkt_serialize_enter(&sc->msk_serializer); 2732 2733 for (i = 0; i < sc->msk_num_port; i++) { 2734 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2735 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_RUNNING) != 0)) 2736 msk_stop(sc->msk_if[i]); 2737 } 2738 2739 /* Disable all interrupts. */ 2740 CSR_WRITE_4(sc, B0_IMSK, 0); 2741 CSR_READ_4(sc, B0_IMSK); 2742 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2743 CSR_READ_4(sc, B0_HWE_IMSK); 2744 2745 mskc_phy_power(sc, MSK_PHY_POWERDOWN); 2746 2747 /* Put hardware reset. */ 2748 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2749 sc->msk_suspended = 1; 2750 2751 lwkt_serialize_exit(&sc->msk_serializer); 2752 2753 return (0); 2754 } 2755 2756 static int 2757 mskc_resume(device_t dev) 2758 { 2759 struct msk_softc *sc = device_get_softc(dev); 2760 int i; 2761 2762 lwkt_serialize_enter(&sc->msk_serializer); 2763 2764 /* Enable all clocks before accessing any registers. */ 2765 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 2766 mskc_reset(sc); 2767 for (i = 0; i < sc->msk_num_port; i++) { 2768 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2769 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2770 msk_init(sc->msk_if[i]); 2771 } 2772 sc->msk_suspended = 0; 2773 2774 lwkt_serialize_exit(&sc->msk_serializer); 2775 2776 return (0); 2777 } 2778 2779 static void 2780 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2781 { 2782 struct mbuf *m; 2783 struct ifnet *ifp; 2784 struct msk_rxdesc *rxd; 2785 int cons, rxlen; 2786 2787 ifp = sc_if->msk_ifp; 2788 2789 cons = sc_if->msk_cdata.msk_rx_cons; 2790 do { 2791 rxlen = status >> 16; 2792 if ((status & GMR_FS_VLAN) != 0 && 2793 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2794 rxlen -= EVL_ENCAPLEN; 2795 if (sc_if->msk_flags & MSK_FLAG_NORXCHK) { 2796 /* 2797 * For controllers that returns bogus status code 2798 * just do minimal check and let upper stack 2799 * handle this frame. 2800 */ 2801 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 2802 ifp->if_ierrors++; 2803 msk_discard_rxbuf(sc_if, cons); 2804 break; 2805 } 2806 } else if (len > sc_if->msk_framesize || 2807 ((status & GMR_FS_ANY_ERR) != 0) || 2808 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2809 /* Don't count flow-control packet as errors. */ 2810 if ((status & GMR_FS_GOOD_FC) == 0) 2811 ifp->if_ierrors++; 2812 msk_discard_rxbuf(sc_if, cons); 2813 break; 2814 } 2815 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2816 m = rxd->rx_m; 2817 if (msk_newbuf(sc_if, cons, 0) != 0) { 2818 ifp->if_iqdrops++; 2819 /* Reuse old buffer. */ 2820 msk_discard_rxbuf(sc_if, cons); 2821 break; 2822 } 2823 m->m_pkthdr.rcvif = ifp; 2824 m->m_pkthdr.len = m->m_len = len; 2825 ifp->if_ipackets++; 2826 #ifdef notyet 2827 /* Check for VLAN tagged packets. */ 2828 if ((status & GMR_FS_VLAN) != 0 && 2829 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2830 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2831 m->m_flags |= M_VLANTAG; 2832 } 2833 #endif 2834 2835 ifp->if_input(ifp, m); 2836 } while (0); 2837 2838 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2839 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2840 } 2841 2842 #ifdef MSK_JUMBO 2843 static void 2844 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2845 { 2846 struct mbuf *m; 2847 struct ifnet *ifp; 2848 struct msk_rxdesc *jrxd; 2849 int cons, rxlen; 2850 2851 ifp = sc_if->msk_ifp; 2852 2853 MSK_IF_LOCK_ASSERT(sc_if); 2854 2855 cons = sc_if->msk_cdata.msk_rx_cons; 2856 do { 2857 rxlen = status >> 16; 2858 if ((status & GMR_FS_VLAN) != 0 && 2859 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2860 rxlen -= ETHER_VLAN_ENCAP_LEN; 2861 if (len > sc_if->msk_framesize || 2862 ((status & GMR_FS_ANY_ERR) != 0) || 2863 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2864 /* Don't count flow-control packet as errors. */ 2865 if ((status & GMR_FS_GOOD_FC) == 0) 2866 ifp->if_ierrors++; 2867 msk_discard_jumbo_rxbuf(sc_if, cons); 2868 break; 2869 } 2870 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 2871 m = jrxd->rx_m; 2872 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 2873 ifp->if_iqdrops++; 2874 /* Reuse old buffer. */ 2875 msk_discard_jumbo_rxbuf(sc_if, cons); 2876 break; 2877 } 2878 m->m_pkthdr.rcvif = ifp; 2879 m->m_pkthdr.len = m->m_len = len; 2880 ifp->if_ipackets++; 2881 /* Check for VLAN tagged packets. */ 2882 if ((status & GMR_FS_VLAN) != 0 && 2883 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2884 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2885 m->m_flags |= M_VLANTAG; 2886 } 2887 MSK_IF_UNLOCK(sc_if); 2888 (*ifp->if_input)(ifp, m); 2889 MSK_IF_LOCK(sc_if); 2890 } while (0); 2891 2892 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 2893 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 2894 } 2895 #endif 2896 2897 static void 2898 msk_txeof(struct msk_if_softc *sc_if, int idx) 2899 { 2900 struct msk_txdesc *txd; 2901 struct msk_tx_desc *cur_tx; 2902 struct ifnet *ifp; 2903 uint32_t control; 2904 int cons, prog; 2905 2906 ifp = sc_if->msk_ifp; 2907 2908 /* 2909 * Go through our tx ring and free mbufs for those 2910 * frames that have been sent. 2911 */ 2912 cons = sc_if->msk_cdata.msk_tx_cons; 2913 prog = 0; 2914 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 2915 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 2916 break; 2917 prog++; 2918 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 2919 control = le32toh(cur_tx->msk_control); 2920 sc_if->msk_cdata.msk_tx_cnt--; 2921 if ((control & EOP) == 0) 2922 continue; 2923 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 2924 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 2925 2926 ifp->if_opackets++; 2927 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 2928 __func__)); 2929 m_freem(txd->tx_m); 2930 txd->tx_m = NULL; 2931 } 2932 2933 if (prog > 0) { 2934 sc_if->msk_cdata.msk_tx_cons = cons; 2935 if (!MSK_IS_OACTIVE(sc_if)) 2936 ifq_clr_oactive(&ifp->if_snd); 2937 if (sc_if->msk_cdata.msk_tx_cnt == 0) 2938 ifp->if_timer = 0; 2939 /* No need to sync LEs as we didn't update LEs. */ 2940 } 2941 } 2942 2943 static void 2944 msk_tick(void *xsc_if) 2945 { 2946 struct msk_if_softc *sc_if = xsc_if; 2947 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2948 struct mii_data *mii; 2949 2950 lwkt_serialize_enter(ifp->if_serializer); 2951 2952 mii = device_get_softc(sc_if->msk_miibus); 2953 2954 mii_tick(mii); 2955 if (!sc_if->msk_link) 2956 msk_miibus_statchg(sc_if->msk_if_dev); 2957 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 2958 2959 lwkt_serialize_exit(ifp->if_serializer); 2960 } 2961 2962 static void 2963 msk_intr_phy(struct msk_if_softc *sc_if) 2964 { 2965 uint16_t status; 2966 2967 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 2968 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 2969 /* Handle FIFO Underrun/Overflow? */ 2970 if (status & PHY_M_IS_FIFO_ERROR) { 2971 device_printf(sc_if->msk_if_dev, 2972 "PHY FIFO underrun/overflow.\n"); 2973 } 2974 } 2975 2976 static void 2977 msk_intr_gmac(struct msk_if_softc *sc_if) 2978 { 2979 struct msk_softc *sc; 2980 uint8_t status; 2981 2982 sc = sc_if->msk_softc; 2983 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 2984 2985 /* GMAC Rx FIFO overrun. */ 2986 if ((status & GM_IS_RX_FF_OR) != 0) { 2987 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 2988 GMF_CLI_RX_FO); 2989 } 2990 /* GMAC Tx FIFO underrun. */ 2991 if ((status & GM_IS_TX_FF_UR) != 0) { 2992 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 2993 GMF_CLI_TX_FU); 2994 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 2995 /* 2996 * XXX 2997 * In case of Tx underrun, we may need to flush/reset 2998 * Tx MAC but that would also require resynchronization 2999 * with status LEs. Reintializing status LEs would 3000 * affect other port in dual MAC configuration so it 3001 * should be avoided as possible as we can. 3002 * Due to lack of documentation it's all vague guess but 3003 * it needs more investigation. 3004 */ 3005 } 3006 } 3007 3008 static void 3009 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3010 { 3011 struct msk_softc *sc; 3012 3013 sc = sc_if->msk_softc; 3014 if ((status & Y2_IS_PAR_RD1) != 0) { 3015 device_printf(sc_if->msk_if_dev, 3016 "RAM buffer read parity error\n"); 3017 /* Clear IRQ. */ 3018 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3019 RI_CLR_RD_PERR); 3020 } 3021 if ((status & Y2_IS_PAR_WR1) != 0) { 3022 device_printf(sc_if->msk_if_dev, 3023 "RAM buffer write parity error\n"); 3024 /* Clear IRQ. */ 3025 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3026 RI_CLR_WR_PERR); 3027 } 3028 if ((status & Y2_IS_PAR_MAC1) != 0) { 3029 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3030 /* Clear IRQ. */ 3031 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3032 GMF_CLI_TX_PE); 3033 } 3034 if ((status & Y2_IS_PAR_RX1) != 0) { 3035 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3036 /* Clear IRQ. */ 3037 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3038 } 3039 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3040 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3041 /* Clear IRQ. */ 3042 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3043 } 3044 } 3045 3046 static void 3047 mskc_intr_hwerr(struct msk_softc *sc) 3048 { 3049 uint32_t status; 3050 uint32_t tlphead[4]; 3051 3052 status = CSR_READ_4(sc, B0_HWE_ISRC); 3053 /* Time Stamp timer overflow. */ 3054 if ((status & Y2_IS_TIST_OV) != 0) 3055 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3056 if ((status & Y2_IS_PCI_NEXP) != 0) { 3057 /* 3058 * PCI Express Error occured which is not described in PEX 3059 * spec. 3060 * This error is also mapped either to Master Abort( 3061 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3062 * can only be cleared there. 3063 */ 3064 device_printf(sc->msk_dev, 3065 "PCI Express protocol violation error\n"); 3066 } 3067 3068 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3069 uint16_t v16; 3070 3071 if ((status & Y2_IS_MST_ERR) != 0) 3072 device_printf(sc->msk_dev, 3073 "unexpected IRQ Status error\n"); 3074 else 3075 device_printf(sc->msk_dev, 3076 "unexpected IRQ Master error\n"); 3077 /* Reset all bits in the PCI status register. */ 3078 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3079 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3080 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3081 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3082 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3083 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3084 } 3085 3086 /* Check for PCI Express Uncorrectable Error. */ 3087 if ((status & Y2_IS_PCI_EXP) != 0) { 3088 uint32_t v32; 3089 3090 /* 3091 * On PCI Express bus bridges are called root complexes (RC). 3092 * PCI Express errors are recognized by the root complex too, 3093 * which requests the system to handle the problem. After 3094 * error occurence it may be that no access to the adapter 3095 * may be performed any longer. 3096 */ 3097 3098 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3099 if ((v32 & PEX_UNSUP_REQ) != 0) { 3100 /* Ignore unsupported request error. */ 3101 if (bootverbose) { 3102 device_printf(sc->msk_dev, 3103 "Uncorrectable PCI Express error\n"); 3104 } 3105 } 3106 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3107 int i; 3108 3109 /* Get TLP header form Log Registers. */ 3110 for (i = 0; i < 4; i++) 3111 tlphead[i] = CSR_PCI_READ_4(sc, 3112 PEX_HEADER_LOG + i * 4); 3113 /* Check for vendor defined broadcast message. */ 3114 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3115 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3116 CSR_WRITE_4(sc, B0_HWE_IMSK, 3117 sc->msk_intrhwemask); 3118 CSR_READ_4(sc, B0_HWE_IMSK); 3119 } 3120 } 3121 /* Clear the interrupt. */ 3122 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3123 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3124 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3125 } 3126 3127 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3128 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3129 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3130 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3131 } 3132 3133 static __inline void 3134 msk_rxput(struct msk_if_softc *sc_if) 3135 { 3136 struct msk_softc *sc; 3137 3138 sc = sc_if->msk_softc; 3139 #ifdef MSK_JUMBO 3140 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3141 bus_dmamap_sync( 3142 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3143 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3144 BUS_DMASYNC_PREWRITE); 3145 } 3146 #endif 3147 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3148 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3149 } 3150 3151 static int 3152 mskc_handle_events(struct msk_softc *sc) 3153 { 3154 struct msk_if_softc *sc_if; 3155 int rxput[2]; 3156 struct msk_stat_desc *sd; 3157 uint32_t control, status; 3158 int cons, idx, len, port, rxprog; 3159 3160 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3161 if (idx == sc->msk_stat_cons) 3162 return (0); 3163 3164 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3165 3166 rxprog = 0; 3167 for (cons = sc->msk_stat_cons; cons != idx;) { 3168 sd = &sc->msk_stat_ring[cons]; 3169 control = le32toh(sd->msk_control); 3170 if ((control & HW_OWNER) == 0) 3171 break; 3172 /* 3173 * Marvell's FreeBSD driver updates status LE after clearing 3174 * HW_OWNER. However we don't have a way to sync single LE 3175 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3176 * an entire DMA map. So don't sync LE until we have a better 3177 * way to sync LEs. 3178 */ 3179 control &= ~HW_OWNER; 3180 sd->msk_control = htole32(control); 3181 status = le32toh(sd->msk_status); 3182 len = control & STLE_LEN_MASK; 3183 port = (control >> 16) & 0x01; 3184 sc_if = sc->msk_if[port]; 3185 if (sc_if == NULL) { 3186 device_printf(sc->msk_dev, "invalid port opcode " 3187 "0x%08x\n", control & STLE_OP_MASK); 3188 continue; 3189 } 3190 3191 switch (control & STLE_OP_MASK) { 3192 case OP_RXVLAN: 3193 sc_if->msk_vtag = ntohs(len); 3194 break; 3195 case OP_RXCHKSVLAN: 3196 sc_if->msk_vtag = ntohs(len); 3197 break; 3198 case OP_RXSTAT: 3199 if ((sc_if->msk_ifp->if_flags & IFF_RUNNING) == 0) 3200 break; 3201 #ifdef MSK_JUMBO 3202 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3203 msk_jumbo_rxeof(sc_if, status, len); 3204 else 3205 #endif 3206 msk_rxeof(sc_if, status, len); 3207 rxprog++; 3208 /* 3209 * Because there is no way to sync single Rx LE 3210 * put the DMA sync operation off until the end of 3211 * event processing. 3212 */ 3213 rxput[port]++; 3214 /* Update prefetch unit if we've passed water mark. */ 3215 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3216 msk_rxput(sc_if); 3217 rxput[port] = 0; 3218 } 3219 break; 3220 case OP_TXINDEXLE: 3221 if (sc->msk_if[MSK_PORT_A] != NULL) { 3222 msk_txeof(sc->msk_if[MSK_PORT_A], 3223 status & STLE_TXA1_MSKL); 3224 } 3225 if (sc->msk_if[MSK_PORT_B] != NULL) { 3226 msk_txeof(sc->msk_if[MSK_PORT_B], 3227 ((status & STLE_TXA2_MSKL) >> 3228 STLE_TXA2_SHIFTL) | 3229 ((len & STLE_TXA2_MSKH) << 3230 STLE_TXA2_SHIFTH)); 3231 } 3232 break; 3233 default: 3234 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3235 control & STLE_OP_MASK); 3236 break; 3237 } 3238 MSK_INC(cons, MSK_STAT_RING_CNT); 3239 if (rxprog > sc->msk_process_limit) 3240 break; 3241 } 3242 3243 sc->msk_stat_cons = cons; 3244 /* XXX We should sync status LEs here. See above notes. */ 3245 3246 if (rxput[MSK_PORT_A] > 0) 3247 msk_rxput(sc->msk_if[MSK_PORT_A]); 3248 if (rxput[MSK_PORT_B] > 0) 3249 msk_rxput(sc->msk_if[MSK_PORT_B]); 3250 3251 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3252 } 3253 3254 /* Legacy interrupt handler for shared interrupt. */ 3255 static void 3256 mskc_intr(void *xsc) 3257 { 3258 struct msk_softc *sc; 3259 struct msk_if_softc *sc_if0, *sc_if1; 3260 struct ifnet *ifp0, *ifp1; 3261 uint32_t status; 3262 3263 sc = xsc; 3264 ASSERT_SERIALIZED(&sc->msk_serializer); 3265 3266 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3267 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3268 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3269 (status & sc->msk_intrmask) == 0) { 3270 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3271 return; 3272 } 3273 3274 sc_if0 = sc->msk_if[MSK_PORT_A]; 3275 sc_if1 = sc->msk_if[MSK_PORT_B]; 3276 ifp0 = ifp1 = NULL; 3277 if (sc_if0 != NULL) 3278 ifp0 = sc_if0->msk_ifp; 3279 if (sc_if1 != NULL) 3280 ifp1 = sc_if1->msk_ifp; 3281 3282 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3283 msk_intr_phy(sc_if0); 3284 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3285 msk_intr_phy(sc_if1); 3286 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3287 msk_intr_gmac(sc_if0); 3288 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3289 msk_intr_gmac(sc_if1); 3290 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3291 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3292 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3293 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3294 CSR_READ_4(sc, B0_IMSK); 3295 } 3296 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3297 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3298 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3299 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3300 CSR_READ_4(sc, B0_IMSK); 3301 } 3302 if ((status & Y2_IS_HW_ERR) != 0) 3303 mskc_intr_hwerr(sc); 3304 3305 while (mskc_handle_events(sc) != 0) 3306 ; 3307 if ((status & Y2_IS_STAT_BMU) != 0) 3308 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3309 3310 /* Reenable interrupts. */ 3311 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3312 3313 if (ifp0 != NULL && (ifp0->if_flags & IFF_RUNNING) != 0 && 3314 !ifq_is_empty(&ifp0->if_snd)) 3315 if_devstart(ifp0); 3316 if (ifp1 != NULL && (ifp1->if_flags & IFF_RUNNING) != 0 && 3317 !ifq_is_empty(&ifp1->if_snd)) 3318 if_devstart(ifp1); 3319 } 3320 3321 static void 3322 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3323 { 3324 struct msk_softc *sc = sc_if->msk_softc; 3325 struct ifnet *ifp = sc_if->msk_ifp; 3326 3327 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3328 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3329 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3330 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3331 TX_STFW_ENA); 3332 } else { 3333 if (ifp->if_mtu > ETHERMTU) { 3334 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3335 CSR_WRITE_4(sc, 3336 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3337 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3338 /* Disable Store & Forward mode for Tx. */ 3339 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3340 TX_STFW_DIS); 3341 } else { 3342 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3343 TX_STFW_ENA); 3344 } 3345 } 3346 } 3347 3348 static void 3349 msk_init(void *xsc) 3350 { 3351 struct msk_if_softc *sc_if = xsc; 3352 struct msk_softc *sc = sc_if->msk_softc; 3353 struct ifnet *ifp = sc_if->msk_ifp; 3354 struct mii_data *mii; 3355 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3356 uint16_t gmac; 3357 uint32_t reg; 3358 int error, i; 3359 3360 ASSERT_SERIALIZED(ifp->if_serializer); 3361 3362 mii = device_get_softc(sc_if->msk_miibus); 3363 3364 error = 0; 3365 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3366 msk_stop(sc_if); 3367 3368 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN; 3369 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3370 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3371 /* 3372 * In Yukon EC Ultra, TSO & checksum offload is not 3373 * supported for jumbo frame. 3374 */ 3375 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 3376 ifp->if_capenable &= ~IFCAP_TXCSUM; 3377 } 3378 3379 /* GMAC Control reset. */ 3380 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3381 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3382 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3383 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3384 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 3385 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3386 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3387 GMC_BYP_RETR_ON); 3388 } 3389 3390 /* 3391 * Initialize GMAC first such that speed/duplex/flow-control 3392 * parameters are renegotiated when interface is brought up. 3393 */ 3394 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3395 3396 /* Dummy read the Interrupt Source Register. */ 3397 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3398 3399 /* Set MIB Clear Counter Mode. */ 3400 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3401 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3402 /* Read all MIB Counters with Clear Mode set. */ 3403 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3404 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3405 /* Clear MIB Clear Counter Mode. */ 3406 gmac &= ~GM_PAR_MIB_CLR; 3407 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3408 3409 /* Disable FCS. */ 3410 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3411 3412 /* Setup Transmit Control Register. */ 3413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3414 3415 /* Setup Transmit Flow Control Register. */ 3416 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3417 3418 /* Setup Transmit Parameter Register. */ 3419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3420 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3421 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3422 3423 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3424 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3425 3426 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3427 gmac |= GM_SMOD_JUMBO_ENA; 3428 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3429 3430 /* Set station address. */ 3431 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3432 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3433 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3434 eaddr[i]); 3435 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3436 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3437 eaddr[i]); 3438 3439 /* Disable interrupts for counter overflows. */ 3440 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3441 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3442 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3443 3444 /* Configure Rx MAC FIFO. */ 3445 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3446 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3447 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3448 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3449 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3450 reg |= GMF_RX_OVER_ON; 3451 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3452 3453 /* Set receive filter. */ 3454 msk_rxfilter(sc_if); 3455 3456 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3457 /* Clear flush mask - HW bug. */ 3458 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3459 } else { 3460 /* Flush Rx MAC FIFO on any flow control or error. */ 3461 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3462 GMR_FS_ANY_ERR); 3463 } 3464 3465 /* 3466 * Set Rx FIFO flush threshold to 64 bytes 1 FIFO word 3467 * due to hardware hang on receipt of pause frames. 3468 */ 3469 reg = RX_GMF_FL_THR_DEF + 1; 3470 /* Another magic for Yukon FE+ - From Linux. */ 3471 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3472 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3473 reg = 0x178; 3474 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3475 3476 3477 /* Configure Tx MAC FIFO. */ 3478 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3479 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3480 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3481 3482 /* Configure hardware VLAN tag insertion/stripping. */ 3483 msk_setvlan(sc_if, ifp); 3484 3485 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3486 /* Set Rx Pause threshould. */ 3487 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3488 MSK_ECU_LLPP); 3489 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3490 MSK_ECU_ULPP); 3491 /* Configure store-and-forward for Tx. */ 3492 msk_set_tx_stfwd(sc_if); 3493 } 3494 3495 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3496 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3497 /* Disable dynamic watermark - from Linux. */ 3498 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3499 reg &= ~0x03; 3500 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3501 } 3502 3503 /* 3504 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3505 * arbiter as we don't use Sync Tx queue. 3506 */ 3507 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3508 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3509 /* Enable the RAM Interface Arbiter. */ 3510 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3511 3512 /* Setup RAM buffer. */ 3513 msk_set_rambuffer(sc_if); 3514 3515 /* Disable Tx sync Queue. */ 3516 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3517 3518 /* Setup Tx Queue Bus Memory Interface. */ 3519 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3520 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3521 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3522 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3523 switch (sc->msk_hw_id) { 3524 case CHIP_ID_YUKON_EC_U: 3525 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3526 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3527 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3528 MSK_ECU_TXFF_LEV); 3529 } 3530 break; 3531 case CHIP_ID_YUKON_EX: 3532 /* 3533 * Yukon Extreme seems to have silicon bug for 3534 * automatic Tx checksum calculation capability. 3535 */ 3536 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) { 3537 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3538 F_TX_CHK_AUTO_OFF); 3539 } 3540 break; 3541 } 3542 3543 /* Setup Rx Queue Bus Memory Interface. */ 3544 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3545 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3546 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3547 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3548 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3549 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3550 /* MAC Rx RAM Read is controlled by hardware. */ 3551 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3552 } 3553 3554 msk_set_prefetch(sc, sc_if->msk_txq, 3555 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3556 msk_init_tx_ring(sc_if); 3557 3558 /* Disable Rx checksum offload and RSS hash. */ 3559 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3560 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3561 #ifdef MSK_JUMBO 3562 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3563 msk_set_prefetch(sc, sc_if->msk_rxq, 3564 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3565 MSK_JUMBO_RX_RING_CNT - 1); 3566 error = msk_init_jumbo_rx_ring(sc_if); 3567 } else 3568 #endif 3569 { 3570 msk_set_prefetch(sc, sc_if->msk_rxq, 3571 sc_if->msk_rdata.msk_rx_ring_paddr, 3572 MSK_RX_RING_CNT - 1); 3573 error = msk_init_rx_ring(sc_if); 3574 } 3575 if (error != 0) { 3576 device_printf(sc_if->msk_if_dev, 3577 "initialization failed: no memory for Rx buffers\n"); 3578 msk_stop(sc_if); 3579 return; 3580 } 3581 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3582 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 3583 /* Disable flushing of non-ASF packets. */ 3584 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3585 GMF_RX_MACSEC_FLUSH_OFF); 3586 } 3587 3588 /* Configure interrupt handling. */ 3589 if (sc_if->msk_port == MSK_PORT_A) { 3590 sc->msk_intrmask |= Y2_IS_PORT_A; 3591 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3592 } else { 3593 sc->msk_intrmask |= Y2_IS_PORT_B; 3594 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3595 } 3596 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3597 CSR_READ_4(sc, B0_HWE_IMSK); 3598 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3599 CSR_READ_4(sc, B0_IMSK); 3600 3601 sc_if->msk_link = 0; 3602 mii_mediachg(mii); 3603 3604 mskc_set_imtimer(sc); 3605 3606 ifp->if_flags |= IFF_RUNNING; 3607 ifq_clr_oactive(&ifp->if_snd); 3608 3609 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3610 } 3611 3612 static void 3613 msk_set_rambuffer(struct msk_if_softc *sc_if) 3614 { 3615 struct msk_softc *sc; 3616 int ltpp, utpp; 3617 3618 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3619 return; 3620 3621 sc = sc_if->msk_softc; 3622 3623 /* Setup Rx Queue. */ 3624 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3625 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3626 sc->msk_rxqstart[sc_if->msk_port] / 8); 3627 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3628 sc->msk_rxqend[sc_if->msk_port] / 8); 3629 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3630 sc->msk_rxqstart[sc_if->msk_port] / 8); 3631 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3632 sc->msk_rxqstart[sc_if->msk_port] / 8); 3633 3634 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3635 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3636 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3637 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3638 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3639 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3640 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3641 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3642 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3643 3644 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3645 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3646 3647 /* Setup Tx Queue. */ 3648 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3649 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3650 sc->msk_txqstart[sc_if->msk_port] / 8); 3651 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3652 sc->msk_txqend[sc_if->msk_port] / 8); 3653 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3654 sc->msk_txqstart[sc_if->msk_port] / 8); 3655 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3656 sc->msk_txqstart[sc_if->msk_port] / 8); 3657 /* Enable Store & Forward for Tx side. */ 3658 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3659 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3660 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3661 } 3662 3663 static void 3664 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3665 uint32_t count) 3666 { 3667 3668 /* Reset the prefetch unit. */ 3669 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3670 PREF_UNIT_RST_SET); 3671 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3672 PREF_UNIT_RST_CLR); 3673 /* Set LE base address. */ 3674 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3675 MSK_ADDR_LO(addr)); 3676 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3677 MSK_ADDR_HI(addr)); 3678 /* Set the list last index. */ 3679 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3680 count); 3681 /* Turn on prefetch unit. */ 3682 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3683 PREF_UNIT_OP_ON); 3684 /* Dummy read to ensure write. */ 3685 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3686 } 3687 3688 static void 3689 msk_stop(struct msk_if_softc *sc_if) 3690 { 3691 struct msk_softc *sc = sc_if->msk_softc; 3692 struct ifnet *ifp = sc_if->msk_ifp; 3693 struct msk_txdesc *txd; 3694 struct msk_rxdesc *rxd; 3695 #ifdef MSK_JUMBO 3696 struct msk_rxdesc *jrxd; 3697 #endif 3698 uint32_t val; 3699 int i; 3700 3701 ASSERT_SERIALIZED(ifp->if_serializer); 3702 3703 callout_stop(&sc_if->msk_tick_ch); 3704 ifp->if_timer = 0; 3705 3706 /* Disable interrupts. */ 3707 if (sc_if->msk_port == MSK_PORT_A) { 3708 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3709 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3710 } else { 3711 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3712 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3713 } 3714 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3715 CSR_READ_4(sc, B0_HWE_IMSK); 3716 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3717 CSR_READ_4(sc, B0_IMSK); 3718 3719 /* Disable Tx/Rx MAC. */ 3720 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3721 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3722 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3723 /* Read again to ensure writing. */ 3724 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3725 3726 /* Stop Tx BMU. */ 3727 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3728 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3729 for (i = 0; i < MSK_TIMEOUT; i++) { 3730 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3731 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3732 BMU_STOP); 3733 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3734 } else 3735 break; 3736 DELAY(1); 3737 } 3738 if (i == MSK_TIMEOUT) 3739 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3740 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3741 RB_RST_SET | RB_DIS_OP_MD); 3742 3743 /* Disable all GMAC interrupt. */ 3744 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3745 /* Disable PHY interrupt. */ 3746 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3747 3748 /* Disable the RAM Interface Arbiter. */ 3749 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3750 3751 /* Reset the PCI FIFO of the async Tx queue */ 3752 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3753 BMU_RST_SET | BMU_FIFO_RST); 3754 3755 /* Reset the Tx prefetch units. */ 3756 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3757 PREF_UNIT_RST_SET); 3758 3759 /* Reset the RAM Buffer async Tx queue. */ 3760 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3761 3762 /* Reset Tx MAC FIFO. */ 3763 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3764 /* Set Pause Off. */ 3765 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3766 3767 /* 3768 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3769 * reach the end of packet and since we can't make sure that we have 3770 * incoming data, we must reset the BMU while it is not during a DMA 3771 * transfer. Since it is possible that the Rx path is still active, 3772 * the Rx RAM buffer will be stopped first, so any possible incoming 3773 * data will not trigger a DMA. After the RAM buffer is stopped, the 3774 * BMU is polled until any DMA in progress is ended and only then it 3775 * will be reset. 3776 */ 3777 3778 /* Disable the RAM Buffer receive queue. */ 3779 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3780 for (i = 0; i < MSK_TIMEOUT; i++) { 3781 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3782 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3783 break; 3784 DELAY(1); 3785 } 3786 if (i == MSK_TIMEOUT) 3787 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3788 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3789 BMU_RST_SET | BMU_FIFO_RST); 3790 /* Reset the Rx prefetch unit. */ 3791 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3792 PREF_UNIT_RST_SET); 3793 /* Reset the RAM Buffer receive queue. */ 3794 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3795 /* Reset Rx MAC FIFO. */ 3796 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3797 3798 /* Free Rx and Tx mbufs still in the queues. */ 3799 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3800 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3801 if (rxd->rx_m != NULL) { 3802 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3803 rxd->rx_dmamap); 3804 m_freem(rxd->rx_m); 3805 rxd->rx_m = NULL; 3806 } 3807 } 3808 #ifdef MSK_JUMBO 3809 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3810 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3811 if (jrxd->rx_m != NULL) { 3812 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3813 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3814 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3815 jrxd->rx_dmamap); 3816 m_freem(jrxd->rx_m); 3817 jrxd->rx_m = NULL; 3818 } 3819 } 3820 #endif 3821 for (i = 0; i < MSK_TX_RING_CNT; i++) { 3822 txd = &sc_if->msk_cdata.msk_txdesc[i]; 3823 if (txd->tx_m != NULL) { 3824 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 3825 txd->tx_dmamap); 3826 m_freem(txd->tx_m); 3827 txd->tx_m = NULL; 3828 } 3829 } 3830 3831 /* 3832 * Mark the interface down. 3833 */ 3834 ifp->if_flags &= ~IFF_RUNNING; 3835 ifq_clr_oactive(&ifp->if_snd); 3836 sc_if->msk_link = 0; 3837 } 3838 3839 static int 3840 mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS) 3841 { 3842 return sysctl_int_range(oidp, arg1, arg2, req, 3843 MSK_PROC_MIN, MSK_PROC_MAX); 3844 } 3845 3846 static int 3847 mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS) 3848 { 3849 struct msk_softc *sc = arg1; 3850 struct lwkt_serialize *serializer = &sc->msk_serializer; 3851 int error = 0, v; 3852 3853 lwkt_serialize_enter(serializer); 3854 3855 v = sc->msk_intr_rate; 3856 error = sysctl_handle_int(oidp, &v, 0, req); 3857 if (error || req->newptr == NULL) 3858 goto back; 3859 if (v < 0) { 3860 error = EINVAL; 3861 goto back; 3862 } 3863 3864 if (sc->msk_intr_rate != v) { 3865 int flag = 0, i; 3866 3867 sc->msk_intr_rate = v; 3868 for (i = 0; i < 2; ++i) { 3869 if (sc->msk_if[i] != NULL) { 3870 flag |= sc->msk_if[i]-> 3871 arpcom.ac_if.if_flags & IFF_RUNNING; 3872 } 3873 } 3874 if (flag) 3875 mskc_set_imtimer(sc); 3876 } 3877 back: 3878 lwkt_serialize_exit(serializer); 3879 return error; 3880 } 3881 3882 static int 3883 msk_dmamem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag, 3884 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap) 3885 { 3886 struct msk_if_softc *sc_if = device_get_softc(dev); 3887 bus_dmamem_t dmem; 3888 int error; 3889 3890 error = bus_dmamem_coherent(sc_if->msk_cdata.msk_parent_tag, 3891 MSK_RING_ALIGN, 0, 3892 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3893 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3894 if (error) { 3895 device_printf(dev, "can't create coherent DMA memory\n"); 3896 return error; 3897 } 3898 3899 *dtag = dmem.dmem_tag; 3900 *dmap = dmem.dmem_map; 3901 *addr = dmem.dmem_addr; 3902 *paddr = dmem.dmem_busaddr; 3903 3904 return 0; 3905 } 3906 3907 static void 3908 msk_dmamem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 3909 { 3910 if (dtag != NULL) { 3911 bus_dmamap_unload(dtag, dmap); 3912 bus_dmamem_free(dtag, addr, dmap); 3913 bus_dma_tag_destroy(dtag); 3914 } 3915 } 3916 3917 static void 3918 mskc_set_imtimer(struct msk_softc *sc) 3919 { 3920 if (sc->msk_intr_rate > 0) { 3921 /* 3922 * XXX myk(4) seems to use 125MHz for EC/FE/XL 3923 * and 78.125MHz for rest of chip types 3924 */ 3925 CSR_WRITE_4(sc, B2_IRQM_INI, 3926 MSK_USECS(sc, 1000000 / sc->msk_intr_rate)); 3927 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3928 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_START); 3929 } else { 3930 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_STOP); 3931 } 3932 } 3933