xref: /dragonfly/sys/dev/netif/sn/if_sn.c (revision 3a73a0c4)
1 /*
2  * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *      This product includes software developed by Gardner Buchanan.
16  * 4. The name of Gardner Buchanan may not be used to endorse or promote
17  *    products derived from this software without specific prior written
18  *    permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  *
31  *   $FreeBSD: src/sys/dev/sn/if_sn.c,v 1.7.2.3 2001/02/04 04:38:38 toshi Exp $
32  */
33 
34 /*
35  * This is a driver for SMC's 9000 series of Ethernet adapters.
36  *
37  * This FreeBSD driver is derived from the smc9194 Linux driver by
38  * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
39  * This driver also shamelessly borrows from the FreeBSD ep driver
40  * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
41  * All rights reserved.
42  *
43  * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
44  * PC.  It is adapted from Erik Stahlman's Linux driver which worked
45  * with his EFA Info*Express SVC VLB adaptor.  According to SMC's databook,
46  * it will work for the entire SMC 9xxx series. (Ha Ha)
47  *
48  * "Features" of the SMC chip:
49  *   4608 byte packet memory. (for the 91C92.  Others have more)
50  *   EEPROM for configuration
51  *   AUI/TP selection
52  *
53  * Authors:
54  *      Erik Stahlman                   erik@vt.edu
55  *      Herb Peyerl                     hpeyerl@novatel.ca
56  *      Andres Vega Garcia              avega@sophia.inria.fr
57  *      Serge Babkin                    babkin@hq.icb.chel.su
58  *      Gardner Buchanan                gbuchanan@shl.com
59  *
60  * Sources:
61  *    o   SMC databook
62  *    o   "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
63  *    o   "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
64  *
65  * Known Bugs:
66  *    o   The hardware multicast filter isn't used yet.
67  *    o   Setting of the hardware address isn't supported.
68  *    o   Hardware padding isn't used.
69  */
70 
71 /*
72  * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73  *
74  * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75  *                       BSD-nomads, Tokyo, Japan.
76  */
77 /*
78  * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79  * Special thanks to itojun@itojun.org
80  */
81 
82 #undef	SN_DEBUG	/* (by hosokawa) */
83 
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/kernel.h>
87 #include <sys/interrupt.h>
88 #include <sys/errno.h>
89 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/mbuf.h>
92 #include <sys/socket.h>
93 #include <sys/syslog.h>
94 #include <sys/serialize.h>
95 #include <sys/module.h>
96 #include <sys/bus.h>
97 #include <sys/rman.h>
98 
99 #include <net/ethernet.h>
100 #include <net/if.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/if_dl.h>
104 #include <net/if_types.h>
105 #include <net/if_mib.h>
106 
107 #include <net/bpf.h>
108 #include <net/bpfdesc.h>
109 
110 #include <machine/clock.h>
111 
112 #include "if_snreg.h"
113 #include "if_snvar.h"
114 
115 /* Exported variables */
116 devclass_t sn_devclass;
117 
118 static int snioctl(struct ifnet * ifp, u_long, caddr_t, struct ucred *);
119 
120 static void snresume(struct ifnet *);
121 
122 void sninit(void *);
123 void snread(struct ifnet *);
124 void snreset(struct sn_softc *);
125 void snstart(struct ifnet *, struct ifaltq_subque *);
126 void snstop(struct sn_softc *);
127 void snwatchdog(struct ifnet *);
128 
129 static void sn_setmcast(struct sn_softc *);
130 static int sn_getmcf(struct arpcom *ac, u_char *mcf);
131 static u_int smc_crc(u_char *);
132 
133 DECLARE_DUMMY_MODULE(if_sn);
134 
135 /* I (GB) have been unlucky getting the hardware padding
136  * to work properly.
137  */
138 #define SW_PAD
139 
140 static const char *chip_ids[15] = {
141 	NULL, NULL, NULL,
142 	 /* 3 */ "SMC91C90/91C92",
143 	 /* 4 */ "SMC91C94",
144 	 /* 5 */ "SMC91C95",
145 	NULL,
146 	 /* 7 */ "SMC91C100",
147 	 /* 8 */ "SMC91C100FD",
148 	NULL, NULL, NULL,
149 	NULL, NULL, NULL
150 };
151 
152 int
sn_attach(device_t dev)153 sn_attach(device_t dev)
154 {
155 	struct sn_softc *sc = device_get_softc(dev);
156 	struct ifnet   *ifp = &sc->arpcom.ac_if;
157 	u_short         i;
158 	u_char         *p;
159 	int             rev;
160 	u_short         address;
161 	int		j;
162 	int		error;
163 
164 	sn_activate(dev);
165 
166 	snstop(sc);
167 
168 	sc->dev = dev;
169 	sc->pages_wanted = -1;
170 
171 	device_printf(dev, " ");
172 
173 	SMC_SELECT_BANK(3);
174 	rev = inw(BASE + REVISION_REG_W);
175 	if (chip_ids[(rev >> 4) & 0xF])
176 		kprintf("%s ", chip_ids[(rev >> 4) & 0xF]);
177 
178 	SMC_SELECT_BANK(1);
179 	i = inw(BASE + CONFIG_REG_W);
180 	kprintf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
181 
182 	if (sc->pccard_enaddr)
183 		for (j = 0; j < 3; j++) {
184 			u_short	w;
185 
186 			w = (u_short)sc->arpcom.ac_enaddr[j * 2] |
187 				(((u_short)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8);
188 			outw(BASE + IAR_ADDR0_REG_W + j * 2, w);
189 		}
190 
191 	/*
192 	 * Read the station address from the chip. The MAC address is bank 1,
193 	 * regs 4 - 9
194 	 */
195 	SMC_SELECT_BANK(1);
196 	p = (u_char *) & sc->arpcom.ac_enaddr;
197 	for (i = 0; i < 6; i += 2) {
198 		address = inw(BASE + IAR_ADDR0_REG_W + i);
199 		p[i + 1] = address >> 8;
200 		p[i] = address & 0xFF;
201 	}
202 	ifp->if_softc = sc;
203 	if_initname(ifp, "sn", device_get_unit(dev));
204 	ifp->if_mtu = ETHERMTU;
205 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
206 	ifp->if_start = snstart;
207 	ifp->if_ioctl = snioctl;
208 	ifp->if_watchdog = snwatchdog;
209 	ifp->if_init = sninit;
210 	ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
211 	ifq_set_ready(&ifp->if_snd);
212 	ifp->if_timer = 0;
213 
214 	ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
215 
216 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq_res));
217 
218 	error = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE,
219 			       sn_intr, sc, &sc->intrhand,
220 			       ifp->if_serializer);
221 	if (error) {
222 		ether_ifdetach(ifp);
223 		sn_deactivate(dev);
224 		return error;
225 	}
226 
227 	return 0;
228 }
229 
230 
231 /*
232  * Reset and initialize the chip
233  */
234 void
sninit(void * xsc)235 sninit(void *xsc)
236 {
237 	struct sn_softc *sc = xsc;
238 	struct ifnet *ifp = &sc->arpcom.ac_if;
239 	int             flags;
240 	int             mask;
241 
242 	/*
243 	 * This resets the registers mostly to defaults, but doesn't affect
244 	 * EEPROM.  After the reset cycle, we pause briefly for the chip to
245 	 * be happy.
246 	 */
247 	SMC_SELECT_BANK(0);
248 	outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET);
249 	SMC_DELAY();
250 	outw(BASE + RECV_CONTROL_REG_W, 0x0000);
251 	SMC_DELAY();
252 	SMC_DELAY();
253 
254 	outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
255 
256 	/*
257 	 * Set the control register to automatically release succesfully
258 	 * transmitted packets (making the best use out of our limited
259 	 * memory) and to enable the EPH interrupt on certain TX errors.
260 	 */
261 	SMC_SELECT_BANK(1);
262 	outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
263 				    CTR_CR_ENABLE | CTR_LE_ENABLE));
264 
265 	/* Set squelch level to 240mV (default 480mV) */
266 	flags = inw(BASE + CONFIG_REG_W);
267 	flags |= CR_SET_SQLCH;
268 	outw(BASE + CONFIG_REG_W, flags);
269 
270 	/*
271 	 * Reset the MMU and wait for it to be un-busy.
272 	 */
273 	SMC_SELECT_BANK(2);
274 	outw(BASE + MMU_CMD_REG_W, MMUCR_RESET);
275 	while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
276 		;
277 
278 	/*
279 	 * Disable all interrupts
280 	 */
281 	outb(BASE + INTR_MASK_REG_B, 0x00);
282 
283 	sn_setmcast(sc);
284 
285 	/*
286 	 * Set the transmitter control.  We want it enabled.
287 	 */
288 	flags = TCR_ENABLE;
289 
290 #ifndef SW_PAD
291 	/*
292 	 * I (GB) have been unlucky getting this to work.
293 	 */
294 	flags |= TCR_PAD_ENABLE;
295 #endif	/* SW_PAD */
296 
297 	outw(BASE + TXMIT_CONTROL_REG_W, flags);
298 
299 
300 	/*
301 	 * Now, enable interrupts
302 	 */
303 	SMC_SELECT_BANK(2);
304 
305 	mask = IM_EPH_INT |
306 		IM_RX_OVRN_INT |
307 		IM_RCV_INT |
308 		IM_TX_INT;
309 
310 	outb(BASE + INTR_MASK_REG_B, mask);
311 	sc->intr_mask = mask;
312 	sc->pages_wanted = -1;
313 
314 
315 	/*
316 	 * Mark the interface running but not active.
317 	 */
318 	ifp->if_flags |= IFF_RUNNING;
319 	ifq_clr_oactive(&ifp->if_snd);
320 
321 	/*
322 	 * Attempt to push out any waiting packets.
323 	 */
324 	if_devstart(ifp);
325 }
326 
327 
328 void
snstart(struct ifnet * ifp,struct ifaltq_subque * ifsq)329 snstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
330 {
331 	struct sn_softc *sc = ifp->if_softc;
332 	u_int  len;
333 	struct mbuf *m;
334 	struct mbuf    *top;
335 	int             pad;
336 	int             mask;
337 	u_short         length;
338 	u_short         numPages;
339 	u_char          packet_no;
340 	int             time_out;
341 
342 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
343 
344 	if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
345 		return;
346 
347 	if (sc->pages_wanted != -1) {
348 		/* XXX should never happen */
349 		kprintf("%s: snstart() while memory allocation pending\n",
350 		       ifp->if_xname);
351 		ifq_set_oactive(&ifp->if_snd);
352 		return;
353 	}
354 startagain:
355 
356 	/*
357 	 * Sneak a peek at the next packet
358 	 */
359 	m = ifq_dequeue(&ifp->if_snd);
360 	if (m == NULL)
361 		return;
362 
363 	/*
364 	 * Compute the frame length and set pad to give an overall even
365 	 * number of bytes.  Below we assume that the packet length is even.
366 	 */
367 	for (len = 0, top = m; m; m = m->m_next)
368 		len += m->m_len;
369 
370 	pad = (len & 1);
371 
372 	/*
373 	 * We drop packets that are too large. Perhaps we should truncate
374 	 * them instead?
375 	 */
376 	if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
377 		kprintf("%s: large packet discarded (A)\n", ifp->if_xname);
378 		IFNET_STAT_INC(&sc->arpcom.ac_if, oerrors, 1);
379 		m_freem(top);
380 		goto readcheck;
381 	}
382 #ifdef SW_PAD
383 
384 	/*
385 	 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
386 	 */
387 	if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
388 		pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
389 
390 #endif	/* SW_PAD */
391 
392 	length = pad + len;
393 
394 	/*
395 	 * The MMU wants the number of pages to be the number of 256 byte
396 	 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
397 	 * include space for the status word, byte count and control bytes in
398 	 * the allocation request.
399 	 */
400 	numPages = (length + 6) >> 8;
401 
402 
403 	/*
404 	 * Now, try to allocate the memory
405 	 */
406 	SMC_SELECT_BANK(2);
407 	outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
408 
409 	/*
410 	 * Wait a short amount of time to see if the allocation request
411 	 * completes.  Otherwise, I enable the interrupt and wait for
412 	 * completion asyncronously.
413 	 */
414 
415 	time_out = MEMORY_WAIT_TIME;
416 	do {
417 		if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT)
418 			break;
419 	} while (--time_out);
420 
421 	if (!time_out) {
422 
423 		/*
424 		 * No memory now.  Oh well, wait until the chip finds memory
425 		 * later.   Remember how many pages we were asking for and
426 		 * enable the allocation completion interrupt. Also set a
427 		 * watchdog in case  we miss the interrupt. We mark the
428 		 * interface active since there is no point in attempting an
429 		 * snstart() until after the memory is available.
430 		 */
431 		mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT;
432 		outb(BASE + INTR_MASK_REG_B, mask);
433 		sc->intr_mask = mask;
434 
435 		ifp->if_timer = 1;
436 		ifq_set_oactive(&ifp->if_snd);
437 		sc->pages_wanted = numPages;
438 		ifq_prepend(&ifp->if_snd, top);
439 
440 		return;
441 	}
442 	/*
443 	 * The memory allocation completed.  Check the results.
444 	 */
445 	packet_no = inb(BASE + ALLOC_RESULT_REG_B);
446 	if (packet_no & ARR_FAILED) {
447 		kprintf("%s: Memory allocation failed\n", ifp->if_xname);
448 		ifq_prepend(&ifp->if_snd, top);
449 		goto startagain;
450 	}
451 	/*
452 	 * We have a packet number, so tell the card to use it.
453 	 */
454 	outb(BASE + PACKET_NUM_REG_B, packet_no);
455 
456 	/*
457 	 * Point to the beginning of the packet
458 	 */
459 	outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
460 
461 	/*
462 	 * Send the packet length (+6 for status, length and control byte)
463 	 * and the status word (set to zeros)
464 	 */
465 	outw(BASE + DATA_REG_W, 0);
466 	outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
467 	outb(BASE + DATA_REG_B, (length + 6) >> 8);
468 
469 	/*
470 	 * Push out the data to the card.
471 	 */
472 	for (m = top; m != NULL; m = m->m_next) {
473 
474 		/*
475 		 * Push out words.
476 		 */
477 		outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
478 
479 		/*
480 		 * Push out remaining byte.
481 		 */
482 		if (m->m_len & 1)
483 			outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
484 	}
485 
486 	/*
487 	 * Push out padding.
488 	 */
489 	while (pad > 1) {
490 		outw(BASE + DATA_REG_W, 0);
491 		pad -= 2;
492 	}
493 	if (pad)
494 		outb(BASE + DATA_REG_B, 0);
495 
496 	/*
497 	 * Push out control byte and unused packet byte The control byte is 0
498 	 * meaning the packet is even lengthed and no special CRC handling is
499 	 * desired.
500 	 */
501 	outw(BASE + DATA_REG_W, 0);
502 
503 	/*
504 	 * Enable the interrupts and let the chipset deal with it Also set a
505 	 * watchdog in case we miss the interrupt.
506 	 */
507 	mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
508 	outb(BASE + INTR_MASK_REG_B, mask);
509 	sc->intr_mask = mask;
510 
511 	outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
512 
513 	ifq_set_oactive(&ifp->if_snd);
514 	ifp->if_timer = 1;
515 
516 	BPF_MTAP(ifp, top);
517 
518 	IFNET_STAT_INC(ifp, opackets, 1);
519 	m_freem(top);
520 
521 readcheck:
522 
523 	/*
524 	 * Is another packet coming in?  We don't want to overflow the tiny
525 	 * RX FIFO.  If nothing has arrived then attempt to queue another
526 	 * transmit packet.
527 	 */
528 	if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY)
529 		goto startagain;
530 }
531 
532 
533 
534 /* Resume a packet transmit operation after a memory allocation
535  * has completed.
536  *
537  * This is basically a hacked up copy of snstart() which handles
538  * a completed memory allocation the same way snstart() does.
539  * It then passes control to snstart to handle any other queued
540  * packets.
541  */
542 static void
snresume(struct ifnet * ifp)543 snresume(struct ifnet *ifp)
544 {
545 	struct sn_softc *sc = ifp->if_softc;
546 	u_int  len;
547 	struct mbuf *m;
548 	struct mbuf    *top;
549 	int             pad;
550 	int             mask;
551 	u_short         length;
552 	u_short         numPages;
553 	u_short         pages_wanted;
554 	u_char          packet_no;
555 
556 	if (sc->pages_wanted < 0)
557 		return;
558 
559 	pages_wanted = sc->pages_wanted;
560 	sc->pages_wanted = -1;
561 
562 	/*
563 	 * Sneak a peek at the next packet
564 	 */
565 	m = ifq_dequeue(&ifp->if_snd);
566 	if (m == NULL) {
567 		kprintf("%s: snresume() with nothing to send\n",
568 			ifp->if_xname);
569 		return;
570 	}
571 
572 	/*
573 	 * Compute the frame length and set pad to give an overall even
574 	 * number of bytes.  Below we assume that the packet length is even.
575 	 */
576 	for (len = 0, top = m; m; m = m->m_next)
577 		len += m->m_len;
578 
579 	pad = (len & 1);
580 
581 	/*
582 	 * We drop packets that are too large. Perhaps we should truncate
583 	 * them instead?
584 	 */
585 	if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
586 		kprintf("%s: large packet discarded (B)\n", ifp->if_xname);
587 		IFNET_STAT_INC(ifp, oerrors, 1);
588 		m_freem(top);
589 		return;
590 	}
591 #ifdef SW_PAD
592 
593 	/*
594 	 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
595 	 */
596 	if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
597 		pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
598 
599 #endif	/* SW_PAD */
600 
601 	length = pad + len;
602 
603 
604 	/*
605 	 * The MMU wants the number of pages to be the number of 256 byte
606 	 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
607 	 * include space for the status word, byte count and control bytes in
608 	 * the allocation request.
609 	 */
610 	numPages = (length + 6) >> 8;
611 
612 
613 	SMC_SELECT_BANK(2);
614 
615 	/*
616 	 * The memory allocation completed.  Check the results. If it failed,
617 	 * we simply set a watchdog timer and hope for the best.
618 	 */
619 	packet_no = inb(BASE + ALLOC_RESULT_REG_B);
620 	if (packet_no & ARR_FAILED) {
621 		kprintf("%s: Memory allocation failed.  Weird.\n", ifp->if_xname);
622 		ifp->if_timer = 1;
623 		ifq_prepend(&ifp->if_snd, top);
624 		goto try_start;
625 	}
626 	/*
627 	 * We have a packet number, so tell the card to use it.
628 	 */
629 	outb(BASE + PACKET_NUM_REG_B, packet_no);
630 
631 	/*
632 	 * Now, numPages should match the pages_wanted recorded when the
633 	 * memory allocation was initiated.
634 	 */
635 	if (pages_wanted != numPages) {
636 		kprintf("%s: memory allocation wrong size.  Weird.\n", ifp->if_xname);
637 		/*
638 		 * If the allocation was the wrong size we simply release the
639 		 * memory once it is granted. Wait for the MMU to be un-busy.
640 		 */
641 		while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
642 			;
643 		outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
644 
645 		ifq_prepend(&ifp->if_snd, top);
646 		return;
647 	}
648 	/*
649 	 * Point to the beginning of the packet
650 	 */
651 	outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
652 
653 	/*
654 	 * Send the packet length (+6 for status, length and control byte)
655 	 * and the status word (set to zeros)
656 	 */
657 	outw(BASE + DATA_REG_W, 0);
658 	outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
659 	outb(BASE + DATA_REG_B, (length + 6) >> 8);
660 
661 	/*
662 	 * Push out the data to the card.
663 	 */
664 	for (m = top; m != NULL; m = m->m_next) {
665 
666 		/*
667 		 * Push out words.
668 		 */
669 		outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
670 
671 		/*
672 		 * Push out remaining byte.
673 		 */
674 		if (m->m_len & 1)
675 			outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
676 	}
677 
678 	/*
679 	 * Push out padding.
680 	 */
681 	while (pad > 1) {
682 		outw(BASE + DATA_REG_W, 0);
683 		pad -= 2;
684 	}
685 	if (pad)
686 		outb(BASE + DATA_REG_B, 0);
687 
688 	/*
689 	 * Push out control byte and unused packet byte The control byte is 0
690 	 * meaning the packet is even lengthed and no special CRC handling is
691 	 * desired.
692 	 */
693 	outw(BASE + DATA_REG_W, 0);
694 
695 	/*
696 	 * Enable the interrupts and let the chipset deal with it Also set a
697 	 * watchdog in case we miss the interrupt.
698 	 */
699 	mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
700 	outb(BASE + INTR_MASK_REG_B, mask);
701 	sc->intr_mask = mask;
702 	outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
703 
704 	BPF_MTAP(ifp, top);
705 
706 	IFNET_STAT_INC(ifp, opackets, 1);
707 	m_freem(top);
708 
709 try_start:
710 
711 	/*
712 	 * Now pass control to snstart() to queue any additional packets
713 	 */
714 	ifq_clr_oactive(&ifp->if_snd);
715 	if_devstart(ifp);
716 
717 	/*
718 	 * We've sent something, so we're active.  Set a watchdog in case the
719 	 * TX_EMPTY interrupt is lost.
720 	 */
721 	ifq_set_oactive(&ifp->if_snd);
722 	ifp->if_timer = 1;
723 }
724 
725 
726 void
sn_intr(void * arg)727 sn_intr(void *arg)
728 {
729 	int             status, interrupts;
730 	struct sn_softc *sc = (struct sn_softc *) arg;
731 	struct ifnet   *ifp = &sc->arpcom.ac_if;
732 
733 	/*
734 	 * Chip state registers
735 	 */
736 	u_char          mask;
737 	u_char          packet_no;
738 	u_short         tx_status;
739 	u_short         card_stats;
740 
741 	/*
742 	 * Clear the watchdog.
743 	 */
744 	ifp->if_timer = 0;
745 
746 	SMC_SELECT_BANK(2);
747 
748 	/*
749 	 * Obtain the current interrupt mask and clear the hardware mask
750 	 * while servicing interrupts.
751 	 */
752 	mask = inb(BASE + INTR_MASK_REG_B);
753 	outb(BASE + INTR_MASK_REG_B, 0x00);
754 
755 	/*
756 	 * Get the set of interrupts which occurred and eliminate any which
757 	 * are masked.
758 	 */
759 	interrupts = inb(BASE + INTR_STAT_REG_B);
760 	status = interrupts & mask;
761 
762 	/*
763 	 * Now, process each of the interrupt types.
764 	 */
765 
766 	/*
767 	 * Receive Overrun.
768 	 */
769 	if (status & IM_RX_OVRN_INT) {
770 
771 		/*
772 		 * Acknowlege Interrupt
773 		 */
774 		SMC_SELECT_BANK(2);
775 		outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT);
776 
777 		IFNET_STAT_INC(&sc->arpcom.ac_if, ierrors, 1);
778 	}
779 	/*
780 	 * Got a packet.
781 	 */
782 	if (status & IM_RCV_INT) {
783 #if 1
784 		int             packet_number;
785 
786 		SMC_SELECT_BANK(2);
787 		packet_number = inw(BASE + FIFO_PORTS_REG_W);
788 
789 		if (packet_number & FIFO_REMPTY) {
790 
791 			/*
792 			 * we got called , but nothing was on the FIFO
793 			 */
794 			kprintf("sn: Receive interrupt with nothing on FIFO\n");
795 
796 			goto out;
797 		}
798 #endif
799 		snread(ifp);
800 	}
801 	/*
802 	 * An on-card memory allocation came through.
803 	 */
804 	if (status & IM_ALLOC_INT) {
805 
806 		/*
807 		 * Disable this interrupt.
808 		 */
809 		mask &= ~IM_ALLOC_INT;
810 		ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
811 		snresume(&sc->arpcom.ac_if);
812 	}
813 	/*
814 	 * TX Completion.  Handle a transmit error message. This will only be
815 	 * called when there is an error, because of the AUTO_RELEASE mode.
816 	 */
817 	if (status & IM_TX_INT) {
818 
819 		/*
820 		 * Acknowlege Interrupt
821 		 */
822 		SMC_SELECT_BANK(2);
823 		outb(BASE + INTR_ACK_REG_B, IM_TX_INT);
824 
825 		packet_no = inw(BASE + FIFO_PORTS_REG_W);
826 		packet_no &= FIFO_TX_MASK;
827 
828 		/*
829 		 * select this as the packet to read from
830 		 */
831 		outb(BASE + PACKET_NUM_REG_B, packet_no);
832 
833 		/*
834 		 * Position the pointer to the first word from this packet
835 		 */
836 		outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
837 
838 		/*
839 		 * Fetch the TX status word.  The value found here will be a
840 		 * copy of the EPH_STATUS_REG_W at the time the transmit
841 		 * failed.
842 		 */
843 		tx_status = inw(BASE + DATA_REG_W);
844 
845 		if (tx_status & EPHSR_TX_SUC) {
846 			device_printf(sc->dev,
847 			    "Successful packet caused interrupt\n");
848 		} else {
849 			IFNET_STAT_INC(&sc->arpcom.ac_if, oerrors, 1);
850 		}
851 
852 		if (tx_status & EPHSR_LATCOL)
853 			IFNET_STAT_INC(&sc->arpcom.ac_if, collisions, 1);
854 
855 		/*
856 		 * Some of these errors will have disabled transmit.
857 		 * Re-enable transmit now.
858 		 */
859 		SMC_SELECT_BANK(0);
860 
861 #ifdef SW_PAD
862 		outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE);
863 #else
864 		outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
865 #endif	/* SW_PAD */
866 
867 		/*
868 		 * kill the failed packet. Wait for the MMU to be un-busy.
869 		 */
870 		SMC_SELECT_BANK(2);
871 		while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
872 			;
873 		outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
874 
875 		/*
876 		 * Attempt to queue more transmits.
877 		 */
878 		ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
879 		if_devstart(&sc->arpcom.ac_if);
880 	}
881 	/*
882 	 * Transmit underrun.  We use this opportunity to update transmit
883 	 * statistics from the card.
884 	 */
885 	if (status & IM_TX_EMPTY_INT) {
886 
887 		/*
888 		 * Acknowlege Interrupt
889 		 */
890 		SMC_SELECT_BANK(2);
891 		outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT);
892 
893 		/*
894 		 * Disable this interrupt.
895 		 */
896 		mask &= ~IM_TX_EMPTY_INT;
897 
898 		SMC_SELECT_BANK(0);
899 		card_stats = inw(BASE + COUNTER_REG_W);
900 
901 		/*
902 		 * Single collisions
903 		 */
904 		IFNET_STAT_INC(&sc->arpcom.ac_if, collisions,
905 		    card_stats & ECR_COLN_MASK);
906 
907 		/*
908 		 * Multiple collisions
909 		 */
910 		IFNET_STAT_INC(&sc->arpcom.ac_if, collisions,
911 		    (card_stats & ECR_MCOLN_MASK) >> 4);
912 
913 		SMC_SELECT_BANK(2);
914 
915 		/*
916 		 * Attempt to enqueue some more stuff.
917 		 */
918 		ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
919 		if_devstart(&sc->arpcom.ac_if);
920 	}
921 	/*
922 	 * Some other error.  Try to fix it by resetting the adapter.
923 	 */
924 	if (status & IM_EPH_INT) {
925 		snstop(sc);
926 		sninit(sc);
927 	}
928 
929 out:
930 	/*
931 	 * Handled all interrupt sources.
932 	 */
933 
934 	SMC_SELECT_BANK(2);
935 
936 	/*
937 	 * Reestablish interrupts from mask which have not been deselected
938 	 * during this interrupt.  Note that the hardware mask, which was set
939 	 * to 0x00 at the start of this service routine, may have been
940 	 * updated by one or more of the interrupt handers and we must let
941 	 * those new interrupts stay enabled here.
942 	 */
943 	mask |= inb(BASE + INTR_MASK_REG_B);
944 	outb(BASE + INTR_MASK_REG_B, mask);
945 	sc->intr_mask = mask;
946 }
947 
948 void
snread(struct ifnet * ifp)949 snread(struct ifnet *ifp)
950 {
951         struct sn_softc *sc = ifp->if_softc;
952 	struct mbuf    *m;
953 	short           status;
954 	int             packet_number;
955 	u_short         packet_length;
956 	u_char         *data;
957 
958 	SMC_SELECT_BANK(2);
959 #if 0
960 	packet_number = inw(BASE + FIFO_PORTS_REG_W);
961 
962 	if (packet_number & FIFO_REMPTY) {
963 
964 		/*
965 		 * we got called , but nothing was on the FIFO
966 		 */
967 		kprintf("sn: Receive interrupt with nothing on FIFO\n");
968 		return;
969 	}
970 #endif
971 read_another:
972 
973 	/*
974 	 * Start reading from the start of the packet. Since PTR_RCV is set,
975 	 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
976 	 */
977 	outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
978 
979 	/*
980 	 * First two words are status and packet_length
981 	 */
982 	status = inw(BASE + DATA_REG_W);
983 	packet_length = inw(BASE + DATA_REG_W) & RLEN_MASK;
984 
985 	/*
986 	 * The packet length contains 3 extra words: status, length, and a
987 	 * extra word with the control byte.
988 	 */
989 	packet_length -= 6;
990 
991 	/*
992 	 * Account for receive errors and discard.
993 	 */
994 	if (status & RS_ERRORS) {
995 		IFNET_STAT_INC(ifp, ierrors, 1);
996 		goto out;
997 	}
998 	/*
999 	 * A packet is received.
1000 	 */
1001 
1002 	/*
1003 	 * Adjust for odd-length packet.
1004 	 */
1005 	if (status & RS_ODDFRAME)
1006 		packet_length++;
1007 
1008 	/*
1009 	 * Allocate a header mbuf from the kernel.
1010 	 */
1011 	MGETHDR(m, M_NOWAIT, MT_DATA);
1012 	if (m == NULL)
1013 		goto out;
1014 
1015 	m->m_pkthdr.rcvif = ifp;
1016 	m->m_pkthdr.len = m->m_len = packet_length;
1017 
1018 	/*
1019 	 * Attach an mbuf cluster
1020 	 */
1021 	MCLGET(m, M_NOWAIT);
1022 
1023 	/*
1024 	 * Insist on getting a cluster
1025 	 */
1026 	if ((m->m_flags & M_EXT) == 0) {
1027 		m_freem(m);
1028 		IFNET_STAT_INC(ifp, ierrors, 1);
1029 		kprintf("sn: snread() kernel memory allocation problem\n");
1030 		goto out;
1031 	}
1032 
1033 	/*
1034 	 * Get packet, including link layer address, from interface.
1035 	 */
1036 
1037 	data = mtod(m, u_char *);
1038 	insw(BASE + DATA_REG_W, data, packet_length >> 1);
1039 	if (packet_length & 1) {
1040 		data += packet_length & ~1;
1041 		*data = inb(BASE + DATA_REG_B);
1042 	}
1043 	IFNET_STAT_INC(ifp, ipackets, 1);
1044 
1045 	m->m_pkthdr.len = m->m_len = packet_length;
1046 
1047 	ifp->if_input(ifp, m, NULL, -1);
1048 
1049 out:
1050 
1051 	/*
1052 	 * Error or good, tell the card to get rid of this packet Wait for
1053 	 * the MMU to be un-busy.
1054 	 */
1055 	SMC_SELECT_BANK(2);
1056 	while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
1057 		;
1058 	outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE);
1059 
1060 	/*
1061 	 * Check whether another packet is ready
1062 	 */
1063 	packet_number = inw(BASE + FIFO_PORTS_REG_W);
1064 	if (packet_number & FIFO_REMPTY) {
1065 		return;
1066 	}
1067 	goto read_another;
1068 }
1069 
1070 
1071 /*
1072  * Handle IOCTLS.  This function is completely stolen from if_ep.c
1073  * As with its progenitor, it does not handle hardware address
1074  * changes.
1075  */
1076 static int
snioctl(struct ifnet * ifp,u_long cmd,caddr_t data,struct ucred * cr)1077 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1078 {
1079 	struct sn_softc *sc = ifp->if_softc;
1080 	int error = 0;
1081 
1082 	switch (cmd) {
1083 	case SIOCSIFFLAGS:
1084 		if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) {
1085 			ifp->if_flags &= ~IFF_RUNNING;
1086 			snstop(sc);
1087 			break;
1088 		} else {
1089 			/* reinitialize card on any parameter change */
1090 			sninit(sc);
1091 			break;
1092 		}
1093 		break;
1094 
1095 #ifdef notdef
1096 	case SIOCGHWADDR:
1097 		error = copyout((caddr_t)sc->sc_addr,
1098 				(caddr_t)&ifr->ifr_data,
1099 				sizeof(sc->sc_addr));
1100 		break;
1101 #endif
1102 
1103 	case SIOCADDMULTI:
1104 	    /* update multicast filter list. */
1105 	    sn_setmcast(sc);
1106 	    error = 0;
1107 	    break;
1108 	case SIOCDELMULTI:
1109 	    /* update multicast filter list. */
1110 	    sn_setmcast(sc);
1111 	    error = 0;
1112 	    break;
1113 	default:
1114 		error = ether_ioctl(ifp, cmd, data);
1115 		break;
1116 	}
1117 
1118 	return (error);
1119 }
1120 
1121 void
snreset(struct sn_softc * sc)1122 snreset(struct sn_softc *sc)
1123 {
1124 	snstop(sc);
1125 	sninit(sc);
1126 }
1127 
1128 void
snwatchdog(struct ifnet * ifp)1129 snwatchdog(struct ifnet *ifp)
1130 {
1131 	sn_intr(ifp->if_softc);
1132 }
1133 
1134 
1135 /* 1. zero the interrupt mask
1136  * 2. clear the enable receive flag
1137  * 3. clear the enable xmit flags
1138  */
1139 void
snstop(struct sn_softc * sc)1140 snstop(struct sn_softc *sc)
1141 {
1142 
1143 	struct ifnet   *ifp = &sc->arpcom.ac_if;
1144 
1145 	/*
1146 	 * Clear interrupt mask; disable all interrupts.
1147 	 */
1148 	SMC_SELECT_BANK(2);
1149 	outb(BASE + INTR_MASK_REG_B, 0x00);
1150 
1151 	/*
1152 	 * Disable transmitter and Receiver
1153 	 */
1154 	SMC_SELECT_BANK(0);
1155 	outw(BASE + RECV_CONTROL_REG_W, 0x0000);
1156 	outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
1157 
1158 	/*
1159 	 * Cancel watchdog.
1160 	 */
1161 	ifp->if_timer = 0;
1162 }
1163 
1164 
1165 int
sn_activate(device_t dev)1166 sn_activate(device_t dev)
1167 {
1168 	struct sn_softc *sc = device_get_softc(dev);
1169 
1170 	sc->port_rid = 0;
1171 	sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1172 	    0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1173 	if (!sc->port_res) {
1174 #ifdef SN_DEBUG
1175 		device_printf(dev, "Cannot allocate ioport\n");
1176 #endif
1177 		return ENOMEM;
1178 	}
1179 
1180 	sc->irq_rid = 0;
1181 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1182 	    RF_ACTIVE);
1183 	if (!sc->irq_res) {
1184 #ifdef SN_DEBUG
1185 		device_printf(dev, "Cannot allocate irq\n");
1186 #endif
1187 		sn_deactivate(dev);
1188 		return ENOMEM;
1189 	}
1190 
1191 	sc->sn_io_addr = rman_get_start(sc->port_res);
1192 	return (0);
1193 }
1194 
1195 void
sn_deactivate(device_t dev)1196 sn_deactivate(device_t dev)
1197 {
1198 	struct sn_softc *sc = device_get_softc(dev);
1199 
1200 	if (sc->port_res)
1201 		bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1202 		    sc->port_res);
1203 	sc->port_res = 0;
1204 	if (sc->irq_res)
1205 		bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1206 		    sc->irq_res);
1207 	sc->irq_res = 0;
1208 	return;
1209 }
1210 
1211 /*
1212  * Function: sn_probe( device_t dev, int pccard )
1213  *
1214  * Purpose:
1215  *      Tests to see if a given ioaddr points to an SMC9xxx chip.
1216  *      Tries to cause as little damage as possible if it's not a SMC chip.
1217  *      Returns a 0 on success
1218  *
1219  * Algorithm:
1220  *      (1) see if the high byte of BANK_SELECT is 0x33
1221  *      (2) compare the ioaddr with the base register's address
1222  *      (3) see if I recognize the chip ID in the appropriate register
1223  *
1224  *
1225  */
1226 int
sn_probe(device_t dev,int pccard)1227 sn_probe(device_t dev, int pccard)
1228 {
1229 	struct sn_softc *sc = device_get_softc(dev);
1230 	u_int           bank;
1231 	u_short         revision_register;
1232 	u_short         base_address_register;
1233 	u_short		ioaddr;
1234 	int		err;
1235 
1236 	if ((err = sn_activate(dev)) != 0)
1237 		return err;
1238 
1239 	ioaddr = sc->sn_io_addr;
1240 
1241 	/*
1242 	 * First, see if the high byte is 0x33
1243 	 */
1244 	bank = inw(ioaddr + BANK_SELECT_REG_W);
1245 	if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1246 #ifdef	SN_DEBUG
1247 		device_printf(dev, "test1 failed\n");
1248 #endif
1249 		goto error;
1250 	}
1251 	/*
1252 	 * The above MIGHT indicate a device, but I need to write to further
1253 	 * test this.  Go to bank 0, then test that the register still
1254 	 * reports the high byte is 0x33.
1255 	 */
1256 	outw(ioaddr + BANK_SELECT_REG_W, 0x0000);
1257 	bank = inw(ioaddr + BANK_SELECT_REG_W);
1258 	if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1259 #ifdef	SN_DEBUG
1260 		device_printf(dev, "test2 failed\n");
1261 #endif
1262 		goto error;
1263 	}
1264 	/*
1265 	 * well, we've already written once, so hopefully another time won't
1266 	 * hurt.  This time, I need to switch the bank register to bank 1, so
1267 	 * I can access the base address register.  The contents of the
1268 	 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1269 	 * to match the I/O port address where the adapter is being probed.
1270 	 */
1271 	outw(ioaddr + BANK_SELECT_REG_W, 0x0001);
1272 	base_address_register = inw(ioaddr + BASE_ADDR_REG_W);
1273 
1274 	/*
1275 	 * This test is nonsence on PC-card architecture, so if
1276 	 * pccard == 1, skip this test. (hosokawa)
1277 	 */
1278 	if (!pccard && (ioaddr != (base_address_register >> 3 & 0x3E0))) {
1279 
1280 		/*
1281 		 * Well, the base address register didn't match.  Must not
1282 		 * have been a SMC chip after all.
1283 		 */
1284 		/*
1285 		 * kprintf("sn: ioaddr %x doesn't match card configuration
1286 		 * (%x)\n", ioaddr, base_address_register >> 3 & 0x3E0 );
1287 		 */
1288 
1289 #ifdef	SN_DEBUG
1290 		device_printf(dev, "test3 failed ioaddr = 0x%x, "
1291 		    "base_address_register = 0x%x\n", ioaddr,
1292 		    base_address_register >> 3 & 0x3E0);
1293 #endif
1294 		goto error;
1295 	}
1296 	/*
1297 	 * Check if the revision register is something that I recognize.
1298 	 * These might need to be added to later, as future revisions could
1299 	 * be added.
1300 	 */
1301 	outw(ioaddr + BANK_SELECT_REG_W, 0x3);
1302 	revision_register = inw(ioaddr + REVISION_REG_W);
1303 	if (!chip_ids[(revision_register >> 4) & 0xF]) {
1304 
1305 		/*
1306 		 * I don't regonize this chip, so...
1307 		 */
1308 #ifdef	SN_DEBUG
1309 		device_printf(dev, "test4 failed\n");
1310 #endif
1311 		goto error;
1312 	}
1313 	/*
1314 	 * at this point I'll assume that the chip is an SMC9xxx. It might be
1315 	 * prudent to check a listing of MAC addresses against the hardware
1316 	 * address, or do some other tests.
1317 	 */
1318 	sn_deactivate(dev);
1319 	return 0;
1320  error:
1321 	sn_deactivate(dev);
1322 	return ENXIO;
1323 }
1324 
1325 #define MCFSZ 8
1326 
1327 static void
sn_setmcast(struct sn_softc * sc)1328 sn_setmcast(struct sn_softc *sc)
1329 {
1330 	struct ifnet *ifp = (struct ifnet *)sc;
1331 	int flags;
1332 
1333 	/*
1334 	 * Set the receiver filter.  We want receive enabled and auto strip
1335 	 * of CRC from received packet.  If we are promiscuous then set that
1336 	 * bit too.
1337 	 */
1338 	flags = RCR_ENABLE | RCR_STRIP_CRC;
1339 
1340 	if (ifp->if_flags & IFF_PROMISC) {
1341 		flags |= RCR_PROMISC | RCR_ALMUL;
1342 	} else if (ifp->if_flags & IFF_ALLMULTI) {
1343 		flags |= RCR_ALMUL;
1344 	} else {
1345 		u_char mcf[MCFSZ];
1346 		if (sn_getmcf(&sc->arpcom, mcf)) {
1347 			/* set filter */
1348 			SMC_SELECT_BANK(3);
1349 			outw(BASE + MULTICAST1_REG_W,
1350 			    ((u_short)mcf[1] << 8) |  mcf[0]);
1351 			outw(BASE + MULTICAST2_REG_W,
1352 			    ((u_short)mcf[3] << 8) |  mcf[2]);
1353 			outw(BASE + MULTICAST3_REG_W,
1354 			    ((u_short)mcf[5] << 8) |  mcf[4]);
1355 			outw(BASE + MULTICAST4_REG_W,
1356 			    ((u_short)mcf[7] << 8) |  mcf[6]);
1357 		} else {
1358 			flags |= RCR_ALMUL;
1359 		}
1360 	}
1361 	SMC_SELECT_BANK(0);
1362 	outw(BASE + RECV_CONTROL_REG_W, flags);
1363 }
1364 
1365 static int
sn_getmcf(struct arpcom * ac,u_char * mcf)1366 sn_getmcf(struct arpcom *ac, u_char *mcf)
1367 {
1368 	int i;
1369 	u_int index, index2;
1370 	u_char *af = mcf;
1371 	struct ifmultiaddr *ifma;
1372 
1373 	bzero(mcf, MCFSZ);
1374 
1375 	TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) {
1376 	    if (ifma->ifma_addr->sa_family != AF_LINK)
1377 		return 0;
1378 	    index = smc_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f;
1379 	    index2 = 0;
1380 	    for (i = 0; i < 6; i++) {
1381 		index2 <<= 1;
1382 		index2 |= (index & 0x01);
1383 		index >>= 1;
1384 	    }
1385 	    af[index2 >> 3] |= 1 << (index2 & 7);
1386 	}
1387 	return 1;  /* use multicast filter */
1388 }
1389 
1390 static u_int
smc_crc(u_char * s)1391 smc_crc(u_char *s)
1392 {
1393 	int perByte;
1394 	int perBit;
1395 	const u_int poly = 0xedb88320;
1396 	u_int v = 0xffffffff;
1397 	u_char c;
1398 
1399 	for (perByte = 0; perByte < ETHER_ADDR_LEN; perByte++) {
1400 		c = s[perByte];
1401 		for (perBit = 0; perBit < 8; perBit++) {
1402 			v = (v >> 1)^(((v ^ c) & 0x01) ? poly : 0);
1403 			c >>= 1;
1404 		}
1405 	}
1406 	return v;
1407 }
1408