1 /* 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/sn/if_sn.c,v 1.7.2.3 2001/02/04 04:38:38 toshi Exp $ 32 * $DragonFly: src/sys/dev/netif/sn/if_sn.c,v 1.29 2008/08/17 04:32:34 sephe Exp $ 33 */ 34 35 /* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o The hardware multicast filter isn't used yet. 68 * o Setting of the hardware address isn't supported. 69 * o Hardware padding isn't used. 70 */ 71 72 /* 73 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 74 * 75 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 76 * BSD-nomads, Tokyo, Japan. 77 */ 78 /* 79 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 80 * Special thanks to itojun@itojun.org 81 */ 82 83 #undef SN_DEBUG /* (by hosokawa) */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/interrupt.h> 89 #include <sys/errno.h> 90 #include <sys/sockio.h> 91 #include <sys/malloc.h> 92 #include <sys/mbuf.h> 93 #include <sys/socket.h> 94 #include <sys/syslog.h> 95 #include <sys/serialize.h> 96 #include <sys/module.h> 97 #include <sys/bus.h> 98 #include <sys/rman.h> 99 #include <sys/thread2.h> 100 101 #include <net/ethernet.h> 102 #include <net/if.h> 103 #include <net/ifq_var.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_types.h> 107 #include <net/if_mib.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/in_var.h> 113 #include <netinet/ip.h> 114 #endif 115 116 #ifdef NS 117 #include <netns/ns.h> 118 #include <netns/ns_if.h> 119 #endif 120 121 #include <net/bpf.h> 122 #include <net/bpfdesc.h> 123 124 #include <machine/clock.h> 125 126 #include "if_snreg.h" 127 #include "if_snvar.h" 128 129 /* Exported variables */ 130 devclass_t sn_devclass; 131 132 static int snioctl(struct ifnet * ifp, u_long, caddr_t, struct ucred *); 133 134 static void snresume(struct ifnet *); 135 136 void sninit(void *); 137 void snread(struct ifnet *); 138 void snreset(struct sn_softc *); 139 void snstart(struct ifnet *); 140 void snstop(struct sn_softc *); 141 void snwatchdog(struct ifnet *); 142 143 static void sn_setmcast(struct sn_softc *); 144 static int sn_getmcf(struct arpcom *ac, u_char *mcf); 145 static u_int smc_crc(u_char *); 146 147 DECLARE_DUMMY_MODULE(if_sn); 148 149 /* I (GB) have been unlucky getting the hardware padding 150 * to work properly. 151 */ 152 #define SW_PAD 153 154 static const char *chip_ids[15] = { 155 NULL, NULL, NULL, 156 /* 3 */ "SMC91C90/91C92", 157 /* 4 */ "SMC91C94", 158 /* 5 */ "SMC91C95", 159 NULL, 160 /* 7 */ "SMC91C100", 161 /* 8 */ "SMC91C100FD", 162 NULL, NULL, NULL, 163 NULL, NULL, NULL 164 }; 165 166 int 167 sn_attach(device_t dev) 168 { 169 struct sn_softc *sc = device_get_softc(dev); 170 struct ifnet *ifp = &sc->arpcom.ac_if; 171 u_short i; 172 u_char *p; 173 int rev; 174 u_short address; 175 int j; 176 int error; 177 178 sn_activate(dev); 179 180 snstop(sc); 181 182 sc->dev = dev; 183 sc->pages_wanted = -1; 184 185 device_printf(dev, " "); 186 187 SMC_SELECT_BANK(3); 188 rev = inw(BASE + REVISION_REG_W); 189 if (chip_ids[(rev >> 4) & 0xF]) 190 kprintf("%s ", chip_ids[(rev >> 4) & 0xF]); 191 192 SMC_SELECT_BANK(1); 193 i = inw(BASE + CONFIG_REG_W); 194 kprintf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 195 196 if (sc->pccard_enaddr) 197 for (j = 0; j < 3; j++) { 198 u_short w; 199 200 w = (u_short)sc->arpcom.ac_enaddr[j * 2] | 201 (((u_short)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8); 202 outw(BASE + IAR_ADDR0_REG_W + j * 2, w); 203 } 204 205 /* 206 * Read the station address from the chip. The MAC address is bank 1, 207 * regs 4 - 9 208 */ 209 SMC_SELECT_BANK(1); 210 p = (u_char *) & sc->arpcom.ac_enaddr; 211 for (i = 0; i < 6; i += 2) { 212 address = inw(BASE + IAR_ADDR0_REG_W + i); 213 p[i + 1] = address >> 8; 214 p[i] = address & 0xFF; 215 } 216 ifp->if_softc = sc; 217 if_initname(ifp, "sn", device_get_unit(dev)); 218 ifp->if_mtu = ETHERMTU; 219 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 220 ifp->if_start = snstart; 221 ifp->if_ioctl = snioctl; 222 ifp->if_watchdog = snwatchdog; 223 ifp->if_init = sninit; 224 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 225 ifq_set_ready(&ifp->if_snd); 226 ifp->if_timer = 0; 227 228 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 229 230 error = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 231 sn_intr, sc, &sc->intrhand, 232 ifp->if_serializer); 233 if (error) { 234 ether_ifdetach(ifp); 235 sn_deactivate(dev); 236 return error; 237 } 238 239 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq_res)); 240 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 241 242 return 0; 243 } 244 245 246 /* 247 * Reset and initialize the chip 248 */ 249 void 250 sninit(void *xsc) 251 { 252 struct sn_softc *sc = xsc; 253 struct ifnet *ifp = &sc->arpcom.ac_if; 254 int flags; 255 int mask; 256 257 /* 258 * This resets the registers mostly to defaults, but doesn't affect 259 * EEPROM. After the reset cycle, we pause briefly for the chip to 260 * be happy. 261 */ 262 SMC_SELECT_BANK(0); 263 outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET); 264 SMC_DELAY(); 265 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 266 SMC_DELAY(); 267 SMC_DELAY(); 268 269 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 270 271 /* 272 * Set the control register to automatically release succesfully 273 * transmitted packets (making the best use out of our limited 274 * memory) and to enable the EPH interrupt on certain TX errors. 275 */ 276 SMC_SELECT_BANK(1); 277 outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 278 CTR_CR_ENABLE | CTR_LE_ENABLE)); 279 280 /* Set squelch level to 240mV (default 480mV) */ 281 flags = inw(BASE + CONFIG_REG_W); 282 flags |= CR_SET_SQLCH; 283 outw(BASE + CONFIG_REG_W, flags); 284 285 /* 286 * Reset the MMU and wait for it to be un-busy. 287 */ 288 SMC_SELECT_BANK(2); 289 outw(BASE + MMU_CMD_REG_W, MMUCR_RESET); 290 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 291 ; 292 293 /* 294 * Disable all interrupts 295 */ 296 outb(BASE + INTR_MASK_REG_B, 0x00); 297 298 sn_setmcast(sc); 299 300 /* 301 * Set the transmitter control. We want it enabled. 302 */ 303 flags = TCR_ENABLE; 304 305 #ifndef SW_PAD 306 /* 307 * I (GB) have been unlucky getting this to work. 308 */ 309 flags |= TCR_PAD_ENABLE; 310 #endif /* SW_PAD */ 311 312 outw(BASE + TXMIT_CONTROL_REG_W, flags); 313 314 315 /* 316 * Now, enable interrupts 317 */ 318 SMC_SELECT_BANK(2); 319 320 mask = IM_EPH_INT | 321 IM_RX_OVRN_INT | 322 IM_RCV_INT | 323 IM_TX_INT; 324 325 outb(BASE + INTR_MASK_REG_B, mask); 326 sc->intr_mask = mask; 327 sc->pages_wanted = -1; 328 329 330 /* 331 * Mark the interface running but not active. 332 */ 333 ifp->if_flags |= IFF_RUNNING; 334 ifp->if_flags &= ~IFF_OACTIVE; 335 336 /* 337 * Attempt to push out any waiting packets. 338 */ 339 if_devstart(ifp); 340 } 341 342 343 void 344 snstart(struct ifnet *ifp) 345 { 346 struct sn_softc *sc = ifp->if_softc; 347 u_int len; 348 struct mbuf *m; 349 struct mbuf *top; 350 int pad; 351 int mask; 352 u_short length; 353 u_short numPages; 354 u_char packet_no; 355 int time_out; 356 357 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 358 return; 359 360 if (sc->pages_wanted != -1) { 361 /* XXX should never happen */ 362 kprintf("%s: snstart() while memory allocation pending\n", 363 ifp->if_xname); 364 ifp->if_flags |= IFF_OACTIVE; 365 return; 366 } 367 startagain: 368 369 /* 370 * Sneak a peek at the next packet 371 */ 372 m = ifq_dequeue(&ifp->if_snd, NULL); 373 if (m == NULL) 374 return; 375 376 /* 377 * Compute the frame length and set pad to give an overall even 378 * number of bytes. Below we assume that the packet length is even. 379 */ 380 for (len = 0, top = m; m; m = m->m_next) 381 len += m->m_len; 382 383 pad = (len & 1); 384 385 /* 386 * We drop packets that are too large. Perhaps we should truncate 387 * them instead? 388 */ 389 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 390 kprintf("%s: large packet discarded (A)\n", ifp->if_xname); 391 ++sc->arpcom.ac_if.if_oerrors; 392 m_freem(top); 393 goto readcheck; 394 } 395 #ifdef SW_PAD 396 397 /* 398 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 399 */ 400 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 401 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 402 403 #endif /* SW_PAD */ 404 405 length = pad + len; 406 407 /* 408 * The MMU wants the number of pages to be the number of 256 byte 409 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 410 * include space for the status word, byte count and control bytes in 411 * the allocation request. 412 */ 413 numPages = (length + 6) >> 8; 414 415 416 /* 417 * Now, try to allocate the memory 418 */ 419 SMC_SELECT_BANK(2); 420 outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 421 422 /* 423 * Wait a short amount of time to see if the allocation request 424 * completes. Otherwise, I enable the interrupt and wait for 425 * completion asyncronously. 426 */ 427 428 time_out = MEMORY_WAIT_TIME; 429 do { 430 if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT) 431 break; 432 } while (--time_out); 433 434 if (!time_out) { 435 436 /* 437 * No memory now. Oh well, wait until the chip finds memory 438 * later. Remember how many pages we were asking for and 439 * enable the allocation completion interrupt. Also set a 440 * watchdog in case we miss the interrupt. We mark the 441 * interface active since there is no point in attempting an 442 * snstart() until after the memory is available. 443 */ 444 mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT; 445 outb(BASE + INTR_MASK_REG_B, mask); 446 sc->intr_mask = mask; 447 448 ifp->if_timer = 1; 449 ifp->if_flags |= IFF_OACTIVE; 450 sc->pages_wanted = numPages; 451 ifq_prepend(&ifp->if_snd, top); 452 453 return; 454 } 455 /* 456 * The memory allocation completed. Check the results. 457 */ 458 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 459 if (packet_no & ARR_FAILED) { 460 kprintf("%s: Memory allocation failed\n", ifp->if_xname); 461 ifq_prepend(&ifp->if_snd, top); 462 goto startagain; 463 } 464 /* 465 * We have a packet number, so tell the card to use it. 466 */ 467 outb(BASE + PACKET_NUM_REG_B, packet_no); 468 469 /* 470 * Point to the beginning of the packet 471 */ 472 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 473 474 /* 475 * Send the packet length (+6 for status, length and control byte) 476 * and the status word (set to zeros) 477 */ 478 outw(BASE + DATA_REG_W, 0); 479 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 480 outb(BASE + DATA_REG_B, (length + 6) >> 8); 481 482 /* 483 * Push out the data to the card. 484 */ 485 for (m = top; m != NULL; m = m->m_next) { 486 487 /* 488 * Push out words. 489 */ 490 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 491 492 /* 493 * Push out remaining byte. 494 */ 495 if (m->m_len & 1) 496 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 497 } 498 499 /* 500 * Push out padding. 501 */ 502 while (pad > 1) { 503 outw(BASE + DATA_REG_W, 0); 504 pad -= 2; 505 } 506 if (pad) 507 outb(BASE + DATA_REG_B, 0); 508 509 /* 510 * Push out control byte and unused packet byte The control byte is 0 511 * meaning the packet is even lengthed and no special CRC handling is 512 * desired. 513 */ 514 outw(BASE + DATA_REG_W, 0); 515 516 /* 517 * Enable the interrupts and let the chipset deal with it Also set a 518 * watchdog in case we miss the interrupt. 519 */ 520 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 521 outb(BASE + INTR_MASK_REG_B, mask); 522 sc->intr_mask = mask; 523 524 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 525 526 ifp->if_flags |= IFF_OACTIVE; 527 ifp->if_timer = 1; 528 529 BPF_MTAP(ifp, top); 530 531 ifp->if_opackets++; 532 m_freem(top); 533 534 readcheck: 535 536 /* 537 * Is another packet coming in? We don't want to overflow the tiny 538 * RX FIFO. If nothing has arrived then attempt to queue another 539 * transmit packet. 540 */ 541 if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY) 542 goto startagain; 543 } 544 545 546 547 /* Resume a packet transmit operation after a memory allocation 548 * has completed. 549 * 550 * This is basically a hacked up copy of snstart() which handles 551 * a completed memory allocation the same way snstart() does. 552 * It then passes control to snstart to handle any other queued 553 * packets. 554 */ 555 static void 556 snresume(struct ifnet *ifp) 557 { 558 struct sn_softc *sc = ifp->if_softc; 559 u_int len; 560 struct mbuf *m; 561 struct mbuf *top; 562 int pad; 563 int mask; 564 u_short length; 565 u_short numPages; 566 u_short pages_wanted; 567 u_char packet_no; 568 569 if (sc->pages_wanted < 0) 570 return; 571 572 pages_wanted = sc->pages_wanted; 573 sc->pages_wanted = -1; 574 575 /* 576 * Sneak a peek at the next packet 577 */ 578 m = ifq_dequeue(&ifp->if_snd, NULL); 579 if (m == NULL) { 580 kprintf("%s: snresume() with nothing to send\n", 581 ifp->if_xname); 582 return; 583 } 584 585 /* 586 * Compute the frame length and set pad to give an overall even 587 * number of bytes. Below we assume that the packet length is even. 588 */ 589 for (len = 0, top = m; m; m = m->m_next) 590 len += m->m_len; 591 592 pad = (len & 1); 593 594 /* 595 * We drop packets that are too large. Perhaps we should truncate 596 * them instead? 597 */ 598 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 599 kprintf("%s: large packet discarded (B)\n", ifp->if_xname); 600 ++ifp->if_oerrors; 601 m_freem(top); 602 return; 603 } 604 #ifdef SW_PAD 605 606 /* 607 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 608 */ 609 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 610 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 611 612 #endif /* SW_PAD */ 613 614 length = pad + len; 615 616 617 /* 618 * The MMU wants the number of pages to be the number of 256 byte 619 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 620 * include space for the status word, byte count and control bytes in 621 * the allocation request. 622 */ 623 numPages = (length + 6) >> 8; 624 625 626 SMC_SELECT_BANK(2); 627 628 /* 629 * The memory allocation completed. Check the results. If it failed, 630 * we simply set a watchdog timer and hope for the best. 631 */ 632 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 633 if (packet_no & ARR_FAILED) { 634 kprintf("%s: Memory allocation failed. Weird.\n", ifp->if_xname); 635 ifp->if_timer = 1; 636 ifq_prepend(&ifp->if_snd, top); 637 goto try_start; 638 } 639 /* 640 * We have a packet number, so tell the card to use it. 641 */ 642 outb(BASE + PACKET_NUM_REG_B, packet_no); 643 644 /* 645 * Now, numPages should match the pages_wanted recorded when the 646 * memory allocation was initiated. 647 */ 648 if (pages_wanted != numPages) { 649 kprintf("%s: memory allocation wrong size. Weird.\n", ifp->if_xname); 650 /* 651 * If the allocation was the wrong size we simply release the 652 * memory once it is granted. Wait for the MMU to be un-busy. 653 */ 654 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 655 ; 656 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 657 658 ifq_prepend(&ifp->if_snd, top); 659 return; 660 } 661 /* 662 * Point to the beginning of the packet 663 */ 664 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 665 666 /* 667 * Send the packet length (+6 for status, length and control byte) 668 * and the status word (set to zeros) 669 */ 670 outw(BASE + DATA_REG_W, 0); 671 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 672 outb(BASE + DATA_REG_B, (length + 6) >> 8); 673 674 /* 675 * Push out the data to the card. 676 */ 677 for (m = top; m != NULL; m = m->m_next) { 678 679 /* 680 * Push out words. 681 */ 682 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 683 684 /* 685 * Push out remaining byte. 686 */ 687 if (m->m_len & 1) 688 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 689 } 690 691 /* 692 * Push out padding. 693 */ 694 while (pad > 1) { 695 outw(BASE + DATA_REG_W, 0); 696 pad -= 2; 697 } 698 if (pad) 699 outb(BASE + DATA_REG_B, 0); 700 701 /* 702 * Push out control byte and unused packet byte The control byte is 0 703 * meaning the packet is even lengthed and no special CRC handling is 704 * desired. 705 */ 706 outw(BASE + DATA_REG_W, 0); 707 708 /* 709 * Enable the interrupts and let the chipset deal with it Also set a 710 * watchdog in case we miss the interrupt. 711 */ 712 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 713 outb(BASE + INTR_MASK_REG_B, mask); 714 sc->intr_mask = mask; 715 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 716 717 BPF_MTAP(ifp, top); 718 719 ifp->if_opackets++; 720 m_freem(top); 721 722 try_start: 723 724 /* 725 * Now pass control to snstart() to queue any additional packets 726 */ 727 ifp->if_flags &= ~IFF_OACTIVE; 728 if_devstart(ifp); 729 730 /* 731 * We've sent something, so we're active. Set a watchdog in case the 732 * TX_EMPTY interrupt is lost. 733 */ 734 ifp->if_flags |= IFF_OACTIVE; 735 ifp->if_timer = 1; 736 } 737 738 739 void 740 sn_intr(void *arg) 741 { 742 int status, interrupts; 743 struct sn_softc *sc = (struct sn_softc *) arg; 744 struct ifnet *ifp = &sc->arpcom.ac_if; 745 746 /* 747 * Chip state registers 748 */ 749 u_char mask; 750 u_char packet_no; 751 u_short tx_status; 752 u_short card_stats; 753 754 /* 755 * Clear the watchdog. 756 */ 757 ifp->if_timer = 0; 758 759 SMC_SELECT_BANK(2); 760 761 /* 762 * Obtain the current interrupt mask and clear the hardware mask 763 * while servicing interrupts. 764 */ 765 mask = inb(BASE + INTR_MASK_REG_B); 766 outb(BASE + INTR_MASK_REG_B, 0x00); 767 768 /* 769 * Get the set of interrupts which occurred and eliminate any which 770 * are masked. 771 */ 772 interrupts = inb(BASE + INTR_STAT_REG_B); 773 status = interrupts & mask; 774 775 /* 776 * Now, process each of the interrupt types. 777 */ 778 779 /* 780 * Receive Overrun. 781 */ 782 if (status & IM_RX_OVRN_INT) { 783 784 /* 785 * Acknowlege Interrupt 786 */ 787 SMC_SELECT_BANK(2); 788 outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT); 789 790 ++sc->arpcom.ac_if.if_ierrors; 791 } 792 /* 793 * Got a packet. 794 */ 795 if (status & IM_RCV_INT) { 796 #if 1 797 int packet_number; 798 799 SMC_SELECT_BANK(2); 800 packet_number = inw(BASE + FIFO_PORTS_REG_W); 801 802 if (packet_number & FIFO_REMPTY) { 803 804 /* 805 * we got called , but nothing was on the FIFO 806 */ 807 kprintf("sn: Receive interrupt with nothing on FIFO\n"); 808 809 goto out; 810 } 811 #endif 812 snread(ifp); 813 } 814 /* 815 * An on-card memory allocation came through. 816 */ 817 if (status & IM_ALLOC_INT) { 818 819 /* 820 * Disable this interrupt. 821 */ 822 mask &= ~IM_ALLOC_INT; 823 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 824 snresume(&sc->arpcom.ac_if); 825 } 826 /* 827 * TX Completion. Handle a transmit error message. This will only be 828 * called when there is an error, because of the AUTO_RELEASE mode. 829 */ 830 if (status & IM_TX_INT) { 831 832 /* 833 * Acknowlege Interrupt 834 */ 835 SMC_SELECT_BANK(2); 836 outb(BASE + INTR_ACK_REG_B, IM_TX_INT); 837 838 packet_no = inw(BASE + FIFO_PORTS_REG_W); 839 packet_no &= FIFO_TX_MASK; 840 841 /* 842 * select this as the packet to read from 843 */ 844 outb(BASE + PACKET_NUM_REG_B, packet_no); 845 846 /* 847 * Position the pointer to the first word from this packet 848 */ 849 outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 850 851 /* 852 * Fetch the TX status word. The value found here will be a 853 * copy of the EPH_STATUS_REG_W at the time the transmit 854 * failed. 855 */ 856 tx_status = inw(BASE + DATA_REG_W); 857 858 if (tx_status & EPHSR_TX_SUC) { 859 device_printf(sc->dev, 860 "Successful packet caused interrupt\n"); 861 } else { 862 ++sc->arpcom.ac_if.if_oerrors; 863 } 864 865 if (tx_status & EPHSR_LATCOL) 866 ++sc->arpcom.ac_if.if_collisions; 867 868 /* 869 * Some of these errors will have disabled transmit. 870 * Re-enable transmit now. 871 */ 872 SMC_SELECT_BANK(0); 873 874 #ifdef SW_PAD 875 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE); 876 #else 877 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 878 #endif /* SW_PAD */ 879 880 /* 881 * kill the failed packet. Wait for the MMU to be un-busy. 882 */ 883 SMC_SELECT_BANK(2); 884 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 885 ; 886 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 887 888 /* 889 * Attempt to queue more transmits. 890 */ 891 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 892 if_devstart(&sc->arpcom.ac_if); 893 } 894 /* 895 * Transmit underrun. We use this opportunity to update transmit 896 * statistics from the card. 897 */ 898 if (status & IM_TX_EMPTY_INT) { 899 900 /* 901 * Acknowlege Interrupt 902 */ 903 SMC_SELECT_BANK(2); 904 outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT); 905 906 /* 907 * Disable this interrupt. 908 */ 909 mask &= ~IM_TX_EMPTY_INT; 910 911 SMC_SELECT_BANK(0); 912 card_stats = inw(BASE + COUNTER_REG_W); 913 914 /* 915 * Single collisions 916 */ 917 sc->arpcom.ac_if.if_collisions += card_stats & ECR_COLN_MASK; 918 919 /* 920 * Multiple collisions 921 */ 922 sc->arpcom.ac_if.if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 923 924 SMC_SELECT_BANK(2); 925 926 /* 927 * Attempt to enqueue some more stuff. 928 */ 929 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 930 if_devstart(&sc->arpcom.ac_if); 931 } 932 /* 933 * Some other error. Try to fix it by resetting the adapter. 934 */ 935 if (status & IM_EPH_INT) { 936 snstop(sc); 937 sninit(sc); 938 } 939 940 out: 941 /* 942 * Handled all interrupt sources. 943 */ 944 945 SMC_SELECT_BANK(2); 946 947 /* 948 * Reestablish interrupts from mask which have not been deselected 949 * during this interrupt. Note that the hardware mask, which was set 950 * to 0x00 at the start of this service routine, may have been 951 * updated by one or more of the interrupt handers and we must let 952 * those new interrupts stay enabled here. 953 */ 954 mask |= inb(BASE + INTR_MASK_REG_B); 955 outb(BASE + INTR_MASK_REG_B, mask); 956 sc->intr_mask = mask; 957 } 958 959 void 960 snread(struct ifnet *ifp) 961 { 962 struct sn_softc *sc = ifp->if_softc; 963 struct mbuf *m; 964 short status; 965 int packet_number; 966 u_short packet_length; 967 u_char *data; 968 969 SMC_SELECT_BANK(2); 970 #if 0 971 packet_number = inw(BASE + FIFO_PORTS_REG_W); 972 973 if (packet_number & FIFO_REMPTY) { 974 975 /* 976 * we got called , but nothing was on the FIFO 977 */ 978 kprintf("sn: Receive interrupt with nothing on FIFO\n"); 979 return; 980 } 981 #endif 982 read_another: 983 984 /* 985 * Start reading from the start of the packet. Since PTR_RCV is set, 986 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 987 */ 988 outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 989 990 /* 991 * First two words are status and packet_length 992 */ 993 status = inw(BASE + DATA_REG_W); 994 packet_length = inw(BASE + DATA_REG_W) & RLEN_MASK; 995 996 /* 997 * The packet length contains 3 extra words: status, length, and a 998 * extra word with the control byte. 999 */ 1000 packet_length -= 6; 1001 1002 /* 1003 * Account for receive errors and discard. 1004 */ 1005 if (status & RS_ERRORS) { 1006 ++ifp->if_ierrors; 1007 goto out; 1008 } 1009 /* 1010 * A packet is received. 1011 */ 1012 1013 /* 1014 * Adjust for odd-length packet. 1015 */ 1016 if (status & RS_ODDFRAME) 1017 packet_length++; 1018 1019 /* 1020 * Allocate a header mbuf from the kernel. 1021 */ 1022 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1023 if (m == NULL) 1024 goto out; 1025 1026 m->m_pkthdr.rcvif = ifp; 1027 m->m_pkthdr.len = m->m_len = packet_length; 1028 1029 /* 1030 * Attach an mbuf cluster 1031 */ 1032 MCLGET(m, MB_DONTWAIT); 1033 1034 /* 1035 * Insist on getting a cluster 1036 */ 1037 if ((m->m_flags & M_EXT) == 0) { 1038 m_freem(m); 1039 ++ifp->if_ierrors; 1040 kprintf("sn: snread() kernel memory allocation problem\n"); 1041 goto out; 1042 } 1043 1044 /* 1045 * Get packet, including link layer address, from interface. 1046 */ 1047 1048 data = mtod(m, u_char *); 1049 insw(BASE + DATA_REG_W, data, packet_length >> 1); 1050 if (packet_length & 1) { 1051 data += packet_length & ~1; 1052 *data = inb(BASE + DATA_REG_B); 1053 } 1054 ++ifp->if_ipackets; 1055 1056 m->m_pkthdr.len = m->m_len = packet_length; 1057 1058 ifp->if_input(ifp, m); 1059 1060 out: 1061 1062 /* 1063 * Error or good, tell the card to get rid of this packet Wait for 1064 * the MMU to be un-busy. 1065 */ 1066 SMC_SELECT_BANK(2); 1067 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1068 ; 1069 outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE); 1070 1071 /* 1072 * Check whether another packet is ready 1073 */ 1074 packet_number = inw(BASE + FIFO_PORTS_REG_W); 1075 if (packet_number & FIFO_REMPTY) { 1076 return; 1077 } 1078 goto read_another; 1079 } 1080 1081 1082 /* 1083 * Handle IOCTLS. This function is completely stolen from if_ep.c 1084 * As with its progenitor, it does not handle hardware address 1085 * changes. 1086 */ 1087 static int 1088 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1089 { 1090 struct sn_softc *sc = ifp->if_softc; 1091 int error = 0; 1092 1093 switch (cmd) { 1094 case SIOCSIFFLAGS: 1095 if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) { 1096 ifp->if_flags &= ~IFF_RUNNING; 1097 snstop(sc); 1098 break; 1099 } else { 1100 /* reinitialize card on any parameter change */ 1101 sninit(sc); 1102 break; 1103 } 1104 break; 1105 1106 #ifdef notdef 1107 case SIOCGHWADDR: 1108 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data, 1109 sizeof(sc->sc_addr)); 1110 break; 1111 #endif 1112 1113 case SIOCADDMULTI: 1114 /* update multicast filter list. */ 1115 sn_setmcast(sc); 1116 error = 0; 1117 break; 1118 case SIOCDELMULTI: 1119 /* update multicast filter list. */ 1120 sn_setmcast(sc); 1121 error = 0; 1122 break; 1123 default: 1124 error = ether_ioctl(ifp, cmd, data); 1125 break; 1126 } 1127 1128 return (error); 1129 } 1130 1131 void 1132 snreset(struct sn_softc *sc) 1133 { 1134 snstop(sc); 1135 sninit(sc); 1136 } 1137 1138 void 1139 snwatchdog(struct ifnet *ifp) 1140 { 1141 sn_intr(ifp->if_softc); 1142 } 1143 1144 1145 /* 1. zero the interrupt mask 1146 * 2. clear the enable receive flag 1147 * 3. clear the enable xmit flags 1148 */ 1149 void 1150 snstop(struct sn_softc *sc) 1151 { 1152 1153 struct ifnet *ifp = &sc->arpcom.ac_if; 1154 1155 /* 1156 * Clear interrupt mask; disable all interrupts. 1157 */ 1158 SMC_SELECT_BANK(2); 1159 outb(BASE + INTR_MASK_REG_B, 0x00); 1160 1161 /* 1162 * Disable transmitter and Receiver 1163 */ 1164 SMC_SELECT_BANK(0); 1165 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 1166 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 1167 1168 /* 1169 * Cancel watchdog. 1170 */ 1171 ifp->if_timer = 0; 1172 } 1173 1174 1175 int 1176 sn_activate(device_t dev) 1177 { 1178 struct sn_softc *sc = device_get_softc(dev); 1179 1180 sc->port_rid = 0; 1181 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1182 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1183 if (!sc->port_res) { 1184 #ifdef SN_DEBUG 1185 device_printf(dev, "Cannot allocate ioport\n"); 1186 #endif 1187 return ENOMEM; 1188 } 1189 1190 sc->irq_rid = 0; 1191 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1192 RF_ACTIVE); 1193 if (!sc->irq_res) { 1194 #ifdef SN_DEBUG 1195 device_printf(dev, "Cannot allocate irq\n"); 1196 #endif 1197 sn_deactivate(dev); 1198 return ENOMEM; 1199 } 1200 1201 sc->sn_io_addr = rman_get_start(sc->port_res); 1202 return (0); 1203 } 1204 1205 void 1206 sn_deactivate(device_t dev) 1207 { 1208 struct sn_softc *sc = device_get_softc(dev); 1209 1210 if (sc->port_res) 1211 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1212 sc->port_res); 1213 sc->port_res = 0; 1214 if (sc->irq_res) 1215 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1216 sc->irq_res); 1217 sc->irq_res = 0; 1218 return; 1219 } 1220 1221 /* 1222 * Function: sn_probe( device_t dev, int pccard ) 1223 * 1224 * Purpose: 1225 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1226 * Tries to cause as little damage as possible if it's not a SMC chip. 1227 * Returns a 0 on success 1228 * 1229 * Algorithm: 1230 * (1) see if the high byte of BANK_SELECT is 0x33 1231 * (2) compare the ioaddr with the base register's address 1232 * (3) see if I recognize the chip ID in the appropriate register 1233 * 1234 * 1235 */ 1236 int 1237 sn_probe(device_t dev, int pccard) 1238 { 1239 struct sn_softc *sc = device_get_softc(dev); 1240 u_int bank; 1241 u_short revision_register; 1242 u_short base_address_register; 1243 u_short ioaddr; 1244 int err; 1245 1246 if ((err = sn_activate(dev)) != 0) 1247 return err; 1248 1249 ioaddr = sc->sn_io_addr; 1250 1251 /* 1252 * First, see if the high byte is 0x33 1253 */ 1254 bank = inw(ioaddr + BANK_SELECT_REG_W); 1255 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1256 #ifdef SN_DEBUG 1257 device_printf(dev, "test1 failed\n"); 1258 #endif 1259 goto error; 1260 } 1261 /* 1262 * The above MIGHT indicate a device, but I need to write to further 1263 * test this. Go to bank 0, then test that the register still 1264 * reports the high byte is 0x33. 1265 */ 1266 outw(ioaddr + BANK_SELECT_REG_W, 0x0000); 1267 bank = inw(ioaddr + BANK_SELECT_REG_W); 1268 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1269 #ifdef SN_DEBUG 1270 device_printf(dev, "test2 failed\n"); 1271 #endif 1272 goto error; 1273 } 1274 /* 1275 * well, we've already written once, so hopefully another time won't 1276 * hurt. This time, I need to switch the bank register to bank 1, so 1277 * I can access the base address register. The contents of the 1278 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1279 * to match the I/O port address where the adapter is being probed. 1280 */ 1281 outw(ioaddr + BANK_SELECT_REG_W, 0x0001); 1282 base_address_register = inw(ioaddr + BASE_ADDR_REG_W); 1283 1284 /* 1285 * This test is nonsence on PC-card architecture, so if 1286 * pccard == 1, skip this test. (hosokawa) 1287 */ 1288 if (!pccard && (ioaddr != (base_address_register >> 3 & 0x3E0))) { 1289 1290 /* 1291 * Well, the base address register didn't match. Must not 1292 * have been a SMC chip after all. 1293 */ 1294 /* 1295 * kprintf("sn: ioaddr %x doesn't match card configuration 1296 * (%x)\n", ioaddr, base_address_register >> 3 & 0x3E0 ); 1297 */ 1298 1299 #ifdef SN_DEBUG 1300 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1301 "base_address_register = 0x%x\n", ioaddr, 1302 base_address_register >> 3 & 0x3E0); 1303 #endif 1304 goto error; 1305 } 1306 /* 1307 * Check if the revision register is something that I recognize. 1308 * These might need to be added to later, as future revisions could 1309 * be added. 1310 */ 1311 outw(ioaddr + BANK_SELECT_REG_W, 0x3); 1312 revision_register = inw(ioaddr + REVISION_REG_W); 1313 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1314 1315 /* 1316 * I don't regonize this chip, so... 1317 */ 1318 #ifdef SN_DEBUG 1319 device_printf(dev, "test4 failed\n"); 1320 #endif 1321 goto error; 1322 } 1323 /* 1324 * at this point I'll assume that the chip is an SMC9xxx. It might be 1325 * prudent to check a listing of MAC addresses against the hardware 1326 * address, or do some other tests. 1327 */ 1328 sn_deactivate(dev); 1329 return 0; 1330 error: 1331 sn_deactivate(dev); 1332 return ENXIO; 1333 } 1334 1335 #define MCFSZ 8 1336 1337 static void 1338 sn_setmcast(struct sn_softc *sc) 1339 { 1340 struct ifnet *ifp = (struct ifnet *)sc; 1341 int flags; 1342 1343 /* 1344 * Set the receiver filter. We want receive enabled and auto strip 1345 * of CRC from received packet. If we are promiscuous then set that 1346 * bit too. 1347 */ 1348 flags = RCR_ENABLE | RCR_STRIP_CRC; 1349 1350 if (ifp->if_flags & IFF_PROMISC) { 1351 flags |= RCR_PROMISC | RCR_ALMUL; 1352 } else if (ifp->if_flags & IFF_ALLMULTI) { 1353 flags |= RCR_ALMUL; 1354 } else { 1355 u_char mcf[MCFSZ]; 1356 if (sn_getmcf(&sc->arpcom, mcf)) { 1357 /* set filter */ 1358 SMC_SELECT_BANK(3); 1359 outw(BASE + MULTICAST1_REG_W, 1360 ((u_short)mcf[1] << 8) | mcf[0]); 1361 outw(BASE + MULTICAST2_REG_W, 1362 ((u_short)mcf[3] << 8) | mcf[2]); 1363 outw(BASE + MULTICAST3_REG_W, 1364 ((u_short)mcf[5] << 8) | mcf[4]); 1365 outw(BASE + MULTICAST4_REG_W, 1366 ((u_short)mcf[7] << 8) | mcf[6]); 1367 } else { 1368 flags |= RCR_ALMUL; 1369 } 1370 } 1371 SMC_SELECT_BANK(0); 1372 outw(BASE + RECV_CONTROL_REG_W, flags); 1373 } 1374 1375 static int 1376 sn_getmcf(struct arpcom *ac, u_char *mcf) 1377 { 1378 int i; 1379 u_int index, index2; 1380 u_char *af = (u_char *) mcf; 1381 struct ifmultiaddr *ifma; 1382 1383 bzero(mcf, MCFSZ); 1384 1385 TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) { 1386 if (ifma->ifma_addr->sa_family != AF_LINK) 1387 return 0; 1388 index = smc_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f; 1389 index2 = 0; 1390 for (i = 0; i < 6; i++) { 1391 index2 <<= 1; 1392 index2 |= (index & 0x01); 1393 index >>= 1; 1394 } 1395 af[index2 >> 3] |= 1 << (index2 & 7); 1396 } 1397 return 1; /* use multicast filter */ 1398 } 1399 1400 static u_int 1401 smc_crc(u_char *s) 1402 { 1403 int perByte; 1404 int perBit; 1405 const u_int poly = 0xedb88320; 1406 u_int v = 0xffffffff; 1407 u_char c; 1408 1409 for (perByte = 0; perByte < ETHER_ADDR_LEN; perByte++) { 1410 c = s[perByte]; 1411 for (perBit = 0; perBit < 8; perBit++) { 1412 v = (v >> 1)^(((v ^ c) & 0x01) ? poly : 0); 1413 c >>= 1; 1414 } 1415 } 1416 return v; 1417 } 1418