1 /* 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/sn/if_sn.c,v 1.7.2.3 2001/02/04 04:38:38 toshi Exp $ 32 * $DragonFly: src/sys/dev/netif/sn/if_sn.c,v 1.29 2008/08/17 04:32:34 sephe Exp $ 33 */ 34 35 /* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o The hardware multicast filter isn't used yet. 68 * o Setting of the hardware address isn't supported. 69 * o Hardware padding isn't used. 70 */ 71 72 /* 73 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 74 * 75 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 76 * BSD-nomads, Tokyo, Japan. 77 */ 78 /* 79 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 80 * Special thanks to itojun@itojun.org 81 */ 82 83 #undef SN_DEBUG /* (by hosokawa) */ 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/interrupt.h> 89 #include <sys/errno.h> 90 #include <sys/sockio.h> 91 #include <sys/malloc.h> 92 #include <sys/mbuf.h> 93 #include <sys/socket.h> 94 #include <sys/syslog.h> 95 #include <sys/serialize.h> 96 #include <sys/module.h> 97 #include <sys/bus.h> 98 #include <sys/rman.h> 99 #include <sys/thread2.h> 100 101 #include <net/ethernet.h> 102 #include <net/if.h> 103 #include <net/ifq_var.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_types.h> 107 #include <net/if_mib.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/in_var.h> 113 #include <netinet/ip.h> 114 #endif 115 116 #include <net/bpf.h> 117 #include <net/bpfdesc.h> 118 119 #include <machine/clock.h> 120 121 #include "if_snreg.h" 122 #include "if_snvar.h" 123 124 /* Exported variables */ 125 devclass_t sn_devclass; 126 127 static int snioctl(struct ifnet * ifp, u_long, caddr_t, struct ucred *); 128 129 static void snresume(struct ifnet *); 130 131 void sninit(void *); 132 void snread(struct ifnet *); 133 void snreset(struct sn_softc *); 134 void snstart(struct ifnet *); 135 void snstop(struct sn_softc *); 136 void snwatchdog(struct ifnet *); 137 138 static void sn_setmcast(struct sn_softc *); 139 static int sn_getmcf(struct arpcom *ac, u_char *mcf); 140 static u_int smc_crc(u_char *); 141 142 DECLARE_DUMMY_MODULE(if_sn); 143 144 /* I (GB) have been unlucky getting the hardware padding 145 * to work properly. 146 */ 147 #define SW_PAD 148 149 static const char *chip_ids[15] = { 150 NULL, NULL, NULL, 151 /* 3 */ "SMC91C90/91C92", 152 /* 4 */ "SMC91C94", 153 /* 5 */ "SMC91C95", 154 NULL, 155 /* 7 */ "SMC91C100", 156 /* 8 */ "SMC91C100FD", 157 NULL, NULL, NULL, 158 NULL, NULL, NULL 159 }; 160 161 int 162 sn_attach(device_t dev) 163 { 164 struct sn_softc *sc = device_get_softc(dev); 165 struct ifnet *ifp = &sc->arpcom.ac_if; 166 u_short i; 167 u_char *p; 168 int rev; 169 u_short address; 170 int j; 171 int error; 172 173 sn_activate(dev); 174 175 snstop(sc); 176 177 sc->dev = dev; 178 sc->pages_wanted = -1; 179 180 device_printf(dev, " "); 181 182 SMC_SELECT_BANK(3); 183 rev = inw(BASE + REVISION_REG_W); 184 if (chip_ids[(rev >> 4) & 0xF]) 185 kprintf("%s ", chip_ids[(rev >> 4) & 0xF]); 186 187 SMC_SELECT_BANK(1); 188 i = inw(BASE + CONFIG_REG_W); 189 kprintf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 190 191 if (sc->pccard_enaddr) 192 for (j = 0; j < 3; j++) { 193 u_short w; 194 195 w = (u_short)sc->arpcom.ac_enaddr[j * 2] | 196 (((u_short)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8); 197 outw(BASE + IAR_ADDR0_REG_W + j * 2, w); 198 } 199 200 /* 201 * Read the station address from the chip. The MAC address is bank 1, 202 * regs 4 - 9 203 */ 204 SMC_SELECT_BANK(1); 205 p = (u_char *) & sc->arpcom.ac_enaddr; 206 for (i = 0; i < 6; i += 2) { 207 address = inw(BASE + IAR_ADDR0_REG_W + i); 208 p[i + 1] = address >> 8; 209 p[i] = address & 0xFF; 210 } 211 ifp->if_softc = sc; 212 if_initname(ifp, "sn", device_get_unit(dev)); 213 ifp->if_mtu = ETHERMTU; 214 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 215 ifp->if_start = snstart; 216 ifp->if_ioctl = snioctl; 217 ifp->if_watchdog = snwatchdog; 218 ifp->if_init = sninit; 219 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 220 ifq_set_ready(&ifp->if_snd); 221 ifp->if_timer = 0; 222 223 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 224 225 error = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 226 sn_intr, sc, &sc->intrhand, 227 ifp->if_serializer); 228 if (error) { 229 ether_ifdetach(ifp); 230 sn_deactivate(dev); 231 return error; 232 } 233 234 ifp->if_cpuid = rman_get_cpuid(sc->irq_res); 235 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 236 237 return 0; 238 } 239 240 241 /* 242 * Reset and initialize the chip 243 */ 244 void 245 sninit(void *xsc) 246 { 247 struct sn_softc *sc = xsc; 248 struct ifnet *ifp = &sc->arpcom.ac_if; 249 int flags; 250 int mask; 251 252 /* 253 * This resets the registers mostly to defaults, but doesn't affect 254 * EEPROM. After the reset cycle, we pause briefly for the chip to 255 * be happy. 256 */ 257 SMC_SELECT_BANK(0); 258 outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET); 259 SMC_DELAY(); 260 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 261 SMC_DELAY(); 262 SMC_DELAY(); 263 264 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 265 266 /* 267 * Set the control register to automatically release succesfully 268 * transmitted packets (making the best use out of our limited 269 * memory) and to enable the EPH interrupt on certain TX errors. 270 */ 271 SMC_SELECT_BANK(1); 272 outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 273 CTR_CR_ENABLE | CTR_LE_ENABLE)); 274 275 /* Set squelch level to 240mV (default 480mV) */ 276 flags = inw(BASE + CONFIG_REG_W); 277 flags |= CR_SET_SQLCH; 278 outw(BASE + CONFIG_REG_W, flags); 279 280 /* 281 * Reset the MMU and wait for it to be un-busy. 282 */ 283 SMC_SELECT_BANK(2); 284 outw(BASE + MMU_CMD_REG_W, MMUCR_RESET); 285 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 286 ; 287 288 /* 289 * Disable all interrupts 290 */ 291 outb(BASE + INTR_MASK_REG_B, 0x00); 292 293 sn_setmcast(sc); 294 295 /* 296 * Set the transmitter control. We want it enabled. 297 */ 298 flags = TCR_ENABLE; 299 300 #ifndef SW_PAD 301 /* 302 * I (GB) have been unlucky getting this to work. 303 */ 304 flags |= TCR_PAD_ENABLE; 305 #endif /* SW_PAD */ 306 307 outw(BASE + TXMIT_CONTROL_REG_W, flags); 308 309 310 /* 311 * Now, enable interrupts 312 */ 313 SMC_SELECT_BANK(2); 314 315 mask = IM_EPH_INT | 316 IM_RX_OVRN_INT | 317 IM_RCV_INT | 318 IM_TX_INT; 319 320 outb(BASE + INTR_MASK_REG_B, mask); 321 sc->intr_mask = mask; 322 sc->pages_wanted = -1; 323 324 325 /* 326 * Mark the interface running but not active. 327 */ 328 ifp->if_flags |= IFF_RUNNING; 329 ifp->if_flags &= ~IFF_OACTIVE; 330 331 /* 332 * Attempt to push out any waiting packets. 333 */ 334 if_devstart(ifp); 335 } 336 337 338 void 339 snstart(struct ifnet *ifp) 340 { 341 struct sn_softc *sc = ifp->if_softc; 342 u_int len; 343 struct mbuf *m; 344 struct mbuf *top; 345 int pad; 346 int mask; 347 u_short length; 348 u_short numPages; 349 u_char packet_no; 350 int time_out; 351 352 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 353 return; 354 355 if (sc->pages_wanted != -1) { 356 /* XXX should never happen */ 357 kprintf("%s: snstart() while memory allocation pending\n", 358 ifp->if_xname); 359 ifp->if_flags |= IFF_OACTIVE; 360 return; 361 } 362 startagain: 363 364 /* 365 * Sneak a peek at the next packet 366 */ 367 m = ifq_dequeue(&ifp->if_snd, NULL); 368 if (m == NULL) 369 return; 370 371 /* 372 * Compute the frame length and set pad to give an overall even 373 * number of bytes. Below we assume that the packet length is even. 374 */ 375 for (len = 0, top = m; m; m = m->m_next) 376 len += m->m_len; 377 378 pad = (len & 1); 379 380 /* 381 * We drop packets that are too large. Perhaps we should truncate 382 * them instead? 383 */ 384 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 385 kprintf("%s: large packet discarded (A)\n", ifp->if_xname); 386 ++sc->arpcom.ac_if.if_oerrors; 387 m_freem(top); 388 goto readcheck; 389 } 390 #ifdef SW_PAD 391 392 /* 393 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 394 */ 395 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 396 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 397 398 #endif /* SW_PAD */ 399 400 length = pad + len; 401 402 /* 403 * The MMU wants the number of pages to be the number of 256 byte 404 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 405 * include space for the status word, byte count and control bytes in 406 * the allocation request. 407 */ 408 numPages = (length + 6) >> 8; 409 410 411 /* 412 * Now, try to allocate the memory 413 */ 414 SMC_SELECT_BANK(2); 415 outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 416 417 /* 418 * Wait a short amount of time to see if the allocation request 419 * completes. Otherwise, I enable the interrupt and wait for 420 * completion asyncronously. 421 */ 422 423 time_out = MEMORY_WAIT_TIME; 424 do { 425 if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT) 426 break; 427 } while (--time_out); 428 429 if (!time_out) { 430 431 /* 432 * No memory now. Oh well, wait until the chip finds memory 433 * later. Remember how many pages we were asking for and 434 * enable the allocation completion interrupt. Also set a 435 * watchdog in case we miss the interrupt. We mark the 436 * interface active since there is no point in attempting an 437 * snstart() until after the memory is available. 438 */ 439 mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT; 440 outb(BASE + INTR_MASK_REG_B, mask); 441 sc->intr_mask = mask; 442 443 ifp->if_timer = 1; 444 ifp->if_flags |= IFF_OACTIVE; 445 sc->pages_wanted = numPages; 446 ifq_prepend(&ifp->if_snd, top); 447 448 return; 449 } 450 /* 451 * The memory allocation completed. Check the results. 452 */ 453 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 454 if (packet_no & ARR_FAILED) { 455 kprintf("%s: Memory allocation failed\n", ifp->if_xname); 456 ifq_prepend(&ifp->if_snd, top); 457 goto startagain; 458 } 459 /* 460 * We have a packet number, so tell the card to use it. 461 */ 462 outb(BASE + PACKET_NUM_REG_B, packet_no); 463 464 /* 465 * Point to the beginning of the packet 466 */ 467 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 468 469 /* 470 * Send the packet length (+6 for status, length and control byte) 471 * and the status word (set to zeros) 472 */ 473 outw(BASE + DATA_REG_W, 0); 474 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 475 outb(BASE + DATA_REG_B, (length + 6) >> 8); 476 477 /* 478 * Push out the data to the card. 479 */ 480 for (m = top; m != NULL; m = m->m_next) { 481 482 /* 483 * Push out words. 484 */ 485 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 486 487 /* 488 * Push out remaining byte. 489 */ 490 if (m->m_len & 1) 491 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 492 } 493 494 /* 495 * Push out padding. 496 */ 497 while (pad > 1) { 498 outw(BASE + DATA_REG_W, 0); 499 pad -= 2; 500 } 501 if (pad) 502 outb(BASE + DATA_REG_B, 0); 503 504 /* 505 * Push out control byte and unused packet byte The control byte is 0 506 * meaning the packet is even lengthed and no special CRC handling is 507 * desired. 508 */ 509 outw(BASE + DATA_REG_W, 0); 510 511 /* 512 * Enable the interrupts and let the chipset deal with it Also set a 513 * watchdog in case we miss the interrupt. 514 */ 515 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 516 outb(BASE + INTR_MASK_REG_B, mask); 517 sc->intr_mask = mask; 518 519 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 520 521 ifp->if_flags |= IFF_OACTIVE; 522 ifp->if_timer = 1; 523 524 BPF_MTAP(ifp, top); 525 526 ifp->if_opackets++; 527 m_freem(top); 528 529 readcheck: 530 531 /* 532 * Is another packet coming in? We don't want to overflow the tiny 533 * RX FIFO. If nothing has arrived then attempt to queue another 534 * transmit packet. 535 */ 536 if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY) 537 goto startagain; 538 } 539 540 541 542 /* Resume a packet transmit operation after a memory allocation 543 * has completed. 544 * 545 * This is basically a hacked up copy of snstart() which handles 546 * a completed memory allocation the same way snstart() does. 547 * It then passes control to snstart to handle any other queued 548 * packets. 549 */ 550 static void 551 snresume(struct ifnet *ifp) 552 { 553 struct sn_softc *sc = ifp->if_softc; 554 u_int len; 555 struct mbuf *m; 556 struct mbuf *top; 557 int pad; 558 int mask; 559 u_short length; 560 u_short numPages; 561 u_short pages_wanted; 562 u_char packet_no; 563 564 if (sc->pages_wanted < 0) 565 return; 566 567 pages_wanted = sc->pages_wanted; 568 sc->pages_wanted = -1; 569 570 /* 571 * Sneak a peek at the next packet 572 */ 573 m = ifq_dequeue(&ifp->if_snd, NULL); 574 if (m == NULL) { 575 kprintf("%s: snresume() with nothing to send\n", 576 ifp->if_xname); 577 return; 578 } 579 580 /* 581 * Compute the frame length and set pad to give an overall even 582 * number of bytes. Below we assume that the packet length is even. 583 */ 584 for (len = 0, top = m; m; m = m->m_next) 585 len += m->m_len; 586 587 pad = (len & 1); 588 589 /* 590 * We drop packets that are too large. Perhaps we should truncate 591 * them instead? 592 */ 593 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 594 kprintf("%s: large packet discarded (B)\n", ifp->if_xname); 595 ++ifp->if_oerrors; 596 m_freem(top); 597 return; 598 } 599 #ifdef SW_PAD 600 601 /* 602 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 603 */ 604 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 605 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 606 607 #endif /* SW_PAD */ 608 609 length = pad + len; 610 611 612 /* 613 * The MMU wants the number of pages to be the number of 256 byte 614 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 615 * include space for the status word, byte count and control bytes in 616 * the allocation request. 617 */ 618 numPages = (length + 6) >> 8; 619 620 621 SMC_SELECT_BANK(2); 622 623 /* 624 * The memory allocation completed. Check the results. If it failed, 625 * we simply set a watchdog timer and hope for the best. 626 */ 627 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 628 if (packet_no & ARR_FAILED) { 629 kprintf("%s: Memory allocation failed. Weird.\n", ifp->if_xname); 630 ifp->if_timer = 1; 631 ifq_prepend(&ifp->if_snd, top); 632 goto try_start; 633 } 634 /* 635 * We have a packet number, so tell the card to use it. 636 */ 637 outb(BASE + PACKET_NUM_REG_B, packet_no); 638 639 /* 640 * Now, numPages should match the pages_wanted recorded when the 641 * memory allocation was initiated. 642 */ 643 if (pages_wanted != numPages) { 644 kprintf("%s: memory allocation wrong size. Weird.\n", ifp->if_xname); 645 /* 646 * If the allocation was the wrong size we simply release the 647 * memory once it is granted. Wait for the MMU to be un-busy. 648 */ 649 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 650 ; 651 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 652 653 ifq_prepend(&ifp->if_snd, top); 654 return; 655 } 656 /* 657 * Point to the beginning of the packet 658 */ 659 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 660 661 /* 662 * Send the packet length (+6 for status, length and control byte) 663 * and the status word (set to zeros) 664 */ 665 outw(BASE + DATA_REG_W, 0); 666 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 667 outb(BASE + DATA_REG_B, (length + 6) >> 8); 668 669 /* 670 * Push out the data to the card. 671 */ 672 for (m = top; m != NULL; m = m->m_next) { 673 674 /* 675 * Push out words. 676 */ 677 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 678 679 /* 680 * Push out remaining byte. 681 */ 682 if (m->m_len & 1) 683 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 684 } 685 686 /* 687 * Push out padding. 688 */ 689 while (pad > 1) { 690 outw(BASE + DATA_REG_W, 0); 691 pad -= 2; 692 } 693 if (pad) 694 outb(BASE + DATA_REG_B, 0); 695 696 /* 697 * Push out control byte and unused packet byte The control byte is 0 698 * meaning the packet is even lengthed and no special CRC handling is 699 * desired. 700 */ 701 outw(BASE + DATA_REG_W, 0); 702 703 /* 704 * Enable the interrupts and let the chipset deal with it Also set a 705 * watchdog in case we miss the interrupt. 706 */ 707 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 708 outb(BASE + INTR_MASK_REG_B, mask); 709 sc->intr_mask = mask; 710 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 711 712 BPF_MTAP(ifp, top); 713 714 ifp->if_opackets++; 715 m_freem(top); 716 717 try_start: 718 719 /* 720 * Now pass control to snstart() to queue any additional packets 721 */ 722 ifp->if_flags &= ~IFF_OACTIVE; 723 if_devstart(ifp); 724 725 /* 726 * We've sent something, so we're active. Set a watchdog in case the 727 * TX_EMPTY interrupt is lost. 728 */ 729 ifp->if_flags |= IFF_OACTIVE; 730 ifp->if_timer = 1; 731 } 732 733 734 void 735 sn_intr(void *arg) 736 { 737 int status, interrupts; 738 struct sn_softc *sc = (struct sn_softc *) arg; 739 struct ifnet *ifp = &sc->arpcom.ac_if; 740 741 /* 742 * Chip state registers 743 */ 744 u_char mask; 745 u_char packet_no; 746 u_short tx_status; 747 u_short card_stats; 748 749 /* 750 * Clear the watchdog. 751 */ 752 ifp->if_timer = 0; 753 754 SMC_SELECT_BANK(2); 755 756 /* 757 * Obtain the current interrupt mask and clear the hardware mask 758 * while servicing interrupts. 759 */ 760 mask = inb(BASE + INTR_MASK_REG_B); 761 outb(BASE + INTR_MASK_REG_B, 0x00); 762 763 /* 764 * Get the set of interrupts which occurred and eliminate any which 765 * are masked. 766 */ 767 interrupts = inb(BASE + INTR_STAT_REG_B); 768 status = interrupts & mask; 769 770 /* 771 * Now, process each of the interrupt types. 772 */ 773 774 /* 775 * Receive Overrun. 776 */ 777 if (status & IM_RX_OVRN_INT) { 778 779 /* 780 * Acknowlege Interrupt 781 */ 782 SMC_SELECT_BANK(2); 783 outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT); 784 785 ++sc->arpcom.ac_if.if_ierrors; 786 } 787 /* 788 * Got a packet. 789 */ 790 if (status & IM_RCV_INT) { 791 #if 1 792 int packet_number; 793 794 SMC_SELECT_BANK(2); 795 packet_number = inw(BASE + FIFO_PORTS_REG_W); 796 797 if (packet_number & FIFO_REMPTY) { 798 799 /* 800 * we got called , but nothing was on the FIFO 801 */ 802 kprintf("sn: Receive interrupt with nothing on FIFO\n"); 803 804 goto out; 805 } 806 #endif 807 snread(ifp); 808 } 809 /* 810 * An on-card memory allocation came through. 811 */ 812 if (status & IM_ALLOC_INT) { 813 814 /* 815 * Disable this interrupt. 816 */ 817 mask &= ~IM_ALLOC_INT; 818 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 819 snresume(&sc->arpcom.ac_if); 820 } 821 /* 822 * TX Completion. Handle a transmit error message. This will only be 823 * called when there is an error, because of the AUTO_RELEASE mode. 824 */ 825 if (status & IM_TX_INT) { 826 827 /* 828 * Acknowlege Interrupt 829 */ 830 SMC_SELECT_BANK(2); 831 outb(BASE + INTR_ACK_REG_B, IM_TX_INT); 832 833 packet_no = inw(BASE + FIFO_PORTS_REG_W); 834 packet_no &= FIFO_TX_MASK; 835 836 /* 837 * select this as the packet to read from 838 */ 839 outb(BASE + PACKET_NUM_REG_B, packet_no); 840 841 /* 842 * Position the pointer to the first word from this packet 843 */ 844 outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 845 846 /* 847 * Fetch the TX status word. The value found here will be a 848 * copy of the EPH_STATUS_REG_W at the time the transmit 849 * failed. 850 */ 851 tx_status = inw(BASE + DATA_REG_W); 852 853 if (tx_status & EPHSR_TX_SUC) { 854 device_printf(sc->dev, 855 "Successful packet caused interrupt\n"); 856 } else { 857 ++sc->arpcom.ac_if.if_oerrors; 858 } 859 860 if (tx_status & EPHSR_LATCOL) 861 ++sc->arpcom.ac_if.if_collisions; 862 863 /* 864 * Some of these errors will have disabled transmit. 865 * Re-enable transmit now. 866 */ 867 SMC_SELECT_BANK(0); 868 869 #ifdef SW_PAD 870 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE); 871 #else 872 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 873 #endif /* SW_PAD */ 874 875 /* 876 * kill the failed packet. Wait for the MMU to be un-busy. 877 */ 878 SMC_SELECT_BANK(2); 879 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 880 ; 881 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 882 883 /* 884 * Attempt to queue more transmits. 885 */ 886 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 887 if_devstart(&sc->arpcom.ac_if); 888 } 889 /* 890 * Transmit underrun. We use this opportunity to update transmit 891 * statistics from the card. 892 */ 893 if (status & IM_TX_EMPTY_INT) { 894 895 /* 896 * Acknowlege Interrupt 897 */ 898 SMC_SELECT_BANK(2); 899 outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT); 900 901 /* 902 * Disable this interrupt. 903 */ 904 mask &= ~IM_TX_EMPTY_INT; 905 906 SMC_SELECT_BANK(0); 907 card_stats = inw(BASE + COUNTER_REG_W); 908 909 /* 910 * Single collisions 911 */ 912 sc->arpcom.ac_if.if_collisions += card_stats & ECR_COLN_MASK; 913 914 /* 915 * Multiple collisions 916 */ 917 sc->arpcom.ac_if.if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 918 919 SMC_SELECT_BANK(2); 920 921 /* 922 * Attempt to enqueue some more stuff. 923 */ 924 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 925 if_devstart(&sc->arpcom.ac_if); 926 } 927 /* 928 * Some other error. Try to fix it by resetting the adapter. 929 */ 930 if (status & IM_EPH_INT) { 931 snstop(sc); 932 sninit(sc); 933 } 934 935 out: 936 /* 937 * Handled all interrupt sources. 938 */ 939 940 SMC_SELECT_BANK(2); 941 942 /* 943 * Reestablish interrupts from mask which have not been deselected 944 * during this interrupt. Note that the hardware mask, which was set 945 * to 0x00 at the start of this service routine, may have been 946 * updated by one or more of the interrupt handers and we must let 947 * those new interrupts stay enabled here. 948 */ 949 mask |= inb(BASE + INTR_MASK_REG_B); 950 outb(BASE + INTR_MASK_REG_B, mask); 951 sc->intr_mask = mask; 952 } 953 954 void 955 snread(struct ifnet *ifp) 956 { 957 struct sn_softc *sc = ifp->if_softc; 958 struct mbuf *m; 959 short status; 960 int packet_number; 961 u_short packet_length; 962 u_char *data; 963 964 SMC_SELECT_BANK(2); 965 #if 0 966 packet_number = inw(BASE + FIFO_PORTS_REG_W); 967 968 if (packet_number & FIFO_REMPTY) { 969 970 /* 971 * we got called , but nothing was on the FIFO 972 */ 973 kprintf("sn: Receive interrupt with nothing on FIFO\n"); 974 return; 975 } 976 #endif 977 read_another: 978 979 /* 980 * Start reading from the start of the packet. Since PTR_RCV is set, 981 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 982 */ 983 outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 984 985 /* 986 * First two words are status and packet_length 987 */ 988 status = inw(BASE + DATA_REG_W); 989 packet_length = inw(BASE + DATA_REG_W) & RLEN_MASK; 990 991 /* 992 * The packet length contains 3 extra words: status, length, and a 993 * extra word with the control byte. 994 */ 995 packet_length -= 6; 996 997 /* 998 * Account for receive errors and discard. 999 */ 1000 if (status & RS_ERRORS) { 1001 ++ifp->if_ierrors; 1002 goto out; 1003 } 1004 /* 1005 * A packet is received. 1006 */ 1007 1008 /* 1009 * Adjust for odd-length packet. 1010 */ 1011 if (status & RS_ODDFRAME) 1012 packet_length++; 1013 1014 /* 1015 * Allocate a header mbuf from the kernel. 1016 */ 1017 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1018 if (m == NULL) 1019 goto out; 1020 1021 m->m_pkthdr.rcvif = ifp; 1022 m->m_pkthdr.len = m->m_len = packet_length; 1023 1024 /* 1025 * Attach an mbuf cluster 1026 */ 1027 MCLGET(m, MB_DONTWAIT); 1028 1029 /* 1030 * Insist on getting a cluster 1031 */ 1032 if ((m->m_flags & M_EXT) == 0) { 1033 m_freem(m); 1034 ++ifp->if_ierrors; 1035 kprintf("sn: snread() kernel memory allocation problem\n"); 1036 goto out; 1037 } 1038 1039 /* 1040 * Get packet, including link layer address, from interface. 1041 */ 1042 1043 data = mtod(m, u_char *); 1044 insw(BASE + DATA_REG_W, data, packet_length >> 1); 1045 if (packet_length & 1) { 1046 data += packet_length & ~1; 1047 *data = inb(BASE + DATA_REG_B); 1048 } 1049 ++ifp->if_ipackets; 1050 1051 m->m_pkthdr.len = m->m_len = packet_length; 1052 1053 ifp->if_input(ifp, m); 1054 1055 out: 1056 1057 /* 1058 * Error or good, tell the card to get rid of this packet Wait for 1059 * the MMU to be un-busy. 1060 */ 1061 SMC_SELECT_BANK(2); 1062 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1063 ; 1064 outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE); 1065 1066 /* 1067 * Check whether another packet is ready 1068 */ 1069 packet_number = inw(BASE + FIFO_PORTS_REG_W); 1070 if (packet_number & FIFO_REMPTY) { 1071 return; 1072 } 1073 goto read_another; 1074 } 1075 1076 1077 /* 1078 * Handle IOCTLS. This function is completely stolen from if_ep.c 1079 * As with its progenitor, it does not handle hardware address 1080 * changes. 1081 */ 1082 static int 1083 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1084 { 1085 struct sn_softc *sc = ifp->if_softc; 1086 int error = 0; 1087 1088 switch (cmd) { 1089 case SIOCSIFFLAGS: 1090 if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) { 1091 ifp->if_flags &= ~IFF_RUNNING; 1092 snstop(sc); 1093 break; 1094 } else { 1095 /* reinitialize card on any parameter change */ 1096 sninit(sc); 1097 break; 1098 } 1099 break; 1100 1101 #ifdef notdef 1102 case SIOCGHWADDR: 1103 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data, 1104 sizeof(sc->sc_addr)); 1105 break; 1106 #endif 1107 1108 case SIOCADDMULTI: 1109 /* update multicast filter list. */ 1110 sn_setmcast(sc); 1111 error = 0; 1112 break; 1113 case SIOCDELMULTI: 1114 /* update multicast filter list. */ 1115 sn_setmcast(sc); 1116 error = 0; 1117 break; 1118 default: 1119 error = ether_ioctl(ifp, cmd, data); 1120 break; 1121 } 1122 1123 return (error); 1124 } 1125 1126 void 1127 snreset(struct sn_softc *sc) 1128 { 1129 snstop(sc); 1130 sninit(sc); 1131 } 1132 1133 void 1134 snwatchdog(struct ifnet *ifp) 1135 { 1136 sn_intr(ifp->if_softc); 1137 } 1138 1139 1140 /* 1. zero the interrupt mask 1141 * 2. clear the enable receive flag 1142 * 3. clear the enable xmit flags 1143 */ 1144 void 1145 snstop(struct sn_softc *sc) 1146 { 1147 1148 struct ifnet *ifp = &sc->arpcom.ac_if; 1149 1150 /* 1151 * Clear interrupt mask; disable all interrupts. 1152 */ 1153 SMC_SELECT_BANK(2); 1154 outb(BASE + INTR_MASK_REG_B, 0x00); 1155 1156 /* 1157 * Disable transmitter and Receiver 1158 */ 1159 SMC_SELECT_BANK(0); 1160 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 1161 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 1162 1163 /* 1164 * Cancel watchdog. 1165 */ 1166 ifp->if_timer = 0; 1167 } 1168 1169 1170 int 1171 sn_activate(device_t dev) 1172 { 1173 struct sn_softc *sc = device_get_softc(dev); 1174 1175 sc->port_rid = 0; 1176 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1177 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1178 if (!sc->port_res) { 1179 #ifdef SN_DEBUG 1180 device_printf(dev, "Cannot allocate ioport\n"); 1181 #endif 1182 return ENOMEM; 1183 } 1184 1185 sc->irq_rid = 0; 1186 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1187 RF_ACTIVE); 1188 if (!sc->irq_res) { 1189 #ifdef SN_DEBUG 1190 device_printf(dev, "Cannot allocate irq\n"); 1191 #endif 1192 sn_deactivate(dev); 1193 return ENOMEM; 1194 } 1195 1196 sc->sn_io_addr = rman_get_start(sc->port_res); 1197 return (0); 1198 } 1199 1200 void 1201 sn_deactivate(device_t dev) 1202 { 1203 struct sn_softc *sc = device_get_softc(dev); 1204 1205 if (sc->port_res) 1206 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1207 sc->port_res); 1208 sc->port_res = 0; 1209 if (sc->irq_res) 1210 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1211 sc->irq_res); 1212 sc->irq_res = 0; 1213 return; 1214 } 1215 1216 /* 1217 * Function: sn_probe( device_t dev, int pccard ) 1218 * 1219 * Purpose: 1220 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1221 * Tries to cause as little damage as possible if it's not a SMC chip. 1222 * Returns a 0 on success 1223 * 1224 * Algorithm: 1225 * (1) see if the high byte of BANK_SELECT is 0x33 1226 * (2) compare the ioaddr with the base register's address 1227 * (3) see if I recognize the chip ID in the appropriate register 1228 * 1229 * 1230 */ 1231 int 1232 sn_probe(device_t dev, int pccard) 1233 { 1234 struct sn_softc *sc = device_get_softc(dev); 1235 u_int bank; 1236 u_short revision_register; 1237 u_short base_address_register; 1238 u_short ioaddr; 1239 int err; 1240 1241 if ((err = sn_activate(dev)) != 0) 1242 return err; 1243 1244 ioaddr = sc->sn_io_addr; 1245 1246 /* 1247 * First, see if the high byte is 0x33 1248 */ 1249 bank = inw(ioaddr + BANK_SELECT_REG_W); 1250 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1251 #ifdef SN_DEBUG 1252 device_printf(dev, "test1 failed\n"); 1253 #endif 1254 goto error; 1255 } 1256 /* 1257 * The above MIGHT indicate a device, but I need to write to further 1258 * test this. Go to bank 0, then test that the register still 1259 * reports the high byte is 0x33. 1260 */ 1261 outw(ioaddr + BANK_SELECT_REG_W, 0x0000); 1262 bank = inw(ioaddr + BANK_SELECT_REG_W); 1263 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1264 #ifdef SN_DEBUG 1265 device_printf(dev, "test2 failed\n"); 1266 #endif 1267 goto error; 1268 } 1269 /* 1270 * well, we've already written once, so hopefully another time won't 1271 * hurt. This time, I need to switch the bank register to bank 1, so 1272 * I can access the base address register. The contents of the 1273 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1274 * to match the I/O port address where the adapter is being probed. 1275 */ 1276 outw(ioaddr + BANK_SELECT_REG_W, 0x0001); 1277 base_address_register = inw(ioaddr + BASE_ADDR_REG_W); 1278 1279 /* 1280 * This test is nonsence on PC-card architecture, so if 1281 * pccard == 1, skip this test. (hosokawa) 1282 */ 1283 if (!pccard && (ioaddr != (base_address_register >> 3 & 0x3E0))) { 1284 1285 /* 1286 * Well, the base address register didn't match. Must not 1287 * have been a SMC chip after all. 1288 */ 1289 /* 1290 * kprintf("sn: ioaddr %x doesn't match card configuration 1291 * (%x)\n", ioaddr, base_address_register >> 3 & 0x3E0 ); 1292 */ 1293 1294 #ifdef SN_DEBUG 1295 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1296 "base_address_register = 0x%x\n", ioaddr, 1297 base_address_register >> 3 & 0x3E0); 1298 #endif 1299 goto error; 1300 } 1301 /* 1302 * Check if the revision register is something that I recognize. 1303 * These might need to be added to later, as future revisions could 1304 * be added. 1305 */ 1306 outw(ioaddr + BANK_SELECT_REG_W, 0x3); 1307 revision_register = inw(ioaddr + REVISION_REG_W); 1308 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1309 1310 /* 1311 * I don't regonize this chip, so... 1312 */ 1313 #ifdef SN_DEBUG 1314 device_printf(dev, "test4 failed\n"); 1315 #endif 1316 goto error; 1317 } 1318 /* 1319 * at this point I'll assume that the chip is an SMC9xxx. It might be 1320 * prudent to check a listing of MAC addresses against the hardware 1321 * address, or do some other tests. 1322 */ 1323 sn_deactivate(dev); 1324 return 0; 1325 error: 1326 sn_deactivate(dev); 1327 return ENXIO; 1328 } 1329 1330 #define MCFSZ 8 1331 1332 static void 1333 sn_setmcast(struct sn_softc *sc) 1334 { 1335 struct ifnet *ifp = (struct ifnet *)sc; 1336 int flags; 1337 1338 /* 1339 * Set the receiver filter. We want receive enabled and auto strip 1340 * of CRC from received packet. If we are promiscuous then set that 1341 * bit too. 1342 */ 1343 flags = RCR_ENABLE | RCR_STRIP_CRC; 1344 1345 if (ifp->if_flags & IFF_PROMISC) { 1346 flags |= RCR_PROMISC | RCR_ALMUL; 1347 } else if (ifp->if_flags & IFF_ALLMULTI) { 1348 flags |= RCR_ALMUL; 1349 } else { 1350 u_char mcf[MCFSZ]; 1351 if (sn_getmcf(&sc->arpcom, mcf)) { 1352 /* set filter */ 1353 SMC_SELECT_BANK(3); 1354 outw(BASE + MULTICAST1_REG_W, 1355 ((u_short)mcf[1] << 8) | mcf[0]); 1356 outw(BASE + MULTICAST2_REG_W, 1357 ((u_short)mcf[3] << 8) | mcf[2]); 1358 outw(BASE + MULTICAST3_REG_W, 1359 ((u_short)mcf[5] << 8) | mcf[4]); 1360 outw(BASE + MULTICAST4_REG_W, 1361 ((u_short)mcf[7] << 8) | mcf[6]); 1362 } else { 1363 flags |= RCR_ALMUL; 1364 } 1365 } 1366 SMC_SELECT_BANK(0); 1367 outw(BASE + RECV_CONTROL_REG_W, flags); 1368 } 1369 1370 static int 1371 sn_getmcf(struct arpcom *ac, u_char *mcf) 1372 { 1373 int i; 1374 u_int index, index2; 1375 u_char *af = (u_char *) mcf; 1376 struct ifmultiaddr *ifma; 1377 1378 bzero(mcf, MCFSZ); 1379 1380 TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) { 1381 if (ifma->ifma_addr->sa_family != AF_LINK) 1382 return 0; 1383 index = smc_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f; 1384 index2 = 0; 1385 for (i = 0; i < 6; i++) { 1386 index2 <<= 1; 1387 index2 |= (index & 0x01); 1388 index >>= 1; 1389 } 1390 af[index2 >> 3] |= 1 << (index2 & 7); 1391 } 1392 return 1; /* use multicast filter */ 1393 } 1394 1395 static u_int 1396 smc_crc(u_char *s) 1397 { 1398 int perByte; 1399 int perBit; 1400 const u_int poly = 0xedb88320; 1401 u_int v = 0xffffffff; 1402 u_char c; 1403 1404 for (perByte = 0; perByte < ETHER_ADDR_LEN; perByte++) { 1405 c = s[perByte]; 1406 for (perBit = 0; perBit < 8; perBit++) { 1407 v = (v >> 1)^(((v ^ c) & 0x01) ? poly : 0); 1408 c >>= 1; 1409 } 1410 } 1411 return v; 1412 } 1413