1 /*
2 * Single-precision vector sinh(x) function.
3 *
4 * Copyright (c) 2022-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "pl_sig.h"
10 #include "pl_test.h"
11
12 #include "v_expm1f_inline.h"
13
14 static const struct data
15 {
16 struct v_expm1f_data expm1f_consts;
17 uint32x4_t halff;
18 #if WANT_SIMD_EXCEPT
19 uint32x4_t tiny_bound, thresh;
20 #else
21 uint32x4_t oflow_bound;
22 #endif
23 } data = {
24 .expm1f_consts = V_EXPM1F_DATA,
25 .halff = V4 (0x3f000000),
26 #if WANT_SIMD_EXCEPT
27 /* 0x1.6a09e8p-32, below which expm1f underflows. */
28 .tiny_bound = V4 (0x2fb504f4),
29 /* asuint(oflow_bound) - asuint(tiny_bound). */
30 .thresh = V4 (0x12fbbbb3),
31 #else
32 /* 0x1.61814ep+6, above which expm1f helper overflows. */
33 .oflow_bound = V4 (0x42b0c0a7),
34 #endif
35 };
36
37 static float32x4_t NOINLINE VPCS_ATTR
special_case(float32x4_t x,float32x4_t y,uint32x4_t special)38 special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
39 {
40 return v_call_f32 (sinhf, x, y, special);
41 }
42
43 /* Approximation for vector single-precision sinh(x) using expm1.
44 sinh(x) = (exp(x) - exp(-x)) / 2.
45 The maximum error is 2.26 ULP:
46 _ZGVnN4v_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4
47 want 0x1.e469e4p-4. */
V_NAME_F1(sinh)48 float32x4_t VPCS_ATTR V_NAME_F1 (sinh) (float32x4_t x)
49 {
50 const struct data *d = ptr_barrier (&data);
51
52 uint32x4_t ix = vreinterpretq_u32_f32 (x);
53 float32x4_t ax = vabsq_f32 (x);
54 uint32x4_t iax = vreinterpretq_u32_f32 (ax);
55 uint32x4_t sign = veorq_u32 (ix, iax);
56 float32x4_t halfsign = vreinterpretq_f32_u32 (vorrq_u32 (sign, d->halff));
57
58 #if WANT_SIMD_EXCEPT
59 uint32x4_t special = vcgeq_u32 (vsubq_u32 (iax, d->tiny_bound), d->thresh);
60 ax = v_zerofy_f32 (ax, special);
61 #else
62 uint32x4_t special = vcgeq_u32 (iax, d->oflow_bound);
63 #endif
64
65 /* Up to the point that expm1f overflows, we can use it to calculate sinhf
66 using a slight rearrangement of the definition of asinh. This allows us
67 to retain acceptable accuracy for very small inputs. */
68 float32x4_t t = expm1f_inline (ax, &d->expm1f_consts);
69 t = vaddq_f32 (t, vdivq_f32 (t, vaddq_f32 (t, v_f32 (1.0))));
70
71 /* Fall back to the scalar variant for any lanes that should trigger an
72 exception. */
73 if (unlikely (v_any_u32 (special)))
74 return special_case (x, vmulq_f32 (t, halfsign), special);
75
76 return vmulq_f32 (t, halfsign);
77 }
78
79 PL_SIG (V, F, 1, sinh, -10.0, 10.0)
80 PL_TEST_ULP (V_NAME_F1 (sinh), 1.76)
81 PL_TEST_EXPECT_FENV (V_NAME_F1 (sinh), WANT_SIMD_EXCEPT)
82 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0, 0x2fb504f4, 1000)
83 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x2fb504f4, 0x42b0c0a7, 100000)
84 PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x42b0c0a7, inf, 1000)
85