1072a4ba8SAndrew Turner /*
2072a4ba8SAndrew Turner * Single-precision vector sinh(x) function.
3072a4ba8SAndrew Turner *
4072a4ba8SAndrew Turner * Copyright (c) 2022-2023, Arm Limited.
5072a4ba8SAndrew Turner * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6072a4ba8SAndrew Turner */
7072a4ba8SAndrew Turner
8072a4ba8SAndrew Turner #include "v_math.h"
9072a4ba8SAndrew Turner #include "pl_sig.h"
10072a4ba8SAndrew Turner #include "pl_test.h"
11072a4ba8SAndrew Turner
12072a4ba8SAndrew Turner #include "v_expm1f_inline.h"
13072a4ba8SAndrew Turner
14*5a02ffc3SAndrew Turner static const struct data
15072a4ba8SAndrew Turner {
16*5a02ffc3SAndrew Turner struct v_expm1f_data expm1f_consts;
17*5a02ffc3SAndrew Turner uint32x4_t halff;
18*5a02ffc3SAndrew Turner #if WANT_SIMD_EXCEPT
19*5a02ffc3SAndrew Turner uint32x4_t tiny_bound, thresh;
20*5a02ffc3SAndrew Turner #else
21*5a02ffc3SAndrew Turner uint32x4_t oflow_bound;
22*5a02ffc3SAndrew Turner #endif
23*5a02ffc3SAndrew Turner } data = {
24*5a02ffc3SAndrew Turner .expm1f_consts = V_EXPM1F_DATA,
25*5a02ffc3SAndrew Turner .halff = V4 (0x3f000000),
26*5a02ffc3SAndrew Turner #if WANT_SIMD_EXCEPT
27*5a02ffc3SAndrew Turner /* 0x1.6a09e8p-32, below which expm1f underflows. */
28*5a02ffc3SAndrew Turner .tiny_bound = V4 (0x2fb504f4),
29*5a02ffc3SAndrew Turner /* asuint(oflow_bound) - asuint(tiny_bound). */
30*5a02ffc3SAndrew Turner .thresh = V4 (0x12fbbbb3),
31*5a02ffc3SAndrew Turner #else
32*5a02ffc3SAndrew Turner /* 0x1.61814ep+6, above which expm1f helper overflows. */
33*5a02ffc3SAndrew Turner .oflow_bound = V4 (0x42b0c0a7),
34*5a02ffc3SAndrew Turner #endif
35*5a02ffc3SAndrew Turner };
36*5a02ffc3SAndrew Turner
37*5a02ffc3SAndrew Turner static float32x4_t NOINLINE VPCS_ATTR
special_case(float32x4_t x,float32x4_t y,uint32x4_t special)38*5a02ffc3SAndrew Turner special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
39*5a02ffc3SAndrew Turner {
40*5a02ffc3SAndrew Turner return v_call_f32 (sinhf, x, y, special);
41072a4ba8SAndrew Turner }
42072a4ba8SAndrew Turner
43072a4ba8SAndrew Turner /* Approximation for vector single-precision sinh(x) using expm1.
44072a4ba8SAndrew Turner sinh(x) = (exp(x) - exp(-x)) / 2.
45072a4ba8SAndrew Turner The maximum error is 2.26 ULP:
46*5a02ffc3SAndrew Turner _ZGVnN4v_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4
47*5a02ffc3SAndrew Turner want 0x1.e469e4p-4. */
V_NAME_F1(sinh)48*5a02ffc3SAndrew Turner float32x4_t VPCS_ATTR V_NAME_F1 (sinh) (float32x4_t x)
49072a4ba8SAndrew Turner {
50*5a02ffc3SAndrew Turner const struct data *d = ptr_barrier (&data);
51*5a02ffc3SAndrew Turner
52*5a02ffc3SAndrew Turner uint32x4_t ix = vreinterpretq_u32_f32 (x);
53*5a02ffc3SAndrew Turner float32x4_t ax = vabsq_f32 (x);
54*5a02ffc3SAndrew Turner uint32x4_t iax = vreinterpretq_u32_f32 (ax);
55*5a02ffc3SAndrew Turner uint32x4_t sign = veorq_u32 (ix, iax);
56*5a02ffc3SAndrew Turner float32x4_t halfsign = vreinterpretq_f32_u32 (vorrq_u32 (sign, d->halff));
57072a4ba8SAndrew Turner
58072a4ba8SAndrew Turner #if WANT_SIMD_EXCEPT
59*5a02ffc3SAndrew Turner uint32x4_t special = vcgeq_u32 (vsubq_u32 (iax, d->tiny_bound), d->thresh);
60*5a02ffc3SAndrew Turner ax = v_zerofy_f32 (ax, special);
61072a4ba8SAndrew Turner #else
62*5a02ffc3SAndrew Turner uint32x4_t special = vcgeq_u32 (iax, d->oflow_bound);
63072a4ba8SAndrew Turner #endif
64072a4ba8SAndrew Turner
65072a4ba8SAndrew Turner /* Up to the point that expm1f overflows, we can use it to calculate sinhf
66*5a02ffc3SAndrew Turner using a slight rearrangement of the definition of asinh. This allows us
67*5a02ffc3SAndrew Turner to retain acceptable accuracy for very small inputs. */
68*5a02ffc3SAndrew Turner float32x4_t t = expm1f_inline (ax, &d->expm1f_consts);
69*5a02ffc3SAndrew Turner t = vaddq_f32 (t, vdivq_f32 (t, vaddq_f32 (t, v_f32 (1.0))));
70*5a02ffc3SAndrew Turner
71*5a02ffc3SAndrew Turner /* Fall back to the scalar variant for any lanes that should trigger an
72*5a02ffc3SAndrew Turner exception. */
73*5a02ffc3SAndrew Turner if (unlikely (v_any_u32 (special)))
74*5a02ffc3SAndrew Turner return special_case (x, vmulq_f32 (t, halfsign), special);
75*5a02ffc3SAndrew Turner
76*5a02ffc3SAndrew Turner return vmulq_f32 (t, halfsign);
77072a4ba8SAndrew Turner }
78072a4ba8SAndrew Turner
79072a4ba8SAndrew Turner PL_SIG (V, F, 1, sinh, -10.0, 10.0)
80*5a02ffc3SAndrew Turner PL_TEST_ULP (V_NAME_F1 (sinh), 1.76)
81*5a02ffc3SAndrew Turner PL_TEST_EXPECT_FENV (V_NAME_F1 (sinh), WANT_SIMD_EXCEPT)
82*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0, 0x2fb504f4, 1000)
83*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x2fb504f4, 0x42b0c0a7, 100000)
84*5a02ffc3SAndrew Turner PL_TEST_SYM_INTERVAL (V_NAME_F1 (sinh), 0x42b0c0a7, inf, 1000)
85