1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the declaration of the MachineInstr class, which is the 10 // basic representation for all target dependent machine instructions used by 11 // the back end. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 16 #define LLVM_CODEGEN_MACHINEINSTR_H 17 18 #include "llvm/ADT/DenseMapInfo.h" 19 #include "llvm/ADT/PointerSumType.h" 20 #include "llvm/ADT/ilist.h" 21 #include "llvm/ADT/ilist_node.h" 22 #include "llvm/ADT/iterator_range.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineOperand.h" 25 #include "llvm/CodeGen/TargetOpcodes.h" 26 #include "llvm/IR/DebugLoc.h" 27 #include "llvm/IR/InlineAsm.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCSymbol.h" 30 #include "llvm/Support/ArrayRecycler.h" 31 #include "llvm/Support/TrailingObjects.h" 32 #include <algorithm> 33 #include <cassert> 34 #include <cstdint> 35 #include <utility> 36 37 namespace llvm { 38 39 class AAResults; 40 template <typename T> class ArrayRef; 41 class DIExpression; 42 class DILocalVariable; 43 class MachineBasicBlock; 44 class MachineFunction; 45 class MachineRegisterInfo; 46 class ModuleSlotTracker; 47 class raw_ostream; 48 template <typename T> class SmallVectorImpl; 49 class SmallBitVector; 50 class StringRef; 51 class TargetInstrInfo; 52 class TargetRegisterClass; 53 class TargetRegisterInfo; 54 55 //===----------------------------------------------------------------------===// 56 /// Representation of each machine instruction. 57 /// 58 /// This class isn't a POD type, but it must have a trivial destructor. When a 59 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated 60 /// without having their destructor called. 61 /// 62 class MachineInstr 63 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, 64 ilist_sentinel_tracking<true>> { 65 public: 66 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; 67 68 /// Flags to specify different kinds of comments to output in 69 /// assembly code. These flags carry semantic information not 70 /// otherwise easily derivable from the IR text. 71 /// 72 enum CommentFlag { 73 ReloadReuse = 0x1, // higher bits are reserved for target dep comments. 74 NoSchedComment = 0x2, 75 TAsmComments = 0x4 // Target Asm comments should start from this value. 76 }; 77 78 enum MIFlag { 79 NoFlags = 0, 80 FrameSetup = 1 << 0, // Instruction is used as a part of 81 // function frame setup code. 82 FrameDestroy = 1 << 1, // Instruction is used as a part of 83 // function frame destruction code. 84 BundledPred = 1 << 2, // Instruction has bundled predecessors. 85 BundledSucc = 1 << 3, // Instruction has bundled successors. 86 FmNoNans = 1 << 4, // Instruction does not support Fast 87 // math nan values. 88 FmNoInfs = 1 << 5, // Instruction does not support Fast 89 // math infinity values. 90 FmNsz = 1 << 6, // Instruction is not required to retain 91 // signed zero values. 92 FmArcp = 1 << 7, // Instruction supports Fast math 93 // reciprocal approximations. 94 FmContract = 1 << 8, // Instruction supports Fast math 95 // contraction operations like fma. 96 FmAfn = 1 << 9, // Instruction may map to Fast math 97 // instrinsic approximation. 98 FmReassoc = 1 << 10, // Instruction supports Fast math 99 // reassociation of operand order. 100 NoUWrap = 1 << 11, // Instruction supports binary operator 101 // no unsigned wrap. 102 NoSWrap = 1 << 12, // Instruction supports binary operator 103 // no signed wrap. 104 IsExact = 1 << 13, // Instruction supports division is 105 // known to be exact. 106 NoFPExcept = 1 << 14, // Instruction does not raise 107 // floatint-point exceptions. 108 NoMerge = 1 << 15, // Passes that drop source location info 109 // (e.g. branch folding) should skip 110 // this instruction. 111 }; 112 113 private: 114 const MCInstrDesc *MCID; // Instruction descriptor. 115 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. 116 117 // Operands are allocated by an ArrayRecycler. 118 MachineOperand *Operands = nullptr; // Pointer to the first operand. 119 unsigned NumOperands = 0; // Number of operands on instruction. 120 121 uint16_t Flags = 0; // Various bits of additional 122 // information about machine 123 // instruction. 124 125 uint8_t AsmPrinterFlags = 0; // Various bits of information used by 126 // the AsmPrinter to emit helpful 127 // comments. This is *not* semantic 128 // information. Do not use this for 129 // anything other than to convey comment 130 // information to AsmPrinter. 131 132 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags 133 // to properly pack. 134 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; 135 OperandCapacity CapOperands; // Capacity of the Operands array. 136 137 /// Internal implementation detail class that provides out-of-line storage for 138 /// extra info used by the machine instruction when this info cannot be stored 139 /// in-line within the instruction itself. 140 /// 141 /// This has to be defined eagerly due to the implementation constraints of 142 /// `PointerSumType` where it is used. 143 class ExtraInfo final 144 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> { 145 public: 146 static ExtraInfo *create(BumpPtrAllocator &Allocator, 147 ArrayRef<MachineMemOperand *> MMOs, 148 MCSymbol *PreInstrSymbol = nullptr, 149 MCSymbol *PostInstrSymbol = nullptr, 150 MDNode *HeapAllocMarker = nullptr) { 151 bool HasPreInstrSymbol = PreInstrSymbol != nullptr; 152 bool HasPostInstrSymbol = PostInstrSymbol != nullptr; 153 bool HasHeapAllocMarker = HeapAllocMarker != nullptr; 154 auto *Result = new (Allocator.Allocate( 155 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>( 156 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol, 157 HasHeapAllocMarker), 158 alignof(ExtraInfo))) 159 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, 160 HasHeapAllocMarker); 161 162 // Copy the actual data into the trailing objects. 163 std::copy(MMOs.begin(), MMOs.end(), 164 Result->getTrailingObjects<MachineMemOperand *>()); 165 166 if (HasPreInstrSymbol) 167 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; 168 if (HasPostInstrSymbol) 169 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = 170 PostInstrSymbol; 171 if (HasHeapAllocMarker) 172 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker; 173 174 return Result; 175 } 176 177 ArrayRef<MachineMemOperand *> getMMOs() const { 178 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); 179 } 180 181 MCSymbol *getPreInstrSymbol() const { 182 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; 183 } 184 185 MCSymbol *getPostInstrSymbol() const { 186 return HasPostInstrSymbol 187 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] 188 : nullptr; 189 } 190 191 MDNode *getHeapAllocMarker() const { 192 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr; 193 } 194 195 private: 196 friend TrailingObjects; 197 198 // Description of the extra info, used to interpret the actual optional 199 // data appended. 200 // 201 // Note that this is not terribly space optimized. This leaves a great deal 202 // of flexibility to fit more in here later. 203 const int NumMMOs; 204 const bool HasPreInstrSymbol; 205 const bool HasPostInstrSymbol; 206 const bool HasHeapAllocMarker; 207 208 // Implement the `TrailingObjects` internal API. 209 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { 210 return NumMMOs; 211 } 212 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const { 213 return HasPreInstrSymbol + HasPostInstrSymbol; 214 } 215 size_t numTrailingObjects(OverloadToken<MDNode *>) const { 216 return HasHeapAllocMarker; 217 } 218 219 // Just a boring constructor to allow us to initialize the sizes. Always use 220 // the `create` routine above. 221 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, 222 bool HasHeapAllocMarker) 223 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), 224 HasPostInstrSymbol(HasPostInstrSymbol), 225 HasHeapAllocMarker(HasHeapAllocMarker) {} 226 }; 227 228 /// Enumeration of the kinds of inline extra info available. It is important 229 /// that the `MachineMemOperand` inline kind has a tag value of zero to make 230 /// it accessible as an `ArrayRef`. 231 enum ExtraInfoInlineKinds { 232 EIIK_MMO = 0, 233 EIIK_PreInstrSymbol, 234 EIIK_PostInstrSymbol, 235 EIIK_OutOfLine 236 }; 237 238 // We store extra information about the instruction here. The common case is 239 // expected to be nothing or a single pointer (typically a MMO or a symbol). 240 // We work to optimize this common case by storing it inline here rather than 241 // requiring a separate allocation, but we fall back to an allocation when 242 // multiple pointers are needed. 243 PointerSumType<ExtraInfoInlineKinds, 244 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, 245 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, 246 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, 247 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> 248 Info; 249 250 DebugLoc debugLoc; // Source line information. 251 252 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values 253 /// defined by this instruction. 254 unsigned DebugInstrNum; 255 256 // Intrusive list support 257 friend struct ilist_traits<MachineInstr>; 258 friend struct ilist_callback_traits<MachineBasicBlock>; 259 void setParent(MachineBasicBlock *P) { Parent = P; } 260 261 /// This constructor creates a copy of the given 262 /// MachineInstr in the given MachineFunction. 263 MachineInstr(MachineFunction &, const MachineInstr &); 264 265 /// This constructor create a MachineInstr and add the implicit operands. 266 /// It reserves space for number of operands specified by 267 /// MCInstrDesc. An explicit DebugLoc is supplied. 268 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl, 269 bool NoImp = false); 270 271 // MachineInstrs are pool-allocated and owned by MachineFunction. 272 friend class MachineFunction; 273 274 void 275 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, 276 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const; 277 278 public: 279 MachineInstr(const MachineInstr &) = delete; 280 MachineInstr &operator=(const MachineInstr &) = delete; 281 // Use MachineFunction::DeleteMachineInstr() instead. 282 ~MachineInstr() = delete; 283 284 const MachineBasicBlock* getParent() const { return Parent; } 285 MachineBasicBlock* getParent() { return Parent; } 286 287 /// Move the instruction before \p MovePos. 288 void moveBefore(MachineInstr *MovePos); 289 290 /// Return the function that contains the basic block that this instruction 291 /// belongs to. 292 /// 293 /// Note: this is undefined behaviour if the instruction does not have a 294 /// parent. 295 const MachineFunction *getMF() const; 296 MachineFunction *getMF() { 297 return const_cast<MachineFunction *>( 298 static_cast<const MachineInstr *>(this)->getMF()); 299 } 300 301 /// Return the asm printer flags bitvector. 302 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } 303 304 /// Clear the AsmPrinter bitvector. 305 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } 306 307 /// Return whether an AsmPrinter flag is set. 308 bool getAsmPrinterFlag(CommentFlag Flag) const { 309 return AsmPrinterFlags & Flag; 310 } 311 312 /// Set a flag for the AsmPrinter. 313 void setAsmPrinterFlag(uint8_t Flag) { 314 AsmPrinterFlags |= Flag; 315 } 316 317 /// Clear specific AsmPrinter flags. 318 void clearAsmPrinterFlag(CommentFlag Flag) { 319 AsmPrinterFlags &= ~Flag; 320 } 321 322 /// Return the MI flags bitvector. 323 uint16_t getFlags() const { 324 return Flags; 325 } 326 327 /// Return whether an MI flag is set. 328 bool getFlag(MIFlag Flag) const { 329 return Flags & Flag; 330 } 331 332 /// Set a MI flag. 333 void setFlag(MIFlag Flag) { 334 Flags |= (uint16_t)Flag; 335 } 336 337 void setFlags(unsigned flags) { 338 // Filter out the automatically maintained flags. 339 unsigned Mask = BundledPred | BundledSucc; 340 Flags = (Flags & Mask) | (flags & ~Mask); 341 } 342 343 /// clearFlag - Clear a MI flag. 344 void clearFlag(MIFlag Flag) { 345 Flags &= ~((uint16_t)Flag); 346 } 347 348 /// Return true if MI is in a bundle (but not the first MI in a bundle). 349 /// 350 /// A bundle looks like this before it's finalized: 351 /// ---------------- 352 /// | MI | 353 /// ---------------- 354 /// | 355 /// ---------------- 356 /// | MI * | 357 /// ---------------- 358 /// | 359 /// ---------------- 360 /// | MI * | 361 /// ---------------- 362 /// In this case, the first MI starts a bundle but is not inside a bundle, the 363 /// next 2 MIs are considered "inside" the bundle. 364 /// 365 /// After a bundle is finalized, it looks like this: 366 /// ---------------- 367 /// | Bundle | 368 /// ---------------- 369 /// | 370 /// ---------------- 371 /// | MI * | 372 /// ---------------- 373 /// | 374 /// ---------------- 375 /// | MI * | 376 /// ---------------- 377 /// | 378 /// ---------------- 379 /// | MI * | 380 /// ---------------- 381 /// The first instruction has the special opcode "BUNDLE". It's not "inside" 382 /// a bundle, but the next three MIs are. 383 bool isInsideBundle() const { 384 return getFlag(BundledPred); 385 } 386 387 /// Return true if this instruction part of a bundle. This is true 388 /// if either itself or its following instruction is marked "InsideBundle". 389 bool isBundled() const { 390 return isBundledWithPred() || isBundledWithSucc(); 391 } 392 393 /// Return true if this instruction is part of a bundle, and it is not the 394 /// first instruction in the bundle. 395 bool isBundledWithPred() const { return getFlag(BundledPred); } 396 397 /// Return true if this instruction is part of a bundle, and it is not the 398 /// last instruction in the bundle. 399 bool isBundledWithSucc() const { return getFlag(BundledSucc); } 400 401 /// Bundle this instruction with its predecessor. This can be an unbundled 402 /// instruction, or it can be the first instruction in a bundle. 403 void bundleWithPred(); 404 405 /// Bundle this instruction with its successor. This can be an unbundled 406 /// instruction, or it can be the last instruction in a bundle. 407 void bundleWithSucc(); 408 409 /// Break bundle above this instruction. 410 void unbundleFromPred(); 411 412 /// Break bundle below this instruction. 413 void unbundleFromSucc(); 414 415 /// Returns the debug location id of this MachineInstr. 416 const DebugLoc &getDebugLoc() const { return debugLoc; } 417 418 /// Return the operand containing the offset to be used if this DBG_VALUE 419 /// instruction is indirect; will be an invalid register if this value is 420 /// not indirect, and an immediate with value 0 otherwise. 421 const MachineOperand &getDebugOffset() const { 422 assert(isDebugValue() && "not a DBG_VALUE"); 423 return getOperand(1); 424 } 425 MachineOperand &getDebugOffset() { 426 assert(isDebugValue() && "not a DBG_VALUE"); 427 return getOperand(1); 428 } 429 430 /// Return the operand for the debug variable referenced by 431 /// this DBG_VALUE instruction. 432 const MachineOperand &getDebugVariableOp() const; 433 MachineOperand &getDebugVariableOp(); 434 435 /// Return the debug variable referenced by 436 /// this DBG_VALUE instruction. 437 const DILocalVariable *getDebugVariable() const; 438 439 /// Return the operand for the complex address expression referenced by 440 /// this DBG_VALUE instruction. 441 MachineOperand &getDebugExpressionOp(); 442 443 /// Return the complex address expression referenced by 444 /// this DBG_VALUE instruction. 445 const DIExpression *getDebugExpression() const; 446 447 /// Return the debug label referenced by 448 /// this DBG_LABEL instruction. 449 const DILabel *getDebugLabel() const; 450 451 /// Fetch the instruction number of this MachineInstr. If it does not have 452 /// one already, a new and unique number will be assigned. 453 unsigned getDebugInstrNum(); 454 455 /// Examine the instruction number of this MachineInstr. May be zero if 456 /// it hasn't been assigned a number yet. 457 unsigned peekDebugInstrNum() const { return DebugInstrNum; } 458 459 /// Set instruction number of this MachineInstr. Avoid using unless you're 460 /// deserializing this information. 461 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; } 462 463 /// Emit an error referring to the source location of this instruction. 464 /// This should only be used for inline assembly that is somehow 465 /// impossible to compile. Other errors should have been handled much 466 /// earlier. 467 /// 468 /// If this method returns, the caller should try to recover from the error. 469 void emitError(StringRef Msg) const; 470 471 /// Returns the target instruction descriptor of this MachineInstr. 472 const MCInstrDesc &getDesc() const { return *MCID; } 473 474 /// Returns the opcode of this MachineInstr. 475 unsigned getOpcode() const { return MCID->Opcode; } 476 477 /// Retuns the total number of operands. 478 unsigned getNumOperands() const { return NumOperands; } 479 480 /// Returns the total number of operands which are debug locations. 481 unsigned getNumDebugOperands() const { 482 return std::distance(debug_operands().begin(), debug_operands().end()); 483 } 484 485 const MachineOperand& getOperand(unsigned i) const { 486 assert(i < getNumOperands() && "getOperand() out of range!"); 487 return Operands[i]; 488 } 489 MachineOperand& getOperand(unsigned i) { 490 assert(i < getNumOperands() && "getOperand() out of range!"); 491 return Operands[i]; 492 } 493 494 MachineOperand &getDebugOperand(unsigned Index) { 495 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!"); 496 return *(debug_operands().begin() + Index); 497 } 498 const MachineOperand &getDebugOperand(unsigned Index) const { 499 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!"); 500 return *(debug_operands().begin() + Index); 501 } 502 503 /// Returns a pointer to the operand corresponding to a debug use of Reg, or 504 /// nullptr if Reg is not used in any debug operand. 505 const MachineOperand *getDebugOperandForReg(Register Reg) const { 506 const MachineOperand *RegOp = 507 find_if(debug_operands(), [Reg](const MachineOperand &Op) { 508 return Op.isReg() && Op.getReg() == Reg; 509 }); 510 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp; 511 } 512 MachineOperand *getDebugOperandForReg(Register Reg) { 513 MachineOperand *RegOp = 514 find_if(debug_operands(), [Reg](const MachineOperand &Op) { 515 return Op.isReg() && Op.getReg() == Reg; 516 }); 517 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp; 518 } 519 520 unsigned getDebugOperandIndex(const MachineOperand *Op) const { 521 assert(Op >= adl_begin(debug_operands()) && 522 Op <= adl_end(debug_operands()) && "Expected a debug operand."); 523 return std::distance(adl_begin(debug_operands()), Op); 524 } 525 526 /// Returns the total number of definitions. 527 unsigned getNumDefs() const { 528 return getNumExplicitDefs() + MCID->getNumImplicitDefs(); 529 } 530 531 /// Returns true if the instruction has implicit definition. 532 bool hasImplicitDef() const { 533 for (unsigned I = getNumExplicitOperands(), E = getNumOperands(); 534 I != E; ++I) { 535 const MachineOperand &MO = getOperand(I); 536 if (MO.isDef() && MO.isImplicit()) 537 return true; 538 } 539 return false; 540 } 541 542 /// Returns the implicit operands number. 543 unsigned getNumImplicitOperands() const { 544 return getNumOperands() - getNumExplicitOperands(); 545 } 546 547 /// Return true if operand \p OpIdx is a subregister index. 548 bool isOperandSubregIdx(unsigned OpIdx) const { 549 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && 550 "Expected MO_Immediate operand type."); 551 if (isExtractSubreg() && OpIdx == 2) 552 return true; 553 if (isInsertSubreg() && OpIdx == 3) 554 return true; 555 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) 556 return true; 557 if (isSubregToReg() && OpIdx == 3) 558 return true; 559 return false; 560 } 561 562 /// Returns the number of non-implicit operands. 563 unsigned getNumExplicitOperands() const; 564 565 /// Returns the number of non-implicit definitions. 566 unsigned getNumExplicitDefs() const; 567 568 /// iterator/begin/end - Iterate over all operands of a machine instruction. 569 using mop_iterator = MachineOperand *; 570 using const_mop_iterator = const MachineOperand *; 571 572 mop_iterator operands_begin() { return Operands; } 573 mop_iterator operands_end() { return Operands + NumOperands; } 574 575 const_mop_iterator operands_begin() const { return Operands; } 576 const_mop_iterator operands_end() const { return Operands + NumOperands; } 577 578 iterator_range<mop_iterator> operands() { 579 return make_range(operands_begin(), operands_end()); 580 } 581 iterator_range<const_mop_iterator> operands() const { 582 return make_range(operands_begin(), operands_end()); 583 } 584 iterator_range<mop_iterator> explicit_operands() { 585 return make_range(operands_begin(), 586 operands_begin() + getNumExplicitOperands()); 587 } 588 iterator_range<const_mop_iterator> explicit_operands() const { 589 return make_range(operands_begin(), 590 operands_begin() + getNumExplicitOperands()); 591 } 592 iterator_range<mop_iterator> implicit_operands() { 593 return make_range(explicit_operands().end(), operands_end()); 594 } 595 iterator_range<const_mop_iterator> implicit_operands() const { 596 return make_range(explicit_operands().end(), operands_end()); 597 } 598 /// Returns a range over all operands that are used to determine the variable 599 /// location for this DBG_VALUE instruction. 600 iterator_range<mop_iterator> debug_operands() { 601 assert(isDebugValue() && "Must be a debug value instruction."); 602 return make_range(operands_begin(), operands_begin() + 1); 603 } 604 /// \copydoc debug_operands() 605 iterator_range<const_mop_iterator> debug_operands() const { 606 assert(isDebugValue() && "Must be a debug value instruction."); 607 return make_range(operands_begin(), operands_begin() + 1); 608 } 609 /// Returns a range over all explicit operands that are register definitions. 610 /// Implicit definition are not included! 611 iterator_range<mop_iterator> defs() { 612 return make_range(operands_begin(), 613 operands_begin() + getNumExplicitDefs()); 614 } 615 /// \copydoc defs() 616 iterator_range<const_mop_iterator> defs() const { 617 return make_range(operands_begin(), 618 operands_begin() + getNumExplicitDefs()); 619 } 620 /// Returns a range that includes all operands that are register uses. 621 /// This may include unrelated operands which are not register uses. 622 iterator_range<mop_iterator> uses() { 623 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 624 } 625 /// \copydoc uses() 626 iterator_range<const_mop_iterator> uses() const { 627 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 628 } 629 iterator_range<mop_iterator> explicit_uses() { 630 return make_range(operands_begin() + getNumExplicitDefs(), 631 operands_begin() + getNumExplicitOperands()); 632 } 633 iterator_range<const_mop_iterator> explicit_uses() const { 634 return make_range(operands_begin() + getNumExplicitDefs(), 635 operands_begin() + getNumExplicitOperands()); 636 } 637 638 /// Returns the number of the operand iterator \p I points to. 639 unsigned getOperandNo(const_mop_iterator I) const { 640 return I - operands_begin(); 641 } 642 643 /// Access to memory operands of the instruction. If there are none, that does 644 /// not imply anything about whether the function accesses memory. Instead, 645 /// the caller must behave conservatively. 646 ArrayRef<MachineMemOperand *> memoperands() const { 647 if (!Info) 648 return {}; 649 650 if (Info.is<EIIK_MMO>()) 651 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1); 652 653 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 654 return EI->getMMOs(); 655 656 return {}; 657 } 658 659 /// Access to memory operands of the instruction. 660 /// 661 /// If `memoperands_begin() == memoperands_end()`, that does not imply 662 /// anything about whether the function accesses memory. Instead, the caller 663 /// must behave conservatively. 664 mmo_iterator memoperands_begin() const { return memoperands().begin(); } 665 666 /// Access to memory operands of the instruction. 667 /// 668 /// If `memoperands_begin() == memoperands_end()`, that does not imply 669 /// anything about whether the function accesses memory. Instead, the caller 670 /// must behave conservatively. 671 mmo_iterator memoperands_end() const { return memoperands().end(); } 672 673 /// Return true if we don't have any memory operands which described the 674 /// memory access done by this instruction. If this is true, calling code 675 /// must be conservative. 676 bool memoperands_empty() const { return memoperands().empty(); } 677 678 /// Return true if this instruction has exactly one MachineMemOperand. 679 bool hasOneMemOperand() const { return memoperands().size() == 1; } 680 681 /// Return the number of memory operands. 682 unsigned getNumMemOperands() const { return memoperands().size(); } 683 684 /// Helper to extract a pre-instruction symbol if one has been added. 685 MCSymbol *getPreInstrSymbol() const { 686 if (!Info) 687 return nullptr; 688 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) 689 return S; 690 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 691 return EI->getPreInstrSymbol(); 692 693 return nullptr; 694 } 695 696 /// Helper to extract a post-instruction symbol if one has been added. 697 MCSymbol *getPostInstrSymbol() const { 698 if (!Info) 699 return nullptr; 700 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) 701 return S; 702 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 703 return EI->getPostInstrSymbol(); 704 705 return nullptr; 706 } 707 708 /// Helper to extract a heap alloc marker if one has been added. 709 MDNode *getHeapAllocMarker() const { 710 if (!Info) 711 return nullptr; 712 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 713 return EI->getHeapAllocMarker(); 714 715 return nullptr; 716 } 717 718 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 719 /// queries but they are bundle aware. 720 721 enum QueryType { 722 IgnoreBundle, // Ignore bundles 723 AnyInBundle, // Return true if any instruction in bundle has property 724 AllInBundle // Return true if all instructions in bundle have property 725 }; 726 727 /// Return true if the instruction (or in the case of a bundle, 728 /// the instructions inside the bundle) has the specified property. 729 /// The first argument is the property being queried. 730 /// The second argument indicates whether the query should look inside 731 /// instruction bundles. 732 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { 733 assert(MCFlag < 64 && 734 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."); 735 // Inline the fast path for unbundled or bundle-internal instructions. 736 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) 737 return getDesc().getFlags() & (1ULL << MCFlag); 738 739 // If this is the first instruction in a bundle, take the slow path. 740 return hasPropertyInBundle(1ULL << MCFlag, Type); 741 } 742 743 /// Return true if this is an instruction that should go through the usual 744 /// legalization steps. 745 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const { 746 return hasProperty(MCID::PreISelOpcode, Type); 747 } 748 749 /// Return true if this instruction can have a variable number of operands. 750 /// In this case, the variable operands will be after the normal 751 /// operands but before the implicit definitions and uses (if any are 752 /// present). 753 bool isVariadic(QueryType Type = IgnoreBundle) const { 754 return hasProperty(MCID::Variadic, Type); 755 } 756 757 /// Set if this instruction has an optional definition, e.g. 758 /// ARM instructions which can set condition code if 's' bit is set. 759 bool hasOptionalDef(QueryType Type = IgnoreBundle) const { 760 return hasProperty(MCID::HasOptionalDef, Type); 761 } 762 763 /// Return true if this is a pseudo instruction that doesn't 764 /// correspond to a real machine instruction. 765 bool isPseudo(QueryType Type = IgnoreBundle) const { 766 return hasProperty(MCID::Pseudo, Type); 767 } 768 769 bool isReturn(QueryType Type = AnyInBundle) const { 770 return hasProperty(MCID::Return, Type); 771 } 772 773 /// Return true if this is an instruction that marks the end of an EH scope, 774 /// i.e., a catchpad or a cleanuppad instruction. 775 bool isEHScopeReturn(QueryType Type = AnyInBundle) const { 776 return hasProperty(MCID::EHScopeReturn, Type); 777 } 778 779 bool isCall(QueryType Type = AnyInBundle) const { 780 return hasProperty(MCID::Call, Type); 781 } 782 783 /// Return true if this is a call instruction that may have an associated 784 /// call site entry in the debug info. 785 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const; 786 /// Return true if copying, moving, or erasing this instruction requires 787 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo, 788 /// \ref eraseCallSiteInfo). 789 bool shouldUpdateCallSiteInfo() const; 790 791 /// Returns true if the specified instruction stops control flow 792 /// from executing the instruction immediately following it. Examples include 793 /// unconditional branches and return instructions. 794 bool isBarrier(QueryType Type = AnyInBundle) const { 795 return hasProperty(MCID::Barrier, Type); 796 } 797 798 /// Returns true if this instruction part of the terminator for a basic block. 799 /// Typically this is things like return and branch instructions. 800 /// 801 /// Various passes use this to insert code into the bottom of a basic block, 802 /// but before control flow occurs. 803 bool isTerminator(QueryType Type = AnyInBundle) const { 804 return hasProperty(MCID::Terminator, Type); 805 } 806 807 /// Returns true if this is a conditional, unconditional, or indirect branch. 808 /// Predicates below can be used to discriminate between 809 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to 810 /// get more information. 811 bool isBranch(QueryType Type = AnyInBundle) const { 812 return hasProperty(MCID::Branch, Type); 813 } 814 815 /// Return true if this is an indirect branch, such as a 816 /// branch through a register. 817 bool isIndirectBranch(QueryType Type = AnyInBundle) const { 818 return hasProperty(MCID::IndirectBranch, Type); 819 } 820 821 /// Return true if this is a branch which may fall 822 /// through to the next instruction or may transfer control flow to some other 823 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more 824 /// information about this branch. 825 bool isConditionalBranch(QueryType Type = AnyInBundle) const { 826 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type); 827 } 828 829 /// Return true if this is a branch which always 830 /// transfers control flow to some other block. The 831 /// TargetInstrInfo::analyzeBranch method can be used to get more information 832 /// about this branch. 833 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { 834 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type); 835 } 836 837 /// Return true if this instruction has a predicate operand that 838 /// controls execution. It may be set to 'always', or may be set to other 839 /// values. There are various methods in TargetInstrInfo that can be used to 840 /// control and modify the predicate in this instruction. 841 bool isPredicable(QueryType Type = AllInBundle) const { 842 // If it's a bundle than all bundled instructions must be predicable for this 843 // to return true. 844 return hasProperty(MCID::Predicable, Type); 845 } 846 847 /// Return true if this instruction is a comparison. 848 bool isCompare(QueryType Type = IgnoreBundle) const { 849 return hasProperty(MCID::Compare, Type); 850 } 851 852 /// Return true if this instruction is a move immediate 853 /// (including conditional moves) instruction. 854 bool isMoveImmediate(QueryType Type = IgnoreBundle) const { 855 return hasProperty(MCID::MoveImm, Type); 856 } 857 858 /// Return true if this instruction is a register move. 859 /// (including moving values from subreg to reg) 860 bool isMoveReg(QueryType Type = IgnoreBundle) const { 861 return hasProperty(MCID::MoveReg, Type); 862 } 863 864 /// Return true if this instruction is a bitcast instruction. 865 bool isBitcast(QueryType Type = IgnoreBundle) const { 866 return hasProperty(MCID::Bitcast, Type); 867 } 868 869 /// Return true if this instruction is a select instruction. 870 bool isSelect(QueryType Type = IgnoreBundle) const { 871 return hasProperty(MCID::Select, Type); 872 } 873 874 /// Return true if this instruction cannot be safely duplicated. 875 /// For example, if the instruction has a unique labels attached 876 /// to it, duplicating it would cause multiple definition errors. 877 bool isNotDuplicable(QueryType Type = AnyInBundle) const { 878 return hasProperty(MCID::NotDuplicable, Type); 879 } 880 881 /// Return true if this instruction is convergent. 882 /// Convergent instructions can not be made control-dependent on any 883 /// additional values. 884 bool isConvergent(QueryType Type = AnyInBundle) const { 885 if (isInlineAsm()) { 886 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 887 if (ExtraInfo & InlineAsm::Extra_IsConvergent) 888 return true; 889 } 890 return hasProperty(MCID::Convergent, Type); 891 } 892 893 /// Returns true if the specified instruction has a delay slot 894 /// which must be filled by the code generator. 895 bool hasDelaySlot(QueryType Type = AnyInBundle) const { 896 return hasProperty(MCID::DelaySlot, Type); 897 } 898 899 /// Return true for instructions that can be folded as 900 /// memory operands in other instructions. The most common use for this 901 /// is instructions that are simple loads from memory that don't modify 902 /// the loaded value in any way, but it can also be used for instructions 903 /// that can be expressed as constant-pool loads, such as V_SETALLONES 904 /// on x86, to allow them to be folded when it is beneficial. 905 /// This should only be set on instructions that return a value in their 906 /// only virtual register definition. 907 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { 908 return hasProperty(MCID::FoldableAsLoad, Type); 909 } 910 911 /// Return true if this instruction behaves 912 /// the same way as the generic REG_SEQUENCE instructions. 913 /// E.g., on ARM, 914 /// dX VMOVDRR rY, rZ 915 /// is equivalent to 916 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 917 /// 918 /// Note that for the optimizers to be able to take advantage of 919 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 920 /// override accordingly. 921 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { 922 return hasProperty(MCID::RegSequence, Type); 923 } 924 925 /// Return true if this instruction behaves 926 /// the same way as the generic EXTRACT_SUBREG instructions. 927 /// E.g., on ARM, 928 /// rX, rY VMOVRRD dZ 929 /// is equivalent to two EXTRACT_SUBREG: 930 /// rX = EXTRACT_SUBREG dZ, ssub_0 931 /// rY = EXTRACT_SUBREG dZ, ssub_1 932 /// 933 /// Note that for the optimizers to be able to take advantage of 934 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 935 /// override accordingly. 936 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { 937 return hasProperty(MCID::ExtractSubreg, Type); 938 } 939 940 /// Return true if this instruction behaves 941 /// the same way as the generic INSERT_SUBREG instructions. 942 /// E.g., on ARM, 943 /// dX = VSETLNi32 dY, rZ, Imm 944 /// is equivalent to a INSERT_SUBREG: 945 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 946 /// 947 /// Note that for the optimizers to be able to take advantage of 948 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 949 /// override accordingly. 950 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { 951 return hasProperty(MCID::InsertSubreg, Type); 952 } 953 954 //===--------------------------------------------------------------------===// 955 // Side Effect Analysis 956 //===--------------------------------------------------------------------===// 957 958 /// Return true if this instruction could possibly read memory. 959 /// Instructions with this flag set are not necessarily simple load 960 /// instructions, they may load a value and modify it, for example. 961 bool mayLoad(QueryType Type = AnyInBundle) const { 962 if (isInlineAsm()) { 963 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 964 if (ExtraInfo & InlineAsm::Extra_MayLoad) 965 return true; 966 } 967 return hasProperty(MCID::MayLoad, Type); 968 } 969 970 /// Return true if this instruction could possibly modify memory. 971 /// Instructions with this flag set are not necessarily simple store 972 /// instructions, they may store a modified value based on their operands, or 973 /// may not actually modify anything, for example. 974 bool mayStore(QueryType Type = AnyInBundle) const { 975 if (isInlineAsm()) { 976 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 977 if (ExtraInfo & InlineAsm::Extra_MayStore) 978 return true; 979 } 980 return hasProperty(MCID::MayStore, Type); 981 } 982 983 /// Return true if this instruction could possibly read or modify memory. 984 bool mayLoadOrStore(QueryType Type = AnyInBundle) const { 985 return mayLoad(Type) || mayStore(Type); 986 } 987 988 /// Return true if this instruction could possibly raise a floating-point 989 /// exception. This is the case if the instruction is a floating-point 990 /// instruction that can in principle raise an exception, as indicated 991 /// by the MCID::MayRaiseFPException property, *and* at the same time, 992 /// the instruction is used in a context where we expect floating-point 993 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag. 994 bool mayRaiseFPException() const { 995 return hasProperty(MCID::MayRaiseFPException) && 996 !getFlag(MachineInstr::MIFlag::NoFPExcept); 997 } 998 999 //===--------------------------------------------------------------------===// 1000 // Flags that indicate whether an instruction can be modified by a method. 1001 //===--------------------------------------------------------------------===// 1002 1003 /// Return true if this may be a 2- or 3-address 1004 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 1005 /// result if Y and Z are exchanged. If this flag is set, then the 1006 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 1007 /// instruction. 1008 /// 1009 /// Note that this flag may be set on instructions that are only commutable 1010 /// sometimes. In these cases, the call to commuteInstruction will fail. 1011 /// Also note that some instructions require non-trivial modification to 1012 /// commute them. 1013 bool isCommutable(QueryType Type = IgnoreBundle) const { 1014 return hasProperty(MCID::Commutable, Type); 1015 } 1016 1017 /// Return true if this is a 2-address instruction 1018 /// which can be changed into a 3-address instruction if needed. Doing this 1019 /// transformation can be profitable in the register allocator, because it 1020 /// means that the instruction can use a 2-address form if possible, but 1021 /// degrade into a less efficient form if the source and dest register cannot 1022 /// be assigned to the same register. For example, this allows the x86 1023 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 1024 /// is the same speed as the shift but has bigger code size. 1025 /// 1026 /// If this returns true, then the target must implement the 1027 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 1028 /// is allowed to fail if the transformation isn't valid for this specific 1029 /// instruction (e.g. shl reg, 4 on x86). 1030 /// 1031 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { 1032 return hasProperty(MCID::ConvertibleTo3Addr, Type); 1033 } 1034 1035 /// Return true if this instruction requires 1036 /// custom insertion support when the DAG scheduler is inserting it into a 1037 /// machine basic block. If this is true for the instruction, it basically 1038 /// means that it is a pseudo instruction used at SelectionDAG time that is 1039 /// expanded out into magic code by the target when MachineInstrs are formed. 1040 /// 1041 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 1042 /// is used to insert this into the MachineBasicBlock. 1043 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { 1044 return hasProperty(MCID::UsesCustomInserter, Type); 1045 } 1046 1047 /// Return true if this instruction requires *adjustment* 1048 /// after instruction selection by calling a target hook. For example, this 1049 /// can be used to fill in ARM 's' optional operand depending on whether 1050 /// the conditional flag register is used. 1051 bool hasPostISelHook(QueryType Type = IgnoreBundle) const { 1052 return hasProperty(MCID::HasPostISelHook, Type); 1053 } 1054 1055 /// Returns true if this instruction is a candidate for remat. 1056 /// This flag is deprecated, please don't use it anymore. If this 1057 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 1058 /// verify the instruction is really rematable. 1059 bool isRematerializable(QueryType Type = AllInBundle) const { 1060 // It's only possible to re-mat a bundle if all bundled instructions are 1061 // re-materializable. 1062 return hasProperty(MCID::Rematerializable, Type); 1063 } 1064 1065 /// Returns true if this instruction has the same cost (or less) than a move 1066 /// instruction. This is useful during certain types of optimizations 1067 /// (e.g., remat during two-address conversion or machine licm) 1068 /// where we would like to remat or hoist the instruction, but not if it costs 1069 /// more than moving the instruction into the appropriate register. Note, we 1070 /// are not marking copies from and to the same register class with this flag. 1071 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { 1072 // Only returns true for a bundle if all bundled instructions are cheap. 1073 return hasProperty(MCID::CheapAsAMove, Type); 1074 } 1075 1076 /// Returns true if this instruction source operands 1077 /// have special register allocation requirements that are not captured by the 1078 /// operand register classes. e.g. ARM::STRD's two source registers must be an 1079 /// even / odd pair, ARM::STM registers have to be in ascending order. 1080 /// Post-register allocation passes should not attempt to change allocations 1081 /// for sources of instructions with this flag. 1082 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { 1083 return hasProperty(MCID::ExtraSrcRegAllocReq, Type); 1084 } 1085 1086 /// Returns true if this instruction def operands 1087 /// have special register allocation requirements that are not captured by the 1088 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 1089 /// even / odd pair, ARM::LDM registers have to be in ascending order. 1090 /// Post-register allocation passes should not attempt to change allocations 1091 /// for definitions of instructions with this flag. 1092 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { 1093 return hasProperty(MCID::ExtraDefRegAllocReq, Type); 1094 } 1095 1096 enum MICheckType { 1097 CheckDefs, // Check all operands for equality 1098 CheckKillDead, // Check all operands including kill / dead markers 1099 IgnoreDefs, // Ignore all definitions 1100 IgnoreVRegDefs // Ignore virtual register definitions 1101 }; 1102 1103 /// Return true if this instruction is identical to \p Other. 1104 /// Two instructions are identical if they have the same opcode and all their 1105 /// operands are identical (with respect to MachineOperand::isIdenticalTo()). 1106 /// Note that this means liveness related flags (dead, undef, kill) do not 1107 /// affect the notion of identical. 1108 bool isIdenticalTo(const MachineInstr &Other, 1109 MICheckType Check = CheckDefs) const; 1110 1111 /// Unlink 'this' from the containing basic block, and return it without 1112 /// deleting it. 1113 /// 1114 /// This function can not be used on bundled instructions, use 1115 /// removeFromBundle() to remove individual instructions from a bundle. 1116 MachineInstr *removeFromParent(); 1117 1118 /// Unlink this instruction from its basic block and return it without 1119 /// deleting it. 1120 /// 1121 /// If the instruction is part of a bundle, the other instructions in the 1122 /// bundle remain bundled. 1123 MachineInstr *removeFromBundle(); 1124 1125 /// Unlink 'this' from the containing basic block and delete it. 1126 /// 1127 /// If this instruction is the header of a bundle, the whole bundle is erased. 1128 /// This function can not be used for instructions inside a bundle, use 1129 /// eraseFromBundle() to erase individual bundled instructions. 1130 void eraseFromParent(); 1131 1132 /// Unlink 'this' from the containing basic block and delete it. 1133 /// 1134 /// For all definitions mark their uses in DBG_VALUE nodes 1135 /// as undefined. Otherwise like eraseFromParent(). 1136 void eraseFromParentAndMarkDBGValuesForRemoval(); 1137 1138 /// Unlink 'this' form its basic block and delete it. 1139 /// 1140 /// If the instruction is part of a bundle, the other instructions in the 1141 /// bundle remain bundled. 1142 void eraseFromBundle(); 1143 1144 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 1145 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 1146 bool isAnnotationLabel() const { 1147 return getOpcode() == TargetOpcode::ANNOTATION_LABEL; 1148 } 1149 1150 /// Returns true if the MachineInstr represents a label. 1151 bool isLabel() const { 1152 return isEHLabel() || isGCLabel() || isAnnotationLabel(); 1153 } 1154 1155 bool isCFIInstruction() const { 1156 return getOpcode() == TargetOpcode::CFI_INSTRUCTION; 1157 } 1158 1159 bool isPseudoProbe() const { 1160 return getOpcode() == TargetOpcode::PSEUDO_PROBE; 1161 } 1162 1163 // True if the instruction represents a position in the function. 1164 bool isPosition() const { return isLabel() || isCFIInstruction(); } 1165 1166 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 1167 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 1168 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; } 1169 bool isDebugInstr() const { 1170 return isDebugValue() || isDebugLabel() || isDebugRef(); 1171 } 1172 bool isDebugOrPseudoInstr() const { 1173 return isDebugInstr() || isPseudoProbe(); 1174 } 1175 1176 bool isDebugOffsetImm() const { return getDebugOffset().isImm(); } 1177 1178 /// A DBG_VALUE is indirect iff the location operand is a register and 1179 /// the offset operand is an immediate. 1180 bool isIndirectDebugValue() const { 1181 return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm(); 1182 } 1183 1184 /// A DBG_VALUE is an entry value iff its debug expression contains the 1185 /// DW_OP_LLVM_entry_value operation. 1186 bool isDebugEntryValue() const; 1187 1188 /// Return true if the instruction is a debug value which describes a part of 1189 /// a variable as unavailable. 1190 bool isUndefDebugValue() const { 1191 return isDebugValue() && getDebugOperand(0).isReg() && 1192 !getDebugOperand(0).getReg().isValid(); 1193 } 1194 1195 bool isPHI() const { 1196 return getOpcode() == TargetOpcode::PHI || 1197 getOpcode() == TargetOpcode::G_PHI; 1198 } 1199 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 1200 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 1201 bool isInlineAsm() const { 1202 return getOpcode() == TargetOpcode::INLINEASM || 1203 getOpcode() == TargetOpcode::INLINEASM_BR; 1204 } 1205 1206 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86 1207 /// specific, be attached to a generic MachineInstr. 1208 bool isMSInlineAsm() const { 1209 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel; 1210 } 1211 1212 bool isStackAligningInlineAsm() const; 1213 InlineAsm::AsmDialect getInlineAsmDialect() const; 1214 1215 bool isInsertSubreg() const { 1216 return getOpcode() == TargetOpcode::INSERT_SUBREG; 1217 } 1218 1219 bool isSubregToReg() const { 1220 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 1221 } 1222 1223 bool isRegSequence() const { 1224 return getOpcode() == TargetOpcode::REG_SEQUENCE; 1225 } 1226 1227 bool isBundle() const { 1228 return getOpcode() == TargetOpcode::BUNDLE; 1229 } 1230 1231 bool isCopy() const { 1232 return getOpcode() == TargetOpcode::COPY; 1233 } 1234 1235 bool isFullCopy() const { 1236 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 1237 } 1238 1239 bool isExtractSubreg() const { 1240 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 1241 } 1242 1243 /// Return true if the instruction behaves like a copy. 1244 /// This does not include native copy instructions. 1245 bool isCopyLike() const { 1246 return isCopy() || isSubregToReg(); 1247 } 1248 1249 /// Return true is the instruction is an identity copy. 1250 bool isIdentityCopy() const { 1251 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && 1252 getOperand(0).getSubReg() == getOperand(1).getSubReg(); 1253 } 1254 1255 /// Return true if this instruction doesn't produce any output in the form of 1256 /// executable instructions. 1257 bool isMetaInstruction() const { 1258 switch (getOpcode()) { 1259 default: 1260 return false; 1261 case TargetOpcode::IMPLICIT_DEF: 1262 case TargetOpcode::KILL: 1263 case TargetOpcode::CFI_INSTRUCTION: 1264 case TargetOpcode::EH_LABEL: 1265 case TargetOpcode::GC_LABEL: 1266 case TargetOpcode::DBG_VALUE: 1267 case TargetOpcode::DBG_INSTR_REF: 1268 case TargetOpcode::DBG_LABEL: 1269 case TargetOpcode::LIFETIME_START: 1270 case TargetOpcode::LIFETIME_END: 1271 case TargetOpcode::PSEUDO_PROBE: 1272 return true; 1273 } 1274 } 1275 1276 /// Return true if this is a transient instruction that is either very likely 1277 /// to be eliminated during register allocation (such as copy-like 1278 /// instructions), or if this instruction doesn't have an execution-time cost. 1279 bool isTransient() const { 1280 switch (getOpcode()) { 1281 default: 1282 return isMetaInstruction(); 1283 // Copy-like instructions are usually eliminated during register allocation. 1284 case TargetOpcode::PHI: 1285 case TargetOpcode::G_PHI: 1286 case TargetOpcode::COPY: 1287 case TargetOpcode::INSERT_SUBREG: 1288 case TargetOpcode::SUBREG_TO_REG: 1289 case TargetOpcode::REG_SEQUENCE: 1290 return true; 1291 } 1292 } 1293 1294 /// Return the number of instructions inside the MI bundle, excluding the 1295 /// bundle header. 1296 /// 1297 /// This is the number of instructions that MachineBasicBlock::iterator 1298 /// skips, 0 for unbundled instructions. 1299 unsigned getBundleSize() const; 1300 1301 /// Return true if the MachineInstr reads the specified register. 1302 /// If TargetRegisterInfo is passed, then it also checks if there 1303 /// is a read of a super-register. 1304 /// This does not count partial redefines of virtual registers as reads: 1305 /// %reg1024:6 = OP. 1306 bool readsRegister(Register Reg, 1307 const TargetRegisterInfo *TRI = nullptr) const { 1308 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 1309 } 1310 1311 /// Return true if the MachineInstr reads the specified virtual register. 1312 /// Take into account that a partial define is a 1313 /// read-modify-write operation. 1314 bool readsVirtualRegister(Register Reg) const { 1315 return readsWritesVirtualRegister(Reg).first; 1316 } 1317 1318 /// Return a pair of bools (reads, writes) indicating if this instruction 1319 /// reads or writes Reg. This also considers partial defines. 1320 /// If Ops is not null, all operand indices for Reg are added. 1321 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg, 1322 SmallVectorImpl<unsigned> *Ops = nullptr) const; 1323 1324 /// Return true if the MachineInstr kills the specified register. 1325 /// If TargetRegisterInfo is passed, then it also checks if there is 1326 /// a kill of a super-register. 1327 bool killsRegister(Register Reg, 1328 const TargetRegisterInfo *TRI = nullptr) const { 1329 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 1330 } 1331 1332 /// Return true if the MachineInstr fully defines the specified register. 1333 /// If TargetRegisterInfo is passed, then it also checks 1334 /// if there is a def of a super-register. 1335 /// NOTE: It's ignoring subreg indices on virtual registers. 1336 bool definesRegister(Register Reg, 1337 const TargetRegisterInfo *TRI = nullptr) const { 1338 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 1339 } 1340 1341 /// Return true if the MachineInstr modifies (fully define or partially 1342 /// define) the specified register. 1343 /// NOTE: It's ignoring subreg indices on virtual registers. 1344 bool modifiesRegister(Register Reg, 1345 const TargetRegisterInfo *TRI = nullptr) const { 1346 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 1347 } 1348 1349 /// Returns true if the register is dead in this machine instruction. 1350 /// If TargetRegisterInfo is passed, then it also checks 1351 /// if there is a dead def of a super-register. 1352 bool registerDefIsDead(Register Reg, 1353 const TargetRegisterInfo *TRI = nullptr) const { 1354 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 1355 } 1356 1357 /// Returns true if the MachineInstr has an implicit-use operand of exactly 1358 /// the given register (not considering sub/super-registers). 1359 bool hasRegisterImplicitUseOperand(Register Reg) const; 1360 1361 /// Returns the operand index that is a use of the specific register or -1 1362 /// if it is not found. It further tightens the search criteria to a use 1363 /// that kills the register if isKill is true. 1364 int findRegisterUseOperandIdx(Register Reg, bool isKill = false, 1365 const TargetRegisterInfo *TRI = nullptr) const; 1366 1367 /// Wrapper for findRegisterUseOperandIdx, it returns 1368 /// a pointer to the MachineOperand rather than an index. 1369 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, 1370 const TargetRegisterInfo *TRI = nullptr) { 1371 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 1372 return (Idx == -1) ? nullptr : &getOperand(Idx); 1373 } 1374 1375 const MachineOperand *findRegisterUseOperand( 1376 Register Reg, bool isKill = false, 1377 const TargetRegisterInfo *TRI = nullptr) const { 1378 return const_cast<MachineInstr *>(this)-> 1379 findRegisterUseOperand(Reg, isKill, TRI); 1380 } 1381 1382 /// Returns the operand index that is a def of the specified register or 1383 /// -1 if it is not found. If isDead is true, defs that are not dead are 1384 /// skipped. If Overlap is true, then it also looks for defs that merely 1385 /// overlap the specified register. If TargetRegisterInfo is non-null, 1386 /// then it also checks if there is a def of a super-register. 1387 /// This may also return a register mask operand when Overlap is true. 1388 int findRegisterDefOperandIdx(Register Reg, 1389 bool isDead = false, bool Overlap = false, 1390 const TargetRegisterInfo *TRI = nullptr) const; 1391 1392 /// Wrapper for findRegisterDefOperandIdx, it returns 1393 /// a pointer to the MachineOperand rather than an index. 1394 MachineOperand * 1395 findRegisterDefOperand(Register Reg, bool isDead = false, 1396 bool Overlap = false, 1397 const TargetRegisterInfo *TRI = nullptr) { 1398 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); 1399 return (Idx == -1) ? nullptr : &getOperand(Idx); 1400 } 1401 1402 const MachineOperand * 1403 findRegisterDefOperand(Register Reg, bool isDead = false, 1404 bool Overlap = false, 1405 const TargetRegisterInfo *TRI = nullptr) const { 1406 return const_cast<MachineInstr *>(this)->findRegisterDefOperand( 1407 Reg, isDead, Overlap, TRI); 1408 } 1409 1410 /// Find the index of the first operand in the 1411 /// operand list that is used to represent the predicate. It returns -1 if 1412 /// none is found. 1413 int findFirstPredOperandIdx() const; 1414 1415 /// Find the index of the flag word operand that 1416 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 1417 /// getOperand(OpIdx) does not belong to an inline asm operand group. 1418 /// 1419 /// If GroupNo is not NULL, it will receive the number of the operand group 1420 /// containing OpIdx. 1421 /// 1422 /// The flag operand is an immediate that can be decoded with methods like 1423 /// InlineAsm::hasRegClassConstraint(). 1424 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; 1425 1426 /// Compute the static register class constraint for operand OpIdx. 1427 /// For normal instructions, this is derived from the MCInstrDesc. 1428 /// For inline assembly it is derived from the flag words. 1429 /// 1430 /// Returns NULL if the static register class constraint cannot be 1431 /// determined. 1432 const TargetRegisterClass* 1433 getRegClassConstraint(unsigned OpIdx, 1434 const TargetInstrInfo *TII, 1435 const TargetRegisterInfo *TRI) const; 1436 1437 /// Applies the constraints (def/use) implied by this MI on \p Reg to 1438 /// the given \p CurRC. 1439 /// If \p ExploreBundle is set and MI is part of a bundle, all the 1440 /// instructions inside the bundle will be taken into account. In other words, 1441 /// this method accumulates all the constraints of the operand of this MI and 1442 /// the related bundle if MI is a bundle or inside a bundle. 1443 /// 1444 /// Returns the register class that satisfies both \p CurRC and the 1445 /// constraints set by MI. Returns NULL if such a register class does not 1446 /// exist. 1447 /// 1448 /// \pre CurRC must not be NULL. 1449 const TargetRegisterClass *getRegClassConstraintEffectForVReg( 1450 Register Reg, const TargetRegisterClass *CurRC, 1451 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, 1452 bool ExploreBundle = false) const; 1453 1454 /// Applies the constraints (def/use) implied by the \p OpIdx operand 1455 /// to the given \p CurRC. 1456 /// 1457 /// Returns the register class that satisfies both \p CurRC and the 1458 /// constraints set by \p OpIdx MI. Returns NULL if such a register class 1459 /// does not exist. 1460 /// 1461 /// \pre CurRC must not be NULL. 1462 /// \pre The operand at \p OpIdx must be a register. 1463 const TargetRegisterClass * 1464 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, 1465 const TargetInstrInfo *TII, 1466 const TargetRegisterInfo *TRI) const; 1467 1468 /// Add a tie between the register operands at DefIdx and UseIdx. 1469 /// The tie will cause the register allocator to ensure that the two 1470 /// operands are assigned the same physical register. 1471 /// 1472 /// Tied operands are managed automatically for explicit operands in the 1473 /// MCInstrDesc. This method is for exceptional cases like inline asm. 1474 void tieOperands(unsigned DefIdx, unsigned UseIdx); 1475 1476 /// Given the index of a tied register operand, find the 1477 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the 1478 /// index of the tied operand which must exist. 1479 unsigned findTiedOperandIdx(unsigned OpIdx) const; 1480 1481 /// Given the index of a register def operand, 1482 /// check if the register def is tied to a source operand, due to either 1483 /// two-address elimination or inline assembly constraints. Returns the 1484 /// first tied use operand index by reference if UseOpIdx is not null. 1485 bool isRegTiedToUseOperand(unsigned DefOpIdx, 1486 unsigned *UseOpIdx = nullptr) const { 1487 const MachineOperand &MO = getOperand(DefOpIdx); 1488 if (!MO.isReg() || !MO.isDef() || !MO.isTied()) 1489 return false; 1490 if (UseOpIdx) 1491 *UseOpIdx = findTiedOperandIdx(DefOpIdx); 1492 return true; 1493 } 1494 1495 /// Return true if the use operand of the specified index is tied to a def 1496 /// operand. It also returns the def operand index by reference if DefOpIdx 1497 /// is not null. 1498 bool isRegTiedToDefOperand(unsigned UseOpIdx, 1499 unsigned *DefOpIdx = nullptr) const { 1500 const MachineOperand &MO = getOperand(UseOpIdx); 1501 if (!MO.isReg() || !MO.isUse() || !MO.isTied()) 1502 return false; 1503 if (DefOpIdx) 1504 *DefOpIdx = findTiedOperandIdx(UseOpIdx); 1505 return true; 1506 } 1507 1508 /// Clears kill flags on all operands. 1509 void clearKillInfo(); 1510 1511 /// Replace all occurrences of FromReg with ToReg:SubIdx, 1512 /// properly composing subreg indices where necessary. 1513 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, 1514 const TargetRegisterInfo &RegInfo); 1515 1516 /// We have determined MI kills a register. Look for the 1517 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 1518 /// add a implicit operand if it's not found. Returns true if the operand 1519 /// exists / is added. 1520 bool addRegisterKilled(Register IncomingReg, 1521 const TargetRegisterInfo *RegInfo, 1522 bool AddIfNotFound = false); 1523 1524 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes 1525 /// all aliasing registers. 1526 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo); 1527 1528 /// We have determined MI defined a register without a use. 1529 /// Look for the operand that defines it and mark it as IsDead. If 1530 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 1531 /// true if the operand exists / is added. 1532 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, 1533 bool AddIfNotFound = false); 1534 1535 /// Clear all dead flags on operands defining register @p Reg. 1536 void clearRegisterDeads(Register Reg); 1537 1538 /// Mark all subregister defs of register @p Reg with the undef flag. 1539 /// This function is used when we determined to have a subregister def in an 1540 /// otherwise undefined super register. 1541 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true); 1542 1543 /// We have determined MI defines a register. Make sure there is an operand 1544 /// defining Reg. 1545 void addRegisterDefined(Register Reg, 1546 const TargetRegisterInfo *RegInfo = nullptr); 1547 1548 /// Mark every physreg used by this instruction as 1549 /// dead except those in the UsedRegs list. 1550 /// 1551 /// On instructions with register mask operands, also add implicit-def 1552 /// operands for all registers in UsedRegs. 1553 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, 1554 const TargetRegisterInfo &TRI); 1555 1556 /// Return true if it is safe to move this instruction. If 1557 /// SawStore is set to true, it means that there is a store (or call) between 1558 /// the instruction's location and its intended destination. 1559 bool isSafeToMove(AAResults *AA, bool &SawStore) const; 1560 1561 /// Returns true if this instruction's memory access aliases the memory 1562 /// access of Other. 1563 // 1564 /// Assumes any physical registers used to compute addresses 1565 /// have the same value for both instructions. Returns false if neither 1566 /// instruction writes to memory. 1567 /// 1568 /// @param AA Optional alias analysis, used to compare memory operands. 1569 /// @param Other MachineInstr to check aliasing against. 1570 /// @param UseTBAA Whether to pass TBAA information to alias analysis. 1571 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const; 1572 1573 /// Return true if this instruction may have an ordered 1574 /// or volatile memory reference, or if the information describing the memory 1575 /// reference is not available. Return false if it is known to have no 1576 /// ordered or volatile memory references. 1577 bool hasOrderedMemoryRef() const; 1578 1579 /// Return true if this load instruction never traps and points to a memory 1580 /// location whose value doesn't change during the execution of this function. 1581 /// 1582 /// Examples include loading a value from the constant pool or from the 1583 /// argument area of a function (if it does not change). If the instruction 1584 /// does multiple loads, this returns true only if all of the loads are 1585 /// dereferenceable and invariant. 1586 bool isDereferenceableInvariantLoad(AAResults *AA) const; 1587 1588 /// If the specified instruction is a PHI that always merges together the 1589 /// same virtual register, return the register, otherwise return 0. 1590 unsigned isConstantValuePHI() const; 1591 1592 /// Return true if this instruction has side effects that are not modeled 1593 /// by mayLoad / mayStore, etc. 1594 /// For all instructions, the property is encoded in MCInstrDesc::Flags 1595 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is 1596 /// INLINEASM instruction, in which case the side effect property is encoded 1597 /// in one of its operands (see InlineAsm::Extra_HasSideEffect). 1598 /// 1599 bool hasUnmodeledSideEffects() const; 1600 1601 /// Returns true if it is illegal to fold a load across this instruction. 1602 bool isLoadFoldBarrier() const; 1603 1604 /// Return true if all the defs of this instruction are dead. 1605 bool allDefsAreDead() const; 1606 1607 /// Return a valid size if the instruction is a spill instruction. 1608 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const; 1609 1610 /// Return a valid size if the instruction is a folded spill instruction. 1611 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const; 1612 1613 /// Return a valid size if the instruction is a restore instruction. 1614 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const; 1615 1616 /// Return a valid size if the instruction is a folded restore instruction. 1617 Optional<unsigned> 1618 getFoldedRestoreSize(const TargetInstrInfo *TII) const; 1619 1620 /// Copy implicit register operands from specified 1621 /// instruction to this instruction. 1622 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); 1623 1624 /// Debugging support 1625 /// @{ 1626 /// Determine the generic type to be printed (if needed) on uses and defs. 1627 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, 1628 const MachineRegisterInfo &MRI) const; 1629 1630 /// Return true when an instruction has tied register that can't be determined 1631 /// by the instruction's descriptor. This is useful for MIR printing, to 1632 /// determine whether we need to print the ties or not. 1633 bool hasComplexRegisterTies() const; 1634 1635 /// Print this MI to \p OS. 1636 /// Don't print information that can be inferred from other instructions if 1637 /// \p IsStandalone is false. It is usually true when only a fragment of the 1638 /// function is printed. 1639 /// Only print the defs and the opcode if \p SkipOpers is true. 1640 /// Otherwise, also print operands if \p SkipDebugLoc is true. 1641 /// Otherwise, also print the debug loc, with a terminating newline. 1642 /// \p TII is used to print the opcode name. If it's not present, but the 1643 /// MI is in a function, the opcode will be printed using the function's TII. 1644 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, 1645 bool SkipDebugLoc = false, bool AddNewLine = true, 1646 const TargetInstrInfo *TII = nullptr) const; 1647 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, 1648 bool SkipOpers = false, bool SkipDebugLoc = false, 1649 bool AddNewLine = true, 1650 const TargetInstrInfo *TII = nullptr) const; 1651 void dump() const; 1652 /// Print on dbgs() the current instruction and the instructions defining its 1653 /// operands and so on until we reach \p MaxDepth. 1654 void dumpr(const MachineRegisterInfo &MRI, 1655 unsigned MaxDepth = UINT_MAX) const; 1656 /// @} 1657 1658 //===--------------------------------------------------------------------===// 1659 // Accessors used to build up machine instructions. 1660 1661 /// Add the specified operand to the instruction. If it is an implicit 1662 /// operand, it is added to the end of the operand list. If it is an 1663 /// explicit operand it is added at the end of the explicit operand list 1664 /// (before the first implicit operand). 1665 /// 1666 /// MF must be the machine function that was used to allocate this 1667 /// instruction. 1668 /// 1669 /// MachineInstrBuilder provides a more convenient interface for creating 1670 /// instructions and adding operands. 1671 void addOperand(MachineFunction &MF, const MachineOperand &Op); 1672 1673 /// Add an operand without providing an MF reference. This only works for 1674 /// instructions that are inserted in a basic block. 1675 /// 1676 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be 1677 /// preferred. 1678 void addOperand(const MachineOperand &Op); 1679 1680 /// Replace the instruction descriptor (thus opcode) of 1681 /// the current instruction with a new one. 1682 void setDesc(const MCInstrDesc &tid) { MCID = &tid; } 1683 1684 /// Replace current source information with new such. 1685 /// Avoid using this, the constructor argument is preferable. 1686 void setDebugLoc(DebugLoc dl) { 1687 debugLoc = std::move(dl); 1688 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 1689 } 1690 1691 /// Erase an operand from an instruction, leaving it with one 1692 /// fewer operand than it started with. 1693 void RemoveOperand(unsigned OpNo); 1694 1695 /// Clear this MachineInstr's memory reference descriptor list. This resets 1696 /// the memrefs to their most conservative state. This should be used only 1697 /// as a last resort since it greatly pessimizes our knowledge of the memory 1698 /// access performed by the instruction. 1699 void dropMemRefs(MachineFunction &MF); 1700 1701 /// Assign this MachineInstr's memory reference descriptor list. 1702 /// 1703 /// Unlike other methods, this *will* allocate them into a new array 1704 /// associated with the provided `MachineFunction`. 1705 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); 1706 1707 /// Add a MachineMemOperand to the machine instruction. 1708 /// This function should be used only occasionally. The setMemRefs function 1709 /// is the primary method for setting up a MachineInstr's MemRefs list. 1710 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 1711 1712 /// Clone another MachineInstr's memory reference descriptor list and replace 1713 /// ours with it. 1714 /// 1715 /// Note that `*this` may be the incoming MI! 1716 /// 1717 /// Prefer this API whenever possible as it can avoid allocations in common 1718 /// cases. 1719 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); 1720 1721 /// Clone the merge of multiple MachineInstrs' memory reference descriptors 1722 /// list and replace ours with it. 1723 /// 1724 /// Note that `*this` may be one of the incoming MIs! 1725 /// 1726 /// Prefer this API whenever possible as it can avoid allocations in common 1727 /// cases. 1728 void cloneMergedMemRefs(MachineFunction &MF, 1729 ArrayRef<const MachineInstr *> MIs); 1730 1731 /// Set a symbol that will be emitted just prior to the instruction itself. 1732 /// 1733 /// Setting this to a null pointer will remove any such symbol. 1734 /// 1735 /// FIXME: This is not fully implemented yet. 1736 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1737 1738 /// Set a symbol that will be emitted just after the instruction itself. 1739 /// 1740 /// Setting this to a null pointer will remove any such symbol. 1741 /// 1742 /// FIXME: This is not fully implemented yet. 1743 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1744 1745 /// Clone another MachineInstr's pre- and post- instruction symbols and 1746 /// replace ours with it. 1747 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI); 1748 1749 /// Set a marker on instructions that denotes where we should create and emit 1750 /// heap alloc site labels. This waits until after instruction selection and 1751 /// optimizations to create the label, so it should still work if the 1752 /// instruction is removed or duplicated. 1753 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD); 1754 1755 /// Return the MIFlags which represent both MachineInstrs. This 1756 /// should be used when merging two MachineInstrs into one. This routine does 1757 /// not modify the MIFlags of this MachineInstr. 1758 uint16_t mergeFlagsWith(const MachineInstr& Other) const; 1759 1760 static uint16_t copyFlagsFromInstruction(const Instruction &I); 1761 1762 /// Copy all flags to MachineInst MIFlags 1763 void copyIRFlags(const Instruction &I); 1764 1765 /// Break any tie involving OpIdx. 1766 void untieRegOperand(unsigned OpIdx) { 1767 MachineOperand &MO = getOperand(OpIdx); 1768 if (MO.isReg() && MO.isTied()) { 1769 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; 1770 MO.TiedTo = 0; 1771 } 1772 } 1773 1774 /// Add all implicit def and use operands to this instruction. 1775 void addImplicitDefUseOperands(MachineFunction &MF); 1776 1777 /// Scan instructions immediately following MI and collect any matching 1778 /// DBG_VALUEs. 1779 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); 1780 1781 /// Find all DBG_VALUEs that point to the register def in this instruction 1782 /// and point them to \p Reg instead. 1783 void changeDebugValuesDefReg(Register Reg); 1784 1785 /// Returns the Intrinsic::ID for this instruction. 1786 /// \pre Must have an intrinsic ID operand. 1787 unsigned getIntrinsicID() const { 1788 return getOperand(getNumExplicitDefs()).getIntrinsicID(); 1789 } 1790 1791 /// Sets all register debug operands in this debug value instruction to be 1792 /// undef. 1793 void setDebugValueUndef() { 1794 assert(isDebugValue() && "Must be a debug value instruction."); 1795 for (MachineOperand &MO : debug_operands()) { 1796 if (MO.isReg()) { 1797 MO.setReg(0); 1798 MO.setSubReg(0); 1799 } 1800 } 1801 } 1802 1803 private: 1804 /// If this instruction is embedded into a MachineFunction, return the 1805 /// MachineRegisterInfo object for the current function, otherwise 1806 /// return null. 1807 MachineRegisterInfo *getRegInfo(); 1808 1809 /// Unlink all of the register operands in this instruction from their 1810 /// respective use lists. This requires that the operands already be on their 1811 /// use lists. 1812 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); 1813 1814 /// Add all of the register operands in this instruction from their 1815 /// respective use lists. This requires that the operands not be on their 1816 /// use lists yet. 1817 void AddRegOperandsToUseLists(MachineRegisterInfo&); 1818 1819 /// Slow path for hasProperty when we're dealing with a bundle. 1820 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; 1821 1822 /// Implements the logic of getRegClassConstraintEffectForVReg for the 1823 /// this MI and the given operand index \p OpIdx. 1824 /// If the related operand does not constrained Reg, this returns CurRC. 1825 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( 1826 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, 1827 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; 1828 1829 /// Stores extra instruction information inline or allocates as ExtraInfo 1830 /// based on the number of pointers. 1831 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs, 1832 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, 1833 MDNode *HeapAllocMarker); 1834 }; 1835 1836 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the 1837 /// instruction rather than by pointer value. 1838 /// The hashing and equality testing functions ignore definitions so this is 1839 /// useful for CSE, etc. 1840 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 1841 static inline MachineInstr *getEmptyKey() { 1842 return nullptr; 1843 } 1844 1845 static inline MachineInstr *getTombstoneKey() { 1846 return reinterpret_cast<MachineInstr*>(-1); 1847 } 1848 1849 static unsigned getHashValue(const MachineInstr* const &MI); 1850 1851 static bool isEqual(const MachineInstr* const &LHS, 1852 const MachineInstr* const &RHS) { 1853 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 1854 LHS == getEmptyKey() || LHS == getTombstoneKey()) 1855 return LHS == RHS; 1856 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs); 1857 } 1858 }; 1859 1860 //===----------------------------------------------------------------------===// 1861 // Debugging Support 1862 1863 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 1864 MI.print(OS); 1865 return OS; 1866 } 1867 1868 } // end namespace llvm 1869 1870 #endif // LLVM_CODEGEN_MACHINEINSTR_H 1871