1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces used by SelectionDAG 10// instruction selection generators. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Selection DAG Type Constraint definitions. 16// 17// Note that the semantics of these constraints are hard coded into tblgen. To 18// modify or add constraints, you have to hack tblgen. 19// 20 21class SDTypeConstraint<int opnum> { 22 int OperandNum = opnum; 23} 24 25// SDTCisVT - The specified operand has exactly this VT. 26class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 27 ValueType VT = vt; 28} 29 30class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 31 32// SDTCisInt - The specified operand has integer type. 33class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 34 35// SDTCisFP - The specified operand has floating-point type. 36class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 37 38// SDTCisVec - The specified operand has a vector type. 39class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 40 41// SDTCisSameAs - The two specified operands have identical types. 42class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 43 int OtherOperandNum = OtherOp; 44} 45 46// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 47// smaller than the 'Other' operand. 48class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 49 int OtherOperandNum = OtherOp; 50} 51 52class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 53 int BigOperandNum = BigOp; 54} 55 56/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 57/// type as the element type of OtherOp, which is a vector type. 58class SDTCisEltOfVec<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 64/// with length less that of OtherOp, which is a vector type. 65class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70// SDTCVecEltisVT - The specified operand is vector type with element type 71// of VT. 72class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 73 ValueType VT = vt; 74} 75 76// SDTCisSameNumEltsAs - The two specified operands have identical number 77// of elements. 78class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 79 int OtherOperandNum = OtherOp; 80} 81 82// SDTCisSameSizeAs - The two specified operands have identical size. 83class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 84 int OtherOperandNum = OtherOp; 85} 86 87//===----------------------------------------------------------------------===// 88// Selection DAG Type Profile definitions. 89// 90// These use the constraints defined above to describe the type requirements of 91// the various nodes. These are not hard coded into tblgen, allowing targets to 92// add their own if needed. 93// 94 95// SDTypeProfile - This profile describes the type requirements of a Selection 96// DAG node. 97class SDTypeProfile<int numresults, int numoperands, 98 list<SDTypeConstraint> constraints> { 99 int NumResults = numresults; 100 int NumOperands = numoperands; 101 list<SDTypeConstraint> Constraints = constraints; 102} 103 104// Builtin profiles. 105def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 106def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 107def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 108def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 109def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 110def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 111 112def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 114]>; 115def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 116 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 117]>; 118def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr 119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 120]>; 121def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 122 SDTCisSameAs<0, 1>, SDTCisInt<2> 123]>; 124def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 126]>; 127def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc 128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 129]>; 130 131def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 132 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 133]>; 134def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 135 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 136]>; 137def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 139]>; 140def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse 141 SDTCisSameAs<0, 1>, SDTCisInt<0> 142]>; 143def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 144 SDTCisInt<0>, SDTCisInt<1> 145]>; 146def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 147 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 148]>; 149def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 151]>; 152def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 153 SDTCisSameAs<0, 1>, SDTCisFP<0> 154]>; 155def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fpround 156 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 157]>; 158def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fpextend 159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 160]>; 161def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 162 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 163]>; 164def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 165 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 166]>; 167def SDTFPToIntSatOp : SDTypeProfile<1, 2, [ // fp_to_[su]int_sat 168 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, OtherVT> 169]>; 170def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 171 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 172 SDTCisVTSmallerThanOp<2, 1> 173]>; 174def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 175 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 176 SDTCisOpSmallerThanOp<1, 0> 177]>; 178 179def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 180 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 181]>; 182 183def SDTSelect : SDTypeProfile<1, 3, [ // select 184 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 185]>; 186 187def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 188 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 189]>; 190 191def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 192 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 193 SDTCisVT<5, OtherVT> 194]>; 195 196def SDTBr : SDTypeProfile<0, 1, [ // br 197 SDTCisVT<0, OtherVT> 198]>; 199 200def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 201 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 202]>; 203 204def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 205 SDTCisInt<0>, SDTCisVT<1, OtherVT> 206]>; 207 208def SDTBrind : SDTypeProfile<0, 1, [ // brind 209 SDTCisPtrTy<0> 210]>; 211 212def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 213 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 214]>; 215 216def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 217 218def SDTUBSANTrap : SDTypeProfile<0, 1, []>; // ubsantrap 219 220def SDTLoad : SDTypeProfile<1, 1, [ // load 221 SDTCisPtrTy<1> 222]>; 223 224def SDTStore : SDTypeProfile<0, 2, [ // store 225 SDTCisPtrTy<1> 226]>; 227 228def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 229 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 230]>; 231 232def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store 233 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3> 234]>; 235 236def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load 237 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>, 238 SDTCisSameNumEltsAs<0, 3> 239]>; 240 241def SDTMaskedGather : SDTypeProfile<1, 4, [ 242 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisPtrTy<3>, SDTCisVec<4>, 243 SDTCisSameNumEltsAs<0, 2>, SDTCisSameNumEltsAs<0, 4> 244]>; 245 246def SDTMaskedScatter : SDTypeProfile<0, 4, [ 247 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>, SDTCisVec<3>, 248 SDTCisSameNumEltsAs<0, 1>, SDTCisSameNumEltsAs<0, 3> 249]>; 250 251def SDTVecShuffle : SDTypeProfile<1, 2, [ 252 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 253]>; 254def SDTVecSlice : SDTypeProfile<1, 3, [ // vector splice 255 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisInt<3> 256]>; 257def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 258 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 259]>; 260def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 261 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 262]>; 263def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction 264 SDTCisInt<0>, SDTCisVec<1> 265]>; 266def SDTFPVecReduce : SDTypeProfile<1, 1, [ // FP vector reduction 267 SDTCisFP<0>, SDTCisVec<1> 268]>; 269 270def SDTVecReverse : SDTypeProfile<1, 1, [ // vector reverse 271 SDTCisVec<0>, SDTCisSameAs<0,1> 272]>; 273 274def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 275 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 276]>; 277def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 278 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 279]>; 280 281def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 282 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 283]>; 284 285def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 286 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 287 SDTCisInt<0> 288]>; 289def SDTAtomicFence : SDTypeProfile<0, 2, [ 290 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 291]>; 292def SDTAtomic3 : SDTypeProfile<1, 3, [ 293 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 294]>; 295def SDTAtomic2 : SDTypeProfile<1, 2, [ 296 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 297]>; 298 299def SDTFPAtomic2 : SDTypeProfile<1, 2, [ 300 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1> 301]>; 302 303def SDTAtomicStore : SDTypeProfile<0, 2, [ 304 SDTCisPtrTy<0>, SDTCisInt<1> 305]>; 306def SDTAtomicLoad : SDTypeProfile<1, 1, [ 307 SDTCisInt<0>, SDTCisPtrTy<1> 308]>; 309 310class SDCallSeqStart<list<SDTypeConstraint> constraints> : 311 SDTypeProfile<0, 2, constraints>; 312class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 313 SDTypeProfile<0, 2, constraints>; 314 315//===----------------------------------------------------------------------===// 316// Selection DAG Node definitions. 317// 318class SDNode<string opcode, SDTypeProfile typeprof, 319 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 320 : SDPatternOperator { 321 string Opcode = opcode; 322 string SDClass = sdclass; 323 let Properties = props; 324 SDTypeProfile TypeProfile = typeprof; 325} 326 327// Special TableGen-recognized dag nodes 328def set; 329def implicit; 330def node; 331def srcvalue; 332 333def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 334def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 335def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 336def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 337def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 338def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 339def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 340def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>; 341def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 342 "GlobalAddressSDNode">; 343def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 344 "GlobalAddressSDNode">; 345def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 346 "GlobalAddressSDNode">; 347def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 348 "GlobalAddressSDNode">; 349def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 350 "ConstantPoolSDNode">; 351def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 352 "ConstantPoolSDNode">; 353def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 354 "JumpTableSDNode">; 355def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 356 "JumpTableSDNode">; 357def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 358 "FrameIndexSDNode">; 359def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 360 "FrameIndexSDNode">; 361def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 362 "ExternalSymbolSDNode">; 363def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 364 "ExternalSymbolSDNode">; 365def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 366def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 367 "BlockAddressSDNode">; 368def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 369 "BlockAddressSDNode">; 370 371def add : SDNode<"ISD::ADD" , SDTIntBinOp , 372 [SDNPCommutative, SDNPAssociative]>; 373def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 374def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 375 [SDNPCommutative, SDNPAssociative]>; 376def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 377def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 378def avgfloors : SDNode<"ISD::AVGFLOORS" , SDTIntBinOp, [SDNPCommutative]>; 379def avgflooru : SDNode<"ISD::AVGFLOORU" , SDTIntBinOp, [SDNPCommutative]>; 380def avgceils : SDNode<"ISD::AVGCEILS" , SDTIntBinOp, [SDNPCommutative]>; 381def avgceilu : SDNode<"ISD::AVGCEILU" , SDTIntBinOp, [SDNPCommutative]>; 382def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>; 383def abdu : SDNode<"ISD::ABDU" , SDTIntBinOp, [SDNPCommutative]>; 384def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 385def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 386def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 387def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 388def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 389def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 390def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 391def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 392def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 393def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 394def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 395def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 396def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 397def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>; 398def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>; 399def and : SDNode<"ISD::AND" , SDTIntBinOp, 400 [SDNPCommutative, SDNPAssociative]>; 401def or : SDNode<"ISD::OR" , SDTIntBinOp, 402 [SDNPCommutative, SDNPAssociative]>; 403def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 404 [SDNPCommutative, SDNPAssociative]>; 405def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 406 [SDNPCommutative, SDNPOutGlue]>; 407def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 408 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 409def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 410 [SDNPOutGlue]>; 411def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 412 [SDNPOutGlue, SDNPInGlue]>; 413def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 414 [SDNPCommutative, SDNPAssociative]>; 415def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 416 [SDNPCommutative, SDNPAssociative]>; 417def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 418 [SDNPCommutative, SDNPAssociative]>; 419def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 420 [SDNPCommutative, SDNPAssociative]>; 421 422def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 423def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 424def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>; 425def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>; 426def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>; 427def ushlsat : SDNode<"ISD::USHLSAT" , SDTIntBinOp>; 428 429def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 430def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 431def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 432def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 433def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>; 434def sdivfixsat : SDNode<"ISD::SDIVFIXSAT", SDTIntScaledBinOp>; 435def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>; 436def udivfixsat : SDNode<"ISD::UDIVFIXSAT", SDTIntScaledBinOp>; 437 438def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 439def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 440def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 441 442def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 443def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 444def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 445def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>; 446def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>; 447def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>; 448def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 449def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 450def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 451def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 452def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 453def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 454def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 455def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 456def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 457def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 458 459def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; 460def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; 461def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; 462def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; 463def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; 464def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>; 465 466def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 467def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 468def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 469def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 470def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 471def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>; 472def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>; 473def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 474def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 475 [SDNPCommutative, SDNPAssociative]>; 476def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 477 [SDNPCommutative, SDNPAssociative]>; 478def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, 479 [SDNPCommutative]>; 480def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, 481 [SDNPCommutative]>; 482def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp, 483 [SDNPCommutative, SDNPAssociative]>; 484def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp, 485 [SDNPCommutative, SDNPAssociative]>; 486def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 487def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 488def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 489def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 490def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 491def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 492def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 493def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 494def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 495def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 496def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 497def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 498def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 499def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 500def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 501def froundeven : SDNode<"ISD::FROUNDEVEN" , SDTFPUnaryOp>; 502 503def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; 504def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; 505def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>; 506def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>; 507 508def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 509def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 510def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 511 512def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 513def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 514def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 515def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 516def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>; 517def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>; 518def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 519def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 520 521def strict_fadd : SDNode<"ISD::STRICT_FADD", 522 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 523def strict_fsub : SDNode<"ISD::STRICT_FSUB", 524 SDTFPBinOp, [SDNPHasChain]>; 525def strict_fmul : SDNode<"ISD::STRICT_FMUL", 526 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 527def strict_fdiv : SDNode<"ISD::STRICT_FDIV", 528 SDTFPBinOp, [SDNPHasChain]>; 529def strict_frem : SDNode<"ISD::STRICT_FREM", 530 SDTFPBinOp, [SDNPHasChain]>; 531def strict_fma : SDNode<"ISD::STRICT_FMA", 532 SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>; 533def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", 534 SDTFPUnaryOp, [SDNPHasChain]>; 535def strict_fsin : SDNode<"ISD::STRICT_FSIN", 536 SDTFPUnaryOp, [SDNPHasChain]>; 537def strict_fcos : SDNode<"ISD::STRICT_FCOS", 538 SDTFPUnaryOp, [SDNPHasChain]>; 539def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", 540 SDTFPUnaryOp, [SDNPHasChain]>; 541def strict_fpow : SDNode<"ISD::STRICT_FPOW", 542 SDTFPBinOp, [SDNPHasChain]>; 543def strict_flog2 : SDNode<"ISD::STRICT_FLOG2", 544 SDTFPUnaryOp, [SDNPHasChain]>; 545def strict_frint : SDNode<"ISD::STRICT_FRINT", 546 SDTFPUnaryOp, [SDNPHasChain]>; 547def strict_lrint : SDNode<"ISD::STRICT_LRINT", 548 SDTFPToIntOp, [SDNPHasChain]>; 549def strict_llrint : SDNode<"ISD::STRICT_LLRINT", 550 SDTFPToIntOp, [SDNPHasChain]>; 551def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT", 552 SDTFPUnaryOp, [SDNPHasChain]>; 553def strict_fceil : SDNode<"ISD::STRICT_FCEIL", 554 SDTFPUnaryOp, [SDNPHasChain]>; 555def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR", 556 SDTFPUnaryOp, [SDNPHasChain]>; 557def strict_lround : SDNode<"ISD::STRICT_LROUND", 558 SDTFPToIntOp, [SDNPHasChain]>; 559def strict_llround : SDNode<"ISD::STRICT_LLROUND", 560 SDTFPToIntOp, [SDNPHasChain]>; 561def strict_fround : SDNode<"ISD::STRICT_FROUND", 562 SDTFPUnaryOp, [SDNPHasChain]>; 563def strict_froundeven : SDNode<"ISD::STRICT_FROUNDEVEN", 564 SDTFPUnaryOp, [SDNPHasChain]>; 565def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC", 566 SDTFPUnaryOp, [SDNPHasChain]>; 567def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM", 568 SDTFPBinOp, [SDNPHasChain, 569 SDNPCommutative, SDNPAssociative]>; 570def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM", 571 SDTFPBinOp, [SDNPHasChain, 572 SDNPCommutative, SDNPAssociative]>; 573def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM", 574 SDTFPBinOp, [SDNPHasChain, 575 SDNPCommutative, SDNPAssociative]>; 576def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM", 577 SDTFPBinOp, [SDNPHasChain, 578 SDNPCommutative, SDNPAssociative]>; 579def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND", 580 SDTFPRoundOp, [SDNPHasChain]>; 581def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND", 582 SDTFPExtendOp, [SDNPHasChain]>; 583def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT", 584 SDTFPToIntOp, [SDNPHasChain]>; 585def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT", 586 SDTFPToIntOp, [SDNPHasChain]>; 587def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP", 588 SDTIntToFPOp, [SDNPHasChain]>; 589def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP", 590 SDTIntToFPOp, [SDNPHasChain]>; 591def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>; 592def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>; 593 594def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 595def select : SDNode<"ISD::SELECT" , SDTSelect>; 596def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 597def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 598 599def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 600def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 601def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 602def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 603def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 604 [SDNPHasChain, SDNPSideEffect]>; 605def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 606 607def trap : SDNode<"ISD::TRAP" , SDTNone, 608 [SDNPHasChain, SDNPSideEffect]>; 609def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 610 [SDNPHasChain, SDNPSideEffect]>; 611def ubsantrap : SDNode<"ISD::UBSANTRAP" , SDTUBSANTrap, 612 [SDNPHasChain, SDNPSideEffect]>; 613 614def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 615 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 616 SDNPMemOperand]>; 617 618def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 619 [SDNPHasChain, SDNPSideEffect]>; 620 621def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 622 [SDNPHasChain, SDNPSideEffect]>; 623 624def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 625 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 626def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 627 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 628def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 629 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 630def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 631 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 632def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 633 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 634def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2, 635 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 636def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 637 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 638def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 639 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 640def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 641 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 642def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 643 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 644def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 645 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 646def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 647 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 648def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 649 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 650def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2, 651 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 652def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2, 653 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 654def atomic_load_fmax : SDNode<"ISD::ATOMIC_LOAD_FMAX", SDTFPAtomic2, 655 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 656def atomic_load_fmin : SDNode<"ISD::ATOMIC_LOAD_FMIN", SDTFPAtomic2, 657 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 658 659def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 660 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 661def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 662 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 663 664def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore, 665 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 666def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad, 667 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 668 669def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 670 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 671 672def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 673 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 674 675// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 676// and truncst (see below). 677def ld : SDNode<"ISD::LOAD" , SDTLoad, 678 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 679def st : SDNode<"ISD::STORE" , SDTStore, 680 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 681def ist : SDNode<"ISD::STORE" , SDTIStore, 682 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 683 684def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 685def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>; 686def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>; 687def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 688def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>; 689def step_vector : SDNode<"ISD::STEP_VECTOR", SDTypeProfile<1, 1, 690 [SDTCisVec<0>, SDTCisInt<1>]>, []>; 691def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 692 []>; 693 694// vector_extract/vector_insert are deprecated. extractelt/insertelt 695// are preferred. 696def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 697 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 698def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 699 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 700def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 701 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 702 703// This operator does not do subvector type checking. The ARM 704// backend, at least, needs it. 705def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 706 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 707 []>; 708def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR", 709 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVec<2>, SDTCisInt<3>]>, 710 []>; 711 712// This operator does subvector type checking. 713def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 714def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 715 716// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 717// these internally. Don't reference these directly. 718def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 719 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 720 [SDNPHasChain]>; 721def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 722 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 723 [SDNPHasChain]>; 724def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 725 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 726 727def SDT_assert : SDTypeProfile<1, 1, 728 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 729def assertsext : SDNode<"ISD::AssertSext", SDT_assert>; 730def assertzext : SDNode<"ISD::AssertZext", SDT_assert>; 731def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>; 732 733//===----------------------------------------------------------------------===// 734// Selection DAG Condition Codes 735 736class CondCode<string fcmpName = "", string icmpName = ""> { 737 string ICmpPredicate = icmpName; 738 string FCmpPredicate = fcmpName; 739} 740 741// ISD::CondCode enums, and mapping to CmpInst::Predicate names 742def SETOEQ : CondCode<"FCMP_OEQ">; 743def SETOGT : CondCode<"FCMP_OGT">; 744def SETOGE : CondCode<"FCMP_OGE">; 745def SETOLT : CondCode<"FCMP_OLT">; 746def SETOLE : CondCode<"FCMP_OLE">; 747def SETONE : CondCode<"FCMP_ONE">; 748def SETO : CondCode<"FCMP_ORD">; 749def SETUO : CondCode<"FCMP_UNO">; 750def SETUEQ : CondCode<"FCMP_UEQ">; 751def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">; 752def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">; 753def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">; 754def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">; 755def SETUNE : CondCode<"FCMP_UNE">; 756def SETEQ : CondCode<"", "ICMP_EQ">; 757def SETGT : CondCode<"", "ICMP_SGT">; 758def SETGE : CondCode<"", "ICMP_SGE">; 759def SETLT : CondCode<"", "ICMP_SLT">; 760def SETLE : CondCode<"", "ICMP_SLE">; 761def SETNE : CondCode<"", "ICMP_NE">; 762 763//===----------------------------------------------------------------------===// 764// Selection DAG Node Transformation Functions. 765// 766// This mechanism allows targets to manipulate nodes in the output DAG once a 767// match has been formed. This is typically used to manipulate immediate 768// values. 769// 770class SDNodeXForm<SDNode opc, code xformFunction> { 771 SDNode Opcode = opc; 772 code XFormFunction = xformFunction; 773} 774 775def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 776 777//===----------------------------------------------------------------------===// 778// Selection DAG Pattern Fragments. 779// 780// Pattern fragments are reusable chunks of dags that match specific things. 781// They can take arguments and have C++ predicates that control whether they 782// match. They are intended to make the patterns for common instructions more 783// compact and readable. 784// 785 786/// PatFrags - Represents a set of pattern fragments. Each single fragment 787/// can match something on the DAG, from a single node to multiple nested other 788/// fragments. The whole set of fragments matches if any of the single 789/// fragments match. This allows e.g. matching and "add with overflow" and 790/// a regular "add" with the same fragment set. 791/// 792class PatFrags<dag ops, list<dag> frags, code pred = [{}], 793 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 794 dag Operands = ops; 795 list<dag> Fragments = frags; 796 code PredicateCode = pred; 797 code GISelPredicateCode = [{}]; 798 code ImmediateCode = [{}]; 799 SDNodeXForm OperandTransform = xform; 800 801 // When this is set, the PredicateCode may refer to a constant Operands 802 // vector which contains the captured nodes of the DAG, in the order listed 803 // by the Operands field above. 804 // 805 // This is useful when Fragments involves associative / commutative 806 // operators: a single piece of code can easily refer to all operands even 807 // when re-associated / commuted variants of the fragment are matched. 808 bit PredicateCodeUsesOperands = false; 809 810 // Define a few pre-packaged predicates. This helps GlobalISel import 811 // existing rules from SelectionDAG for many common cases. 812 // They will be tested prior to the code in pred and must not be used in 813 // ImmLeaf and its subclasses. 814 815 // If set to true, a predicate is added that checks for the absence of use of 816 // the first result. 817 bit HasNoUse = ?; 818 819 // Is the desired pre-packaged predicate for a load? 820 bit IsLoad = ?; 821 // Is the desired pre-packaged predicate for a store? 822 bit IsStore = ?; 823 // Is the desired pre-packaged predicate for an atomic? 824 bit IsAtomic = ?; 825 826 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 827 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 828 bit IsUnindexed = ?; 829 830 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 831 bit IsNonExtLoad = ?; 832 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 833 bit IsAnyExtLoad = ?; 834 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 835 bit IsSignExtLoad = ?; 836 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 837 bit IsZeroExtLoad = ?; 838 // !cast<StoreSDNode>(N)->isTruncatingStore(); 839 // cast<StoreSDNode>(N)->isTruncatingStore(); 840 bit IsTruncStore = ?; 841 842 // cast<MemSDNode>(N)->getAddressSpace() == 843 // If this empty, accept any address space. 844 list<int> AddressSpaces = ?; 845 846 // cast<MemSDNode>(N)->getAlignment() >= 847 // If this is empty, accept any alignment. 848 int MinAlignment = ?; 849 850 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic 851 bit IsAtomicOrderingMonotonic = ?; 852 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire 853 bit IsAtomicOrderingAcquire = ?; 854 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release 855 bit IsAtomicOrderingRelease = ?; 856 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease 857 bit IsAtomicOrderingAcquireRelease = ?; 858 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent 859 bit IsAtomicOrderingSequentiallyConsistent = ?; 860 861 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 862 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 863 bit IsAtomicOrderingAcquireOrStronger = ?; 864 865 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 866 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 867 bit IsAtomicOrderingReleaseOrStronger = ?; 868 869 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 870 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 871 ValueType MemoryVT = ?; 872 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 873 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 874 ValueType ScalarMemoryVT = ?; 875} 876 877// PatFrag - A version of PatFrags matching only a single fragment. 878class PatFrag<dag ops, dag frag, code pred = [{}], 879 SDNodeXForm xform = NOOP_SDNodeXForm> 880 : PatFrags<ops, [frag], pred, xform>; 881 882// OutPatFrag is a pattern fragment that is used as part of an output pattern 883// (not an input pattern). These do not have predicates or transforms, but are 884// used to avoid repeated subexpressions in output patterns. 885class OutPatFrag<dag ops, dag frag> 886 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 887 888// PatLeaf's are pattern fragments that have no operands. This is just a helper 889// to define immediates and other common things concisely. 890class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 891 : PatFrag<(ops), frag, pred, xform>; 892 893 894// ImmLeaf is a pattern fragment with a constraint on the immediate. The 895// constraint is a function that is run on the immediate (always with the value 896// sign extended out to an int64_t) as Imm. For example: 897// 898// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 899// 900// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 901// is preferred over using PatLeaf because it allows the code generator to 902// reason more about the constraint. 903// 904// If FastIsel should ignore all instructions that have an operand of this type, 905// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 906// the code size of the generated fast instruction selector. 907class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 908 SDNode ImmNode = imm> 909 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 910 let ImmediateCode = pred; 911 bit FastIselShouldIgnore = false; 912 913 // Is the data type of the immediate an APInt? 914 bit IsAPInt = false; 915 916 // Is the data type of the immediate an APFloat? 917 bit IsAPFloat = false; 918} 919 920// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead 921// of imm/Constant. 922class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 923 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>; 924 925// An ImmLeaf except that Imm is an APInt. This is useful when you need to 926// zero-extend the immediate instead of sign-extend it. 927// 928// Note that FastISel does not currently understand IntImmLeaf and will not 929// generate code for rules that make use of it. As such, it does not make sense 930// to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 931// IntImmLeaf will allow GlobalISel to import the rule. 932class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 933 : ImmLeaf<vt, pred, xform> { 934 let IsAPInt = true; 935 let FastIselShouldIgnore = true; 936} 937 938// An ImmLeaf except that Imm is an APFloat. 939// 940// Note that FastISel does not currently understand FPImmLeaf and will not 941// generate code for rules that make use of it. 942class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 943 : ImmLeaf<vt, pred, xform, fpimm> { 944 let IsAPFloat = true; 945 let FastIselShouldIgnore = true; 946} 947 948// Leaf fragments. 949 950def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 951def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 952 953// Use ISD::isConstantSplatVectorAllOnes or ISD::isConstantSplatVectorAllZeros 954// to look for the corresponding build_vector or splat_vector. Will look through 955// bitcasts and check for either opcode, except when used as a pattern root. 956// When used as a pattern root, only fixed-length build_vector and scalable 957// splat_vector are supported. 958def immAllOnesV : SDPatternOperator; // ISD::isConstantSplatVectorAllOnes 959def immAllZerosV : SDPatternOperator; // ISD::isConstantSplatVectorAllZeros 960 961// Other helper fragments. 962def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 963def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 964def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 965 966def zanyext : PatFrags<(ops node:$op), 967 [(zext node:$op), 968 (anyext node:$op)]>; 969 970// null_frag - The null pattern operator is used in multiclass instantiations 971// which accept an SDPatternOperator for use in matching patterns for internal 972// definitions. When expanding a pattern, if the null fragment is referenced 973// in the expansion, the pattern is discarded and it is as-if '[]' had been 974// specified. This allows multiclasses to have the isel patterns be optional. 975def null_frag : SDPatternOperator; 976 977// load fragments. 978def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 979 let IsLoad = true; 980 let IsUnindexed = true; 981} 982def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 983 let IsLoad = true; 984 let IsNonExtLoad = true; 985} 986 987// extending load fragments. 988def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 989 let IsLoad = true; 990 let IsAnyExtLoad = true; 991} 992def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 993 let IsLoad = true; 994 let IsSignExtLoad = true; 995} 996def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 997 let IsLoad = true; 998 let IsZeroExtLoad = true; 999} 1000 1001def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1002 let IsLoad = true; 1003 let MemoryVT = i1; 1004} 1005def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1006 let IsLoad = true; 1007 let MemoryVT = i8; 1008} 1009def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1010 let IsLoad = true; 1011 let MemoryVT = i16; 1012} 1013def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1014 let IsLoad = true; 1015 let MemoryVT = i32; 1016} 1017def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1018 let IsLoad = true; 1019 let MemoryVT = f16; 1020} 1021def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1022 let IsLoad = true; 1023 let MemoryVT = f32; 1024} 1025def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1026 let IsLoad = true; 1027 let MemoryVT = f64; 1028} 1029 1030def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1031 let IsLoad = true; 1032 let MemoryVT = i1; 1033} 1034def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1035 let IsLoad = true; 1036 let MemoryVT = i8; 1037} 1038def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1039 let IsLoad = true; 1040 let MemoryVT = i16; 1041} 1042def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1043 let IsLoad = true; 1044 let MemoryVT = i32; 1045} 1046 1047def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1048 let IsLoad = true; 1049 let MemoryVT = i1; 1050} 1051def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1052 let IsLoad = true; 1053 let MemoryVT = i8; 1054} 1055def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1056 let IsLoad = true; 1057 let MemoryVT = i16; 1058} 1059def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1060 let IsLoad = true; 1061 let MemoryVT = i32; 1062} 1063 1064def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1065 let IsLoad = true; 1066 let ScalarMemoryVT = i1; 1067} 1068def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1069 let IsLoad = true; 1070 let ScalarMemoryVT = i8; 1071} 1072def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1073 let IsLoad = true; 1074 let ScalarMemoryVT = i16; 1075} 1076def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1077 let IsLoad = true; 1078 let ScalarMemoryVT = i32; 1079} 1080def extloadvf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1081 let IsLoad = true; 1082 let ScalarMemoryVT = f16; 1083} 1084def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1085 let IsLoad = true; 1086 let ScalarMemoryVT = f32; 1087} 1088def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1089 let IsLoad = true; 1090 let ScalarMemoryVT = f64; 1091} 1092 1093def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1094 let IsLoad = true; 1095 let ScalarMemoryVT = i1; 1096} 1097def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1098 let IsLoad = true; 1099 let ScalarMemoryVT = i8; 1100} 1101def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1102 let IsLoad = true; 1103 let ScalarMemoryVT = i16; 1104} 1105def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1106 let IsLoad = true; 1107 let ScalarMemoryVT = i32; 1108} 1109 1110def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1111 let IsLoad = true; 1112 let ScalarMemoryVT = i1; 1113} 1114def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1115 let IsLoad = true; 1116 let ScalarMemoryVT = i8; 1117} 1118def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1119 let IsLoad = true; 1120 let ScalarMemoryVT = i16; 1121} 1122def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1123 let IsLoad = true; 1124 let ScalarMemoryVT = i32; 1125} 1126 1127// store fragments. 1128def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 1129 (st node:$val, node:$ptr)> { 1130 let IsStore = true; 1131 let IsUnindexed = true; 1132} 1133def store : PatFrag<(ops node:$val, node:$ptr), 1134 (unindexedstore node:$val, node:$ptr)> { 1135 let IsStore = true; 1136 let IsTruncStore = false; 1137} 1138 1139// truncstore fragments. 1140def truncstore : PatFrag<(ops node:$val, node:$ptr), 1141 (unindexedstore node:$val, node:$ptr)> { 1142 let IsStore = true; 1143 let IsTruncStore = true; 1144} 1145def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 1146 (truncstore node:$val, node:$ptr)> { 1147 let IsStore = true; 1148 let MemoryVT = i8; 1149 let IsTruncStore = true; 1150} 1151def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 1152 (truncstore node:$val, node:$ptr)> { 1153 let IsStore = true; 1154 let MemoryVT = i16; 1155 let IsTruncStore = true; 1156} 1157def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 1158 (truncstore node:$val, node:$ptr)> { 1159 let IsStore = true; 1160 let MemoryVT = i32; 1161 let IsTruncStore = true; 1162} 1163def truncstoref16 : PatFrag<(ops node:$val, node:$ptr), 1164 (truncstore node:$val, node:$ptr)> { 1165 let IsStore = true; 1166 let MemoryVT = f16; 1167} 1168def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 1169 (truncstore node:$val, node:$ptr)> { 1170 let IsStore = true; 1171 let MemoryVT = f32; 1172} 1173def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 1174 (truncstore node:$val, node:$ptr)> { 1175 let IsStore = true; 1176 let MemoryVT = f64; 1177} 1178 1179def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 1180 (truncstore node:$val, node:$ptr)> { 1181 let IsStore = true; 1182 let ScalarMemoryVT = i8; 1183} 1184 1185def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 1186 (truncstore node:$val, node:$ptr)> { 1187 let IsStore = true; 1188 let ScalarMemoryVT = i16; 1189} 1190 1191def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 1192 (truncstore node:$val, node:$ptr)> { 1193 let IsStore = true; 1194 let ScalarMemoryVT = i32; 1195} 1196 1197// indexed store fragments. 1198def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 1199 (ist node:$val, node:$base, node:$offset)> { 1200 let IsStore = true; 1201 let IsTruncStore = false; 1202} 1203 1204def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 1205 (istore node:$val, node:$base, node:$offset), [{ 1206 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1207 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1208}]>; 1209 1210def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 1211 (ist node:$val, node:$base, node:$offset)> { 1212 let IsStore = true; 1213 let IsTruncStore = true; 1214} 1215def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1216 (itruncstore node:$val, node:$base, node:$offset), [{ 1217 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1218 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1219}]>; 1220def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1221 (pre_truncst node:$val, node:$base, node:$offset)> { 1222 let IsStore = true; 1223 let MemoryVT = i1; 1224} 1225def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1226 (pre_truncst node:$val, node:$base, node:$offset)> { 1227 let IsStore = true; 1228 let MemoryVT = i8; 1229} 1230def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1231 (pre_truncst node:$val, node:$base, node:$offset)> { 1232 let IsStore = true; 1233 let MemoryVT = i16; 1234} 1235def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1236 (pre_truncst node:$val, node:$base, node:$offset)> { 1237 let IsStore = true; 1238 let MemoryVT = i32; 1239} 1240def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1241 (pre_truncst node:$val, node:$base, node:$offset)> { 1242 let IsStore = true; 1243 let MemoryVT = f32; 1244} 1245def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1246 (pre_truncst node:$val, node:$base, node:$offset)> { 1247 let IsStore = true; 1248 let ScalarMemoryVT = i8; 1249} 1250def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1251 (pre_truncst node:$val, node:$base, node:$offset)> { 1252 let IsStore = true; 1253 let ScalarMemoryVT = i16; 1254} 1255 1256def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1257 (istore node:$val, node:$ptr, node:$offset), [{ 1258 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1259 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1260}]>; 1261 1262def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1263 (itruncstore node:$val, node:$base, node:$offset), [{ 1264 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1265 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1266}]>; 1267def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1268 (post_truncst node:$val, node:$base, node:$offset)> { 1269 let IsStore = true; 1270 let MemoryVT = i1; 1271} 1272def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1273 (post_truncst node:$val, node:$base, node:$offset)> { 1274 let IsStore = true; 1275 let MemoryVT = i8; 1276} 1277def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1278 (post_truncst node:$val, node:$base, node:$offset)> { 1279 let IsStore = true; 1280 let MemoryVT = i16; 1281} 1282def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1283 (post_truncst node:$val, node:$base, node:$offset)> { 1284 let IsStore = true; 1285 let MemoryVT = i32; 1286} 1287def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1288 (post_truncst node:$val, node:$base, node:$offset)> { 1289 let IsStore = true; 1290 let MemoryVT = f32; 1291} 1292def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1293 (post_truncst node:$val, node:$base, node:$offset)> { 1294 let IsStore = true; 1295 let ScalarMemoryVT = i8; 1296} 1297def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1298 (post_truncst node:$val, node:$base, node:$offset)> { 1299 let IsStore = true; 1300 let ScalarMemoryVT = i16; 1301} 1302 1303// TODO: Split these into volatile and unordered flavors to enable 1304// selectively legal optimizations for each. (See D66309) 1305def simple_load : PatFrag<(ops node:$ptr), 1306 (load node:$ptr), [{ 1307 return cast<LoadSDNode>(N)->isSimple(); 1308}]>; 1309def simple_store : PatFrag<(ops node:$val, node:$ptr), 1310 (store node:$val, node:$ptr), [{ 1311 return cast<StoreSDNode>(N)->isSimple(); 1312}]>; 1313 1314// nontemporal store fragments. 1315def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1316 (store node:$val, node:$ptr), [{ 1317 return cast<StoreSDNode>(N)->isNonTemporal(); 1318}]>; 1319 1320def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1321 (nontemporalstore node:$val, node:$ptr), [{ 1322 StoreSDNode *St = cast<StoreSDNode>(N); 1323 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 1324}]>; 1325 1326def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1327 (nontemporalstore node:$val, node:$ptr), [{ 1328 StoreSDNode *St = cast<StoreSDNode>(N); 1329 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1330}]>; 1331 1332// nontemporal load fragments. 1333def nontemporalload : PatFrag<(ops node:$ptr), 1334 (load node:$ptr), [{ 1335 return cast<LoadSDNode>(N)->isNonTemporal(); 1336}]>; 1337 1338def alignednontemporalload : PatFrag<(ops node:$ptr), 1339 (nontemporalload node:$ptr), [{ 1340 LoadSDNode *Ld = cast<LoadSDNode>(N); 1341 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1342}]>; 1343 1344// setcc convenience fragments. 1345def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1346 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1347def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1348 (setcc node:$lhs, node:$rhs, SETOGT)>; 1349def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1350 (setcc node:$lhs, node:$rhs, SETOGE)>; 1351def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1352 (setcc node:$lhs, node:$rhs, SETOLT)>; 1353def setole : PatFrag<(ops node:$lhs, node:$rhs), 1354 (setcc node:$lhs, node:$rhs, SETOLE)>; 1355def setone : PatFrag<(ops node:$lhs, node:$rhs), 1356 (setcc node:$lhs, node:$rhs, SETONE)>; 1357def seto : PatFrag<(ops node:$lhs, node:$rhs), 1358 (setcc node:$lhs, node:$rhs, SETO)>; 1359def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1360 (setcc node:$lhs, node:$rhs, SETUO)>; 1361def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1362 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1363def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1364 (setcc node:$lhs, node:$rhs, SETUGT)>; 1365def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1366 (setcc node:$lhs, node:$rhs, SETUGE)>; 1367def setult : PatFrag<(ops node:$lhs, node:$rhs), 1368 (setcc node:$lhs, node:$rhs, SETULT)>; 1369def setule : PatFrag<(ops node:$lhs, node:$rhs), 1370 (setcc node:$lhs, node:$rhs, SETULE)>; 1371def setune : PatFrag<(ops node:$lhs, node:$rhs), 1372 (setcc node:$lhs, node:$rhs, SETUNE)>; 1373def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1374 (setcc node:$lhs, node:$rhs, SETEQ)>; 1375def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1376 (setcc node:$lhs, node:$rhs, SETGT)>; 1377def setge : PatFrag<(ops node:$lhs, node:$rhs), 1378 (setcc node:$lhs, node:$rhs, SETGE)>; 1379def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1380 (setcc node:$lhs, node:$rhs, SETLT)>; 1381def setle : PatFrag<(ops node:$lhs, node:$rhs), 1382 (setcc node:$lhs, node:$rhs, SETLE)>; 1383def setne : PatFrag<(ops node:$lhs, node:$rhs), 1384 (setcc node:$lhs, node:$rhs, SETNE)>; 1385 1386// We don't have strict FP extended loads as single DAG nodes, but we can 1387// still provide convenience fragments to match those operations. 1388def strict_extloadf32 : PatFrag<(ops node:$ptr), 1389 (strict_fpextend (f32 (load node:$ptr)))>; 1390def strict_extloadf64 : PatFrag<(ops node:$ptr), 1391 (strict_fpextend (f64 (load node:$ptr)))>; 1392 1393// Convenience fragments to match both strict and non-strict fp operations 1394def any_fadd : PatFrags<(ops node:$lhs, node:$rhs), 1395 [(strict_fadd node:$lhs, node:$rhs), 1396 (fadd node:$lhs, node:$rhs)]>; 1397def any_fsub : PatFrags<(ops node:$lhs, node:$rhs), 1398 [(strict_fsub node:$lhs, node:$rhs), 1399 (fsub node:$lhs, node:$rhs)]>; 1400def any_fmul : PatFrags<(ops node:$lhs, node:$rhs), 1401 [(strict_fmul node:$lhs, node:$rhs), 1402 (fmul node:$lhs, node:$rhs)]>; 1403def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs), 1404 [(strict_fdiv node:$lhs, node:$rhs), 1405 (fdiv node:$lhs, node:$rhs)]>; 1406def any_frem : PatFrags<(ops node:$lhs, node:$rhs), 1407 [(strict_frem node:$lhs, node:$rhs), 1408 (frem node:$lhs, node:$rhs)]>; 1409def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3), 1410 [(strict_fma node:$src1, node:$src2, node:$src3), 1411 (fma node:$src1, node:$src2, node:$src3)]>; 1412def any_fsqrt : PatFrags<(ops node:$src), 1413 [(strict_fsqrt node:$src), 1414 (fsqrt node:$src)]>; 1415def any_fsin : PatFrags<(ops node:$src), 1416 [(strict_fsin node:$src), 1417 (fsin node:$src)]>; 1418def any_fcos : PatFrags<(ops node:$src), 1419 [(strict_fcos node:$src), 1420 (fcos node:$src)]>; 1421def any_fexp2 : PatFrags<(ops node:$src), 1422 [(strict_fexp2 node:$src), 1423 (fexp2 node:$src)]>; 1424def any_fpow : PatFrags<(ops node:$lhs, node:$rhs), 1425 [(strict_fpow node:$lhs, node:$rhs), 1426 (fpow node:$lhs, node:$rhs)]>; 1427def any_flog2 : PatFrags<(ops node:$src), 1428 [(strict_flog2 node:$src), 1429 (flog2 node:$src)]>; 1430def any_frint : PatFrags<(ops node:$src), 1431 [(strict_frint node:$src), 1432 (frint node:$src)]>; 1433def any_lrint : PatFrags<(ops node:$src), 1434 [(strict_lrint node:$src), 1435 (lrint node:$src)]>; 1436def any_llrint : PatFrags<(ops node:$src), 1437 [(strict_llrint node:$src), 1438 (llrint node:$src)]>; 1439def any_fnearbyint : PatFrags<(ops node:$src), 1440 [(strict_fnearbyint node:$src), 1441 (fnearbyint node:$src)]>; 1442def any_fceil : PatFrags<(ops node:$src), 1443 [(strict_fceil node:$src), 1444 (fceil node:$src)]>; 1445def any_ffloor : PatFrags<(ops node:$src), 1446 [(strict_ffloor node:$src), 1447 (ffloor node:$src)]>; 1448def any_lround : PatFrags<(ops node:$src), 1449 [(strict_lround node:$src), 1450 (lround node:$src)]>; 1451def any_llround : PatFrags<(ops node:$src), 1452 [(strict_llround node:$src), 1453 (llround node:$src)]>; 1454def any_fround : PatFrags<(ops node:$src), 1455 [(strict_fround node:$src), 1456 (fround node:$src)]>; 1457def any_froundeven : PatFrags<(ops node:$src), 1458 [(strict_froundeven node:$src), 1459 (froundeven node:$src)]>; 1460def any_ftrunc : PatFrags<(ops node:$src), 1461 [(strict_ftrunc node:$src), 1462 (ftrunc node:$src)]>; 1463def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs), 1464 [(strict_fmaxnum node:$lhs, node:$rhs), 1465 (fmaxnum node:$lhs, node:$rhs)]>; 1466def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs), 1467 [(strict_fminnum node:$lhs, node:$rhs), 1468 (fminnum node:$lhs, node:$rhs)]>; 1469def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs), 1470 [(strict_fmaximum node:$lhs, node:$rhs), 1471 (fmaximum node:$lhs, node:$rhs)]>; 1472def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs), 1473 [(strict_fminimum node:$lhs, node:$rhs), 1474 (fminimum node:$lhs, node:$rhs)]>; 1475def any_fpround : PatFrags<(ops node:$src), 1476 [(strict_fpround node:$src), 1477 (fpround node:$src)]>; 1478def any_fpextend : PatFrags<(ops node:$src), 1479 [(strict_fpextend node:$src), 1480 (fpextend node:$src)]>; 1481def any_extloadf32 : PatFrags<(ops node:$ptr), 1482 [(strict_extloadf32 node:$ptr), 1483 (extloadf32 node:$ptr)]>; 1484def any_extloadf64 : PatFrags<(ops node:$ptr), 1485 [(strict_extloadf64 node:$ptr), 1486 (extloadf64 node:$ptr)]>; 1487def any_fp_to_sint : PatFrags<(ops node:$src), 1488 [(strict_fp_to_sint node:$src), 1489 (fp_to_sint node:$src)]>; 1490def any_fp_to_uint : PatFrags<(ops node:$src), 1491 [(strict_fp_to_uint node:$src), 1492 (fp_to_uint node:$src)]>; 1493def any_sint_to_fp : PatFrags<(ops node:$src), 1494 [(strict_sint_to_fp node:$src), 1495 (sint_to_fp node:$src)]>; 1496def any_uint_to_fp : PatFrags<(ops node:$src), 1497 [(strict_uint_to_fp node:$src), 1498 (uint_to_fp node:$src)]>; 1499def any_fsetcc : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1500 [(strict_fsetcc node:$lhs, node:$rhs, node:$pred), 1501 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1502def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1503 [(strict_fsetccs node:$lhs, node:$rhs, node:$pred), 1504 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1505 1506multiclass binary_atomic_op_ord { 1507 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1508 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1509 let IsAtomic = true; 1510 let IsAtomicOrderingMonotonic = true; 1511 } 1512 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1513 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1514 let IsAtomic = true; 1515 let IsAtomicOrderingAcquire = true; 1516 } 1517 def NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1518 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1519 let IsAtomic = true; 1520 let IsAtomicOrderingRelease = true; 1521 } 1522 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1523 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1524 let IsAtomic = true; 1525 let IsAtomicOrderingAcquireRelease = true; 1526 } 1527 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1528 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1529 let IsAtomic = true; 1530 let IsAtomicOrderingSequentiallyConsistent = true; 1531 } 1532} 1533 1534multiclass ternary_atomic_op_ord { 1535 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1536 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1537 let IsAtomic = true; 1538 let IsAtomicOrderingMonotonic = true; 1539 } 1540 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1541 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1542 let IsAtomic = true; 1543 let IsAtomicOrderingAcquire = true; 1544 } 1545 def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1546 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1547 let IsAtomic = true; 1548 let IsAtomicOrderingRelease = true; 1549 } 1550 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1551 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1552 let IsAtomic = true; 1553 let IsAtomicOrderingAcquireRelease = true; 1554 } 1555 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1556 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1557 let IsAtomic = true; 1558 let IsAtomicOrderingSequentiallyConsistent = true; 1559 } 1560} 1561 1562multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> { 1563 def _8 : PatFrag<(ops node:$ptr, node:$val), 1564 (atomic_op node:$ptr, node:$val)> { 1565 let IsAtomic = true; 1566 let MemoryVT = !if(IsInt, i8, ?); 1567 } 1568 def _16 : PatFrag<(ops node:$ptr, node:$val), 1569 (atomic_op node:$ptr, node:$val)> { 1570 let IsAtomic = true; 1571 let MemoryVT = !if(IsInt, i16, f16); 1572 } 1573 def _32 : PatFrag<(ops node:$ptr, node:$val), 1574 (atomic_op node:$ptr, node:$val)> { 1575 let IsAtomic = true; 1576 let MemoryVT = !if(IsInt, i32, f32); 1577 } 1578 def _64 : PatFrag<(ops node:$ptr, node:$val), 1579 (atomic_op node:$ptr, node:$val)> { 1580 let IsAtomic = true; 1581 let MemoryVT = !if(IsInt, i64, f64); 1582 } 1583 1584 defm NAME#_8 : binary_atomic_op_ord; 1585 defm NAME#_16 : binary_atomic_op_ord; 1586 defm NAME#_32 : binary_atomic_op_ord; 1587 defm NAME#_64 : binary_atomic_op_ord; 1588} 1589 1590multiclass ternary_atomic_op<SDNode atomic_op> { 1591 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1592 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1593 let IsAtomic = true; 1594 let MemoryVT = i8; 1595 } 1596 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1597 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1598 let IsAtomic = true; 1599 let MemoryVT = i16; 1600 } 1601 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1602 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1603 let IsAtomic = true; 1604 let MemoryVT = i32; 1605 } 1606 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1607 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1608 let IsAtomic = true; 1609 let MemoryVT = i64; 1610 } 1611 1612 defm NAME#_8 : ternary_atomic_op_ord; 1613 defm NAME#_16 : ternary_atomic_op_ord; 1614 defm NAME#_32 : ternary_atomic_op_ord; 1615 defm NAME#_64 : ternary_atomic_op_ord; 1616} 1617 1618defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1619defm atomic_swap : binary_atomic_op<atomic_swap>; 1620defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1621defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1622defm atomic_load_clr : binary_atomic_op<atomic_load_clr>; 1623defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1624defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1625defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1626defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1627defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1628defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1629defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1630defm atomic_store : binary_atomic_op<atomic_store>; 1631defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1632 1633/// Atomic load which zeroes the excess high bits. 1634def atomic_load_zext : 1635 PatFrag<(ops node:$ptr), (atomic_load node:$ptr)> { 1636 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1637 let IsZeroExtLoad = true; 1638} 1639 1640/// Atomic load which sign extends the excess high bits. 1641def atomic_load_sext : 1642 PatFrag<(ops node:$ptr), (atomic_load node:$ptr)> { 1643 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1644 let IsSignExtLoad = true; 1645} 1646 1647def atomic_load_8 : 1648 PatFrag<(ops node:$ptr), 1649 (atomic_load node:$ptr)> { 1650 let IsAtomic = true; 1651 let MemoryVT = i8; 1652} 1653 1654def atomic_load_16 : 1655 PatFrag<(ops node:$ptr), 1656 (atomic_load node:$ptr)> { 1657 let IsAtomic = true; 1658 let MemoryVT = i16; 1659} 1660 1661def atomic_load_32 : 1662 PatFrag<(ops node:$ptr), 1663 (atomic_load node:$ptr)> { 1664 let IsAtomic = true; 1665 let MemoryVT = i32; 1666} 1667def atomic_load_64 : 1668 PatFrag<(ops node:$ptr), 1669 (atomic_load node:$ptr)> { 1670 let IsAtomic = true; 1671 let MemoryVT = i64; 1672} 1673 1674def atomic_load_zext_8 : 1675 PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> { 1676 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1677 let MemoryVT = i8; 1678} 1679 1680def atomic_load_zext_16 : 1681 PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> { 1682 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1683 let MemoryVT = i16; 1684} 1685 1686def atomic_load_sext_8 : 1687 PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> { 1688 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1689 let MemoryVT = i8; 1690} 1691 1692def atomic_load_sext_16 : 1693 PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> { 1694 let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic? 1695 let MemoryVT = i16; 1696} 1697 1698// Atomic load which zeroes or anyextends the high bits. 1699def atomic_load_az_8 : PatFrags<(ops node:$op), 1700 [(atomic_load_8 node:$op), 1701 (atomic_load_zext_8 node:$op)]>; 1702 1703// Atomic load which zeroes or anyextends the high bits. 1704def atomic_load_az_16 : PatFrags<(ops node:$op), 1705 [(atomic_load_16 node:$op), 1706 (atomic_load_zext_16 node:$op)]>; 1707 1708def nonext_masked_gather : 1709 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1710 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1711 return cast<MaskedGatherSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 1712}]>; 1713 1714// Any extending masked gather fragments. 1715def ext_masked_gather_i8 : 1716 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1717 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1718 auto MGN = cast<MaskedGatherSDNode>(N); 1719 return MGN->getExtensionType() == ISD::EXTLOAD && 1720 MGN->getMemoryVT().getScalarType() == MVT::i8; 1721}]>; 1722def ext_masked_gather_i16 : 1723 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1724 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1725 auto MGN = cast<MaskedGatherSDNode>(N); 1726 return MGN->getExtensionType() == ISD::EXTLOAD && 1727 MGN->getMemoryVT().getScalarType() == MVT::i16; 1728}]>; 1729def ext_masked_gather_i32 : 1730 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1731 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1732 auto MGN = cast<MaskedGatherSDNode>(N); 1733 return MGN->getExtensionType() == ISD::EXTLOAD && 1734 MGN->getMemoryVT().getScalarType() == MVT::i32; 1735}]>; 1736 1737// Sign extending masked gather fragments. 1738def sext_masked_gather_i8 : 1739 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1740 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1741 auto MGN = cast<MaskedGatherSDNode>(N); 1742 return MGN->getExtensionType() == ISD::SEXTLOAD && 1743 MGN->getMemoryVT().getScalarType() == MVT::i8; 1744}]>; 1745def sext_masked_gather_i16 : 1746 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1747 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1748 auto MGN = cast<MaskedGatherSDNode>(N); 1749 return MGN->getExtensionType() == ISD::SEXTLOAD && 1750 MGN->getMemoryVT().getScalarType() == MVT::i16; 1751}]>; 1752def sext_masked_gather_i32 : 1753 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1754 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1755 auto MGN = cast<MaskedGatherSDNode>(N); 1756 return MGN->getExtensionType() == ISD::SEXTLOAD && 1757 MGN->getMemoryVT().getScalarType() == MVT::i32; 1758}]>; 1759 1760// Zero extending masked gather fragments. 1761def zext_masked_gather_i8 : 1762 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1763 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1764 auto MGN = cast<MaskedGatherSDNode>(N); 1765 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1766 MGN->getMemoryVT().getScalarType() == MVT::i8; 1767}]>; 1768def zext_masked_gather_i16 : 1769 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1770 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1771 auto MGN = cast<MaskedGatherSDNode>(N); 1772 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1773 MGN->getMemoryVT().getScalarType() == MVT::i16; 1774}]>; 1775def zext_masked_gather_i32 : 1776 PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1777 (masked_gather node:$def, node:$pred, node:$ptr, node:$idx), [{ 1778 auto MGN = cast<MaskedGatherSDNode>(N); 1779 return MGN->getExtensionType() == ISD::ZEXTLOAD && 1780 MGN->getMemoryVT().getScalarType() == MVT::i32; 1781}]>; 1782 1783// Any/Zero extending masked gather fragments. 1784def azext_masked_gather_i8 : 1785 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1786 [(ext_masked_gather_i8 node:$def, node:$pred, node:$ptr, node:$idx), 1787 (zext_masked_gather_i8 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1788def azext_masked_gather_i16 : 1789 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1790 [(ext_masked_gather_i16 node:$def, node:$pred, node:$ptr, node:$idx), 1791 (zext_masked_gather_i16 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1792def azext_masked_gather_i32 : 1793 PatFrags<(ops node:$def, node:$pred, node:$ptr, node:$idx), 1794 [(ext_masked_gather_i32 node:$def, node:$pred, node:$ptr, node:$idx), 1795 (zext_masked_gather_i32 node:$def, node:$pred, node:$ptr, node:$idx)]>; 1796 1797def nontrunc_masked_scatter : 1798 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1799 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1800 return !cast<MaskedScatterSDNode>(N)->isTruncatingStore(); 1801}]>; 1802 1803// Truncating masked scatter fragments. 1804def trunc_masked_scatter_i8 : 1805 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1806 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1807 auto MSN = cast<MaskedScatterSDNode>(N); 1808 return MSN->isTruncatingStore() && 1809 MSN->getMemoryVT().getScalarType() == MVT::i8; 1810}]>; 1811def trunc_masked_scatter_i16 : 1812 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1813 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1814 auto MSN = cast<MaskedScatterSDNode>(N); 1815 return MSN->isTruncatingStore() && 1816 MSN->getMemoryVT().getScalarType() == MVT::i16; 1817}]>; 1818def trunc_masked_scatter_i32 : 1819 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx), 1820 (masked_scatter node:$val, node:$pred, node:$ptr, node:$idx), [{ 1821 auto MSN = cast<MaskedScatterSDNode>(N); 1822 return MSN->isTruncatingStore() && 1823 MSN->getMemoryVT().getScalarType() == MVT::i32; 1824}]>; 1825 1826//===----------------------------------------------------------------------===// 1827// Selection DAG Pattern Support. 1828// 1829// Patterns are what are actually matched against by the target-flavored 1830// instruction selection DAG. Instructions defined by the target implicitly 1831// define patterns in most cases, but patterns can also be explicitly added when 1832// an operation is defined by a sequence of instructions (e.g. loading a large 1833// immediate value on RISC targets that do not support immediates as large as 1834// their GPRs). 1835// 1836 1837class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1838 dag PatternToMatch = patternToMatch; 1839 list<dag> ResultInstrs = resultInstrs; 1840 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1841 int AddedComplexity = 0; // See class Instruction in Target.td. 1842} 1843 1844// Pat - A simple (but common) form of a pattern, which produces a simple result 1845// not needing a full list. 1846class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1847 1848//===----------------------------------------------------------------------===// 1849// Complex pattern definitions. 1850// 1851 1852// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1853// in C++. NumOperands is the number of operands returned by the select function; 1854// SelectFunc is the name of the function used to pattern match the max. pattern; 1855// RootNodes are the list of possible root nodes of the sub-dags to match. 1856// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1857// 1858class ComplexPattern<ValueType ty, int numops, string fn, 1859 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1860 int complexity = -1> { 1861 ValueType Ty = ty; 1862 int NumOperands = numops; 1863 string SelectFunc = fn; 1864 list<SDNode> RootNodes = roots; 1865 list<SDNodeProperty> Properties = props; 1866 int Complexity = complexity; 1867} 1868