1//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for AArch64 architecture. 10// 11//===----------------------------------------------------------------------===// 12 13/// CCIfBigEndian - Match only if we're in big endian mode. 14class CCIfBigEndian<CCAction A> : 15 CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; 16 17class CCIfILP32<CCAction A> : 18 CCIf<"State.getMachineFunction().getDataLayout().getPointerSize() == 4", A>; 19 20 21//===----------------------------------------------------------------------===// 22// ARM AAPCS64 Calling Convention 23//===----------------------------------------------------------------------===// 24 25defvar AArch64_Common = [ 26 CCIfType<[iPTR], CCBitConvertToType<i64>>, 27 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 28 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 29 30 // Big endian vectors must be passed as if they were 1-element vectors so that 31 // their lanes are in a consistent order. 32 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 33 CCBitConvertToType<f64>>>, 34 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 35 CCBitConvertToType<f128>>>, 36 37 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter. 38 // However, on windows, in some circumstances, the SRet is passed in X0 or X1 39 // instead. The presence of the inreg attribute indicates that SRet is 40 // passed in the alternative register (X0 or X1), not X8: 41 // - X0 for non-instance methods. 42 // - X1 for instance methods. 43 44 // The "sret" attribute identifies indirect returns. 45 // The "inreg" attribute identifies non-aggregate types. 46 // The position of the "sret" attribute identifies instance/non-instance 47 // methods. 48 // "sret" on argument 0 means non-instance methods. 49 // "sret" on argument 1 means instance methods. 50 51 CCIfInReg<CCIfType<[i64], 52 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>, 53 54 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 55 56 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 57 // slot is 64-bit. 58 CCIfByVal<CCPassByVal<8, 8>>, 59 60 // Pass SwiftSelf in a callee saved register. 61 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>, 62 63 // A SwiftError is passed in X21. 64 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 65 66 // Pass SwiftAsync in an otherwise callee saved register so that it will be 67 // preserved for normal function calls. 68 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>, 69 70 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 71 72 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 73 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 74 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 75 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 76 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 77 CCPassIndirect<i64>>, 78 79 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 80 CCAssignToReg<[P0, P1, P2, P3]>>, 81 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 82 CCPassIndirect<i64>>, 83 84 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 85 // up to eight each of GPR and FPR. 86 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 87 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 88 // i128 is split to two i64s, we can't fit half to register X7. 89 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6], 90 [X0, X1, X3, X5]>>>, 91 92 // i128 is split to two i64s, and its stack alignment is 16 bytes. 93 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 94 95 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 96 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 97 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 98 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 99 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 100 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 101 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 102 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 103 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 104 105 // If more than will fit in registers, pass them on the stack instead. 106 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>, 107 CCIfType<[i32, f32], CCAssignToStack<8, 8>>, 108 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 109 CCAssignToStack<8, 8>>, 110 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 111 CCAssignToStack<16, 16>> 112]; 113 114let Entry = 1 in 115def CC_AArch64_AAPCS : CallingConv<!listconcat( 116 // The 'nest' parameter, if any, is passed in X18. 117 // Darwin and Windows use X18 as the platform register and hence 'nest' isn't 118 // currently supported there. 119 [CCIfNest<CCAssignToReg<[X18]>>], 120 AArch64_Common 121)>; 122 123let Entry = 1 in 124def RetCC_AArch64_AAPCS : CallingConv<[ 125 CCIfType<[iPTR], CCBitConvertToType<i64>>, 126 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 127 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 128 129 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 130 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 131 132 // Big endian vectors must be passed as if they were 1-element vectors so that 133 // their lanes are in a consistent order. 134 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 135 CCBitConvertToType<f64>>>, 136 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 137 CCBitConvertToType<f128>>>, 138 139 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 140 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 141 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 142 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 143 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 144 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 145 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 146 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 147 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 148 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 149 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 150 151 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 152 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 153 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 154 155 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 156 CCAssignToReg<[P0, P1, P2, P3]>> 157]>; 158 159let Entry = 1 in 160def CC_AArch64_Win64PCS : CallingConv<AArch64_Common>; 161 162// Vararg functions on windows pass floats in integer registers 163let Entry = 1 in 164def CC_AArch64_Win64_VarArg : CallingConv<[ 165 CCIfType<[f16, bf16], CCBitConvertToType<i16>>, 166 CCIfType<[f32], CCBitConvertToType<i32>>, 167 CCIfType<[f64], CCBitConvertToType<i64>>, 168 CCDelegateTo<CC_AArch64_Win64PCS> 169]>; 170 171// Vararg functions on Arm64EC ABI use a different convention, using 172// a stack layout compatible with the x64 calling convention. 173let Entry = 1 in 174def CC_AArch64_Arm64EC_VarArg : CallingConv<[ 175 // Convert small floating-point values to integer. 176 CCIfType<[f16, bf16], CCBitConvertToType<i16>>, 177 CCIfType<[f32], CCBitConvertToType<i32>>, 178 CCIfType<[f64, v1f64, v1i64, v2f32, v2i32, v4i16, v4f16, v4bf16, v8i8, iPTR], 179 CCBitConvertToType<i64>>, 180 181 // Larger floating-point/vector values are passed indirectly. 182 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 183 CCPassIndirect<i64>>, 184 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 185 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 186 CCPassIndirect<i64>>, 187 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 188 CCPassIndirect<i64>>, 189 190 // Handle SRet. See comment in CC_AArch64_AAPCS. 191 CCIfInReg<CCIfType<[i64], 192 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>, 193 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 194 195 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 196 // slot is 64-bit. (Shouldn't normally come up; the Microsoft ABI doesn't 197 // use byval.) 198 CCIfByVal<CCPassByVal<8, 8>>, 199 200 // Promote small integers to i32 201 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 202 203 // Pass first four arguments in x0-x3. 204 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3]>>, 205 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3]>>, 206 207 // Put remaining arguments on stack. 208 CCIfType<[i32, i64], CCAssignToStack<8, 8>>, 209]>; 210 211// Windows Control Flow Guard checks take a single argument (the target function 212// address) and have no return value. 213let Entry = 1 in 214def CC_AArch64_Win64_CFGuard_Check : CallingConv<[ 215 CCIfType<[i64], CCAssignToReg<[X15]>> 216]>; 217 218 219// Darwin uses a calling convention which differs in only two ways 220// from the standard one at this level: 221// + i128s (i.e. split i64s) don't need even registers. 222// + Stack slots are sized as needed rather than being at least 64-bit. 223let Entry = 1 in 224def CC_AArch64_DarwinPCS : CallingConv<[ 225 CCIfType<[iPTR], CCBitConvertToType<i64>>, 226 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 227 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 228 229 // An SRet is passed in X8, not X0 like a normal pointer parameter. 230 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 231 232 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 233 // slot is 64-bit. 234 CCIfByVal<CCPassByVal<8, 8>>, 235 236 // Pass SwiftSelf in a callee saved register. 237 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>, 238 239 // A SwiftError is passed in X21. 240 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 241 242 // Pass SwiftAsync in an otherwise callee saved register so that it will be 243 // preserved for normal function calls. 244 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>, 245 246 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 247 248 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 249 // up to eight each of GPR and FPR. 250 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 251 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 252 // i128 is split to two i64s, we can't fit half to register X7. 253 CCIfType<[i64], 254 CCIfSplit<CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6]>>>, 255 // i128 is split to two i64s, and its stack alignment is 16 bytes. 256 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 257 258 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 259 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 260 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 261 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 262 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 263 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 264 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 265 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 266 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 267 268 // If more than will fit in registers, pass them on the stack instead. 269 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>, 270 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16", 271 CCAssignToStack<2, 2>>, 272 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 273 274 // Re-demote pointers to 32-bits so we don't end up storing 64-bit 275 // values and clobbering neighbouring stack locations. Not very pretty. 276 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 277 CCIfPtr<CCIfILP32<CCAssignToStack<4, 4>>>, 278 279 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 280 CCAssignToStack<8, 8>>, 281 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 282 CCAssignToStack<16, 16>> 283]>; 284 285let Entry = 1 in 286def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ 287 CCIfType<[iPTR], CCBitConvertToType<i64>>, 288 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 289 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 290 291 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>, 292 293 // Handle all scalar types as either i64 or f64. 294 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 295 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>, 296 297 // Everything is on the stack. 298 // i128 is split to two i64s, and its stack alignment is 16 bytes. 299 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 300 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 301 CCAssignToStack<8, 8>>, 302 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 303 CCAssignToStack<16, 16>> 304]>; 305 306// In the ILP32 world, the minimum stack slot size is 4 bytes. Otherwise the 307// same as the normal Darwin VarArgs handling. 308let Entry = 1 in 309def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[ 310 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 311 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 312 313 // Handle all scalar types as either i32 or f32. 314 CCIfType<[i8, i16], CCPromoteToType<i32>>, 315 CCIfType<[f16, bf16], CCPromoteToType<f32>>, 316 317 // Everything is on the stack. 318 // i128 is split to two i64s, and its stack alignment is 16 bytes. 319 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 320 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 321 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 322 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 323 CCAssignToStack<8, 8>>, 324 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 325 CCAssignToStack<16, 16>> 326]>; 327 328//===----------------------------------------------------------------------===// 329// ARM64 Calling Convention for GHC 330//===----------------------------------------------------------------------===// 331 332// This calling convention is specific to the Glasgow Haskell Compiler. 333// The only documentation is the GHC source code, specifically the C header 334// file: 335// 336// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs.h 337// 338// which defines the registers for the Spineless Tagless G-Machine (STG) that 339// GHC uses to implement lazy evaluation. The generic STG machine has a set of 340// registers which are mapped to appropriate set of architecture specific 341// registers for each CPU architecture. 342// 343// The STG Machine is documented here: 344// 345// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode 346// 347// The AArch64 register mapping is defined in the following header file: 348// 349// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm64.h 350// 351 352let Entry = 1 in 353def CC_AArch64_GHC : CallingConv<[ 354 CCIfType<[iPTR], CCBitConvertToType<i64>>, 355 356 // Handle all vector types as either f64 or v2f64. 357 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 358 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>, 359 360 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 361 CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>, 362 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>, 363 364 // Promote i8/i16/i32 arguments to i64. 365 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 366 367 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 368 CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>> 369]>; 370 371// The order of the callee-saves in this file is important, because the 372// FrameLowering code will use this order to determine the layout the 373// callee-save area in the stack frame. As can be observed below, Darwin 374// requires the frame-record (LR, FP) to be at the top the callee-save area, 375// whereas for other platforms they are at the bottom. 376 377// FIXME: LR is only callee-saved in the sense that *we* preserve it and are 378// presumably a callee to someone. External functions may not do so, but this 379// is currently safe since BL has LR as an implicit-def and what happens after a 380// tail call doesn't matter. 381// 382// It would be better to model its preservation semantics properly (create a 383// vreg on entry, use it in RET & tail call generation; make that vreg def if we 384// end up saving LR as part of a call frame). Watch this space... 385def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 386 X25, X26, X27, X28, LR, FP, 387 D8, D9, D10, D11, 388 D12, D13, D14, D15)>; 389 390// A variant for treating X18 as callee saved, when interfacing with 391// code that needs X18 to be preserved. 392def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>; 393 394// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x. 395// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs, 396// and not (LR,FP) pairs. 397def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 398 X25, X26, X27, X28, FP, LR, 399 D8, D9, D10, D11, 400 D12, D13, D14, D15)>; 401 402def CSR_Win_AArch64_AAPCS_SwiftError 403 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X21)>; 404 405def CSR_Win_AArch64_AAPCS_SwiftTail 406 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X20, X22)>; 407 408// The Control Flow Guard check call uses a custom calling convention that also 409// preserves X0-X8 and Q0-Q7. 410def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, 411 (sequence "X%u", 0, 8), 412 (sequence "Q%u", 0, 7))>; 413 414// AArch64 PCS for vector functions (VPCS) 415// must (additionally) preserve full Q8-Q23 registers 416def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 417 X25, X26, X27, X28, LR, FP, 418 (sequence "Q%u", 8, 23))>; 419 420// Functions taking SVE arguments or returning an SVE type 421// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15 422def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23), 423 (sequence "P%u", 4, 15), 424 X19, X20, X21, X22, X23, X24, 425 X25, X26, X27, X28, LR, FP)>; 426 427// SME ABI support routines such as __arm_tpidr2_save/restore preserve most registers. 428def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 429 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31), 430 (sequence "P%u", 0, 15), 431 (sequence "X%u", 0, 13), 432 (sequence "X%u",19, 28), 433 LR, FP)>; 434 435// SME ABI support routines __arm_sme_state preserves most registers. 436def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 437 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31), 438 (sequence "P%u", 0, 15), 439 (sequence "X%u", 2, 15), 440 (sequence "X%u",19, 28), 441 LR, FP)>; 442 443// The SMSTART/SMSTOP instructions preserve only GPR registers. 444def CSR_AArch64_SMStartStop : CalleeSavedRegs<(add (sequence "X%u", 0, 28), 445 LR, FP)>; 446 447def CSR_AArch64_AAPCS_SwiftTail 448 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X20, X22)>; 449 450// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since 451// 'this' and the pointer return value are both passed in X0 in these cases, 452// this can be partially modelled by treating X0 as a callee-saved register; 453// only the resulting RegMask is used; the SaveList is ignored 454// 455// (For generic ARM 64-bit ABI code, clang will not generate constructors or 456// destructors with 'this' returns, so this RegMask will not be used in that 457// case) 458def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>; 459 460def CSR_AArch64_AAPCS_SwiftError 461 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>; 462 463// The ELF stub used for TLS-descriptor access saves every feasible 464// register. Only X0 and LR are clobbered. 465def CSR_AArch64_TLS_ELF 466 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP, 467 (sequence "Q%u", 0, 31))>; 468 469def CSR_AArch64_AllRegs 470 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP, 471 (sequence "X%u", 0, 28), FP, LR, SP, 472 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31), 473 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31), 474 (sequence "Q%u", 0, 31))>; 475 476def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>; 477 478def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS, 479 (sequence "X%u", 9, 15))>; 480 481def CSR_AArch64_RT_AllRegs : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, 482 (sequence "Q%u", 8, 31))>; 483 484def CSR_AArch64_StackProbe_Windows 485 : CalleeSavedRegs<(add (sequence "X%u", 0, 15), 486 (sequence "X%u", 18, 28), FP, SP, 487 (sequence "Q%u", 0, 31))>; 488 489// Darwin variants of AAPCS. 490// Darwin puts the frame-record at the top of the callee-save area. 491def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22, 492 X23, X24, X25, X26, X27, X28, 493 D8, D9, D10, D11, 494 D12, D13, D14, D15)>; 495 496def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, 497 X22, X23, X24, X25, X26, X27, 498 X28, (sequence "Q%u", 8, 23))>; 499 500// For Windows calling convention on a non-windows OS, where X18 is treated 501// as reserved, back up X18 when entering non-windows code (marked with the 502// Windows calling convention) and restore when returning regardless of 503// whether the individual function uses it - it might call other functions 504// that clobber it. 505def CSR_Darwin_AArch64_AAPCS_Win64 506 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X18)>; 507 508def CSR_Darwin_AArch64_AAPCS_ThisReturn 509 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X0)>; 510 511def CSR_Darwin_AArch64_AAPCS_SwiftError 512 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>; 513 514def CSR_Darwin_AArch64_AAPCS_SwiftTail 515 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X20, X22)>; 516 517// The function used by Darwin to obtain the address of a thread-local variable 518// guarantees more than a normal AAPCS function. x16 and x17 are used on the 519// fast path for calculation, but other registers except X0 (argument/return) 520// and LR (it is a call, after all) are preserved. 521def CSR_Darwin_AArch64_TLS 522 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17), 523 FP, 524 (sequence "Q%u", 0, 31))>; 525 526// We can only handle a register pair with adjacent registers, the register pair 527// should belong to the same class as well. Since the access function on the 528// fast path calls a function that follows CSR_Darwin_AArch64_TLS, 529// CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS. 530def CSR_Darwin_AArch64_CXX_TLS 531 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, 532 (sub (sequence "X%u", 1, 28), X9, X15, X16, X17, X18, X19), 533 (sequence "D%u", 0, 31))>; 534 535// CSRs that are handled by prologue, epilogue. 536def CSR_Darwin_AArch64_CXX_TLS_PE 537 : CalleeSavedRegs<(add LR, FP)>; 538 539// CSRs that are handled explicitly via copies. 540def CSR_Darwin_AArch64_CXX_TLS_ViaCopy 541 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_CXX_TLS, LR, FP)>; 542 543def CSR_Darwin_AArch64_RT_MostRegs 544 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, (sequence "X%u", 9, 15))>; 545 546def CSR_Darwin_AArch64_RT_AllRegs 547 : CalleeSavedRegs<(add CSR_Darwin_AArch64_RT_MostRegs, (sequence "Q%u", 8, 31))>; 548 549// Variants of the standard calling conventions for shadow call stack. 550// These all preserve x18 in addition to any other registers. 551def CSR_AArch64_NoRegs_SCS 552 : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>; 553def CSR_AArch64_AllRegs_SCS 554 : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>; 555def CSR_AArch64_AAPCS_SwiftError_SCS 556 : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>; 557def CSR_AArch64_RT_MostRegs_SCS 558 : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>; 559def CSR_AArch64_RT_AllRegs_SCS 560 : CalleeSavedRegs<(add CSR_AArch64_RT_AllRegs, X18)>; 561def CSR_AArch64_AAVPCS_SCS 562 : CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>; 563def CSR_AArch64_SVE_AAPCS_SCS 564 : CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>; 565def CSR_AArch64_AAPCS_SCS 566 : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>; 567