1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
15 
16 #define GET_REGINFO_HEADER
17 #include "AArch64GenRegisterInfo.inc"
18 
19 namespace llvm {
20 
21 class MachineFunction;
22 class RegScavenger;
23 class TargetRegisterClass;
24 class Triple;
25 
26 class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
27   const Triple &TT;
28 
29 public:
30   AArch64RegisterInfo(const Triple &TT);
31 
32   // FIXME: This should be tablegen'd like getDwarfRegNum is
getSEHRegNum(unsigned i)33   int getSEHRegNum(unsigned i) const {
34     return getEncodingValue(i);
35   }
36 
37   bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38   bool isStrictlyReservedReg(const MachineFunction &MF, MCRegister Reg) const;
39   bool isAnyArgRegReserved(const MachineFunction &MF) const;
40   void emitReservedArgRegCallError(const MachineFunction &MF) const;
41 
42   void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
43   void UpdateCustomCallPreservedMask(MachineFunction &MF,
44                                      const uint32_t **Mask) const;
45 
46   /// Code Generation virtual methods...
47   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
48   const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
49   const MCPhysReg *
50   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
51   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
52                                        CallingConv::ID) const override;
53   const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
54                                              CallingConv::ID) const;
55 
getCSRFirstUseCost()56   unsigned getCSRFirstUseCost() const override {
57     // The cost will be compared against BlockFrequency where entry has the
58     // value of 1 << 14. A value of 5 will choose to spill or split really
59     // cold path instead of using a callee-saved register.
60     return 5;
61   }
62 
63   const TargetRegisterClass *
64   getSubClassWithSubReg(const TargetRegisterClass *RC,
65                         unsigned Idx) const override;
66 
67   // Calls involved in thread-local variable lookup save more registers than
68   // normal calls, so they need a different mask to represent this.
69   const uint32_t *getTLSCallPreservedMask() const;
70 
71   const uint32_t *getSMStartStopCallPreservedMask() const;
72   const uint32_t *SMEABISupportRoutinesCallPreservedMaskFromX0() const;
73 
74   // Funclets on ARM64 Windows don't preserve any registers.
75   const uint32_t *getNoPreservedMask() const override;
76 
77   // Unwinders may not preserve all Neon and SVE registers.
78   const uint32_t *
79   getCustomEHPadPreservedMask(const MachineFunction &MF) const override;
80 
81   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
82   /// case that 'returned' is on an i64 first argument if the calling convention
83   /// is one that can (partially) model this attribute with a preserved mask
84   /// (i.e. it is a calling convention that uses the same register for the first
85   /// i64 argument and an i64 return value)
86   ///
87   /// Should return NULL in the case that the calling convention does not have
88   /// this property
89   const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
90                                              CallingConv::ID) const;
91 
92   /// Stack probing calls preserve different CSRs to the normal CC.
93   const uint32_t *getWindowsStackProbePreservedMask() const;
94 
95   BitVector getStrictlyReservedRegs(const MachineFunction &MF) const;
96   BitVector getReservedRegs(const MachineFunction &MF) const override;
97   std::optional<std::string>
98   explainReservedReg(const MachineFunction &MF,
99                      MCRegister PhysReg) const override;
100   bool isAsmClobberable(const MachineFunction &MF,
101                        MCRegister PhysReg) const override;
102   const TargetRegisterClass *
103   getPointerRegClass(const MachineFunction &MF,
104                      unsigned Kind = 0) const override;
105   const TargetRegisterClass *
106   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
107 
108   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
109   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
110   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
111 
112   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
113   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
114                           int64_t Offset) const override;
115   Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
116                                         int64_t Offset) const override;
117   void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
118                          int64_t Offset) const override;
119   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
120                            unsigned FIOperandNum,
121                            RegScavenger *RS = nullptr) const override;
122   bool cannotEliminateFrame(const MachineFunction &MF) const;
123 
124   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
125   bool hasBasePointer(const MachineFunction &MF) const;
126   unsigned getBaseRegister() const;
127 
128   bool isArgumentRegister(const MachineFunction &MF,
129                           MCRegister Reg) const override;
130 
131   // Debug information queries.
132   Register getFrameRegister(const MachineFunction &MF) const override;
133 
134   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
135                                MachineFunction &MF) const override;
136 
137   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
138   bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
139 
140   /// SrcRC and DstRC will be morphed into NewRC if this returns true
141   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
142                       unsigned SubReg, const TargetRegisterClass *DstRC,
143                       unsigned DstSubReg, const TargetRegisterClass *NewRC,
144                       LiveIntervals &LIS) const override;
145 
146   void getOffsetOpcodes(const StackOffset &Offset,
147                         SmallVectorImpl<uint64_t> &Ops) const override;
148 };
149 
150 } // end namespace llvm
151 
152 #endif
153