1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the AArch64 implementation of the MRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H 14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H 15 16 #define GET_REGINFO_HEADER 17 #include "AArch64GenRegisterInfo.inc" 18 19 namespace llvm { 20 21 class MachineFunction; 22 class RegScavenger; 23 class TargetRegisterClass; 24 class Triple; 25 26 class AArch64RegisterInfo final : public AArch64GenRegisterInfo { 27 const Triple &TT; 28 29 public: 30 AArch64RegisterInfo(const Triple &TT); 31 32 // FIXME: This should be tablegen'd like getDwarfRegNum is 33 int getSEHRegNum(unsigned i) const { 34 return getEncodingValue(i); 35 } 36 37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const; 38 bool isAnyArgRegReserved(const MachineFunction &MF) const; 39 void emitReservedArgRegCallError(const MachineFunction &MF) const; 40 41 void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const; 42 void UpdateCustomCallPreservedMask(MachineFunction &MF, 43 const uint32_t **Mask) const; 44 45 /// Code Generation virtual methods... 46 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 47 const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const; 48 const MCPhysReg * 49 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 50 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 51 CallingConv::ID) const override; 52 const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF, 53 CallingConv::ID) const; 54 55 unsigned getCSRFirstUseCost() const override { 56 // The cost will be compared against BlockFrequency where entry has the 57 // value of 1 << 14. A value of 5 will choose to spill or split really 58 // cold path instead of using a callee-saved register. 59 return 5; 60 } 61 62 const TargetRegisterClass * 63 getSubClassWithSubReg(const TargetRegisterClass *RC, 64 unsigned Idx) const override; 65 66 // Calls involved in thread-local variable lookup save more registers than 67 // normal calls, so they need a different mask to represent this. 68 const uint32_t *getTLSCallPreservedMask() const; 69 70 // Funclets on ARM64 Windows don't preserve any registers. 71 const uint32_t *getNoPreservedMask() const override; 72 73 // Unwinders may not preserve all Neon and SVE registers. 74 const uint32_t * 75 getCustomEHPadPreservedMask(const MachineFunction &MF) const override; 76 77 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 78 /// case that 'returned' is on an i64 first argument if the calling convention 79 /// is one that can (partially) model this attribute with a preserved mask 80 /// (i.e. it is a calling convention that uses the same register for the first 81 /// i64 argument and an i64 return value) 82 /// 83 /// Should return NULL in the case that the calling convention does not have 84 /// this property 85 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF, 86 CallingConv::ID) const; 87 88 /// Stack probing calls preserve different CSRs to the normal CC. 89 const uint32_t *getWindowsStackProbePreservedMask() const; 90 91 BitVector getReservedRegs(const MachineFunction &MF) const override; 92 bool isAsmClobberable(const MachineFunction &MF, 93 MCRegister PhysReg) const override; 94 bool isConstantPhysReg(MCRegister PhysReg) const override; 95 const TargetRegisterClass * 96 getPointerRegClass(const MachineFunction &MF, 97 unsigned Kind = 0) const override; 98 const TargetRegisterClass * 99 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 100 101 bool requiresRegisterScavenging(const MachineFunction &MF) const override; 102 bool useFPForScavengingIndex(const MachineFunction &MF) const override; 103 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 104 105 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 106 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 107 int64_t Offset) const override; 108 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, 109 int64_t Offset) const override; 110 void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 111 int64_t Offset) const override; 112 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 113 unsigned FIOperandNum, 114 RegScavenger *RS = nullptr) const override; 115 bool cannotEliminateFrame(const MachineFunction &MF) const; 116 117 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 118 bool hasBasePointer(const MachineFunction &MF) const; 119 unsigned getBaseRegister() const; 120 121 bool isArgumentRegister(const MachineFunction &MF, 122 MCRegister Reg) const override; 123 124 // Debug information queries. 125 Register getFrameRegister(const MachineFunction &MF) const override; 126 127 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 128 MachineFunction &MF) const override; 129 130 unsigned getLocalAddressRegister(const MachineFunction &MF) const; 131 bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const; 132 133 /// SrcRC and DstRC will be morphed into NewRC if this returns true 134 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, 135 unsigned SubReg, const TargetRegisterClass *DstRC, 136 unsigned DstSubReg, const TargetRegisterClass *NewRC, 137 LiveIntervals &LIS) const override; 138 139 void getOffsetOpcodes(const StackOffset &Offset, 140 SmallVectorImpl<uint64_t> &Ops) const override; 141 }; 142 143 } // end namespace llvm 144 145 #endif 146