1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AArch64MCTargetDesc.h"
14 #include "AArch64ELFStreamer.h"
15 #include "AArch64MCAsmInfo.h"
16 #include "AArch64WinCOFFStreamer.h"
17 #include "MCTargetDesc/AArch64AddressingModes.h"
18 #include "MCTargetDesc/AArch64InstPrinter.h"
19 #include "TargetInfo/AArch64TargetInfo.h"
20 #include "llvm/DebugInfo/CodeView/CodeView.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/TargetRegistry.h"
30 #include "llvm/Support/Endian.h"
31 #include "llvm/Support/ErrorHandling.h"
32
33 using namespace llvm;
34
35 #define GET_INSTRINFO_MC_DESC
36 #define GET_INSTRINFO_MC_HELPERS
37 #define ENABLE_INSTR_PREDICATE_VERIFIER
38 #include "AArch64GenInstrInfo.inc"
39
40 #define GET_SUBTARGETINFO_MC_DESC
41 #include "AArch64GenSubtargetInfo.inc"
42
43 #define GET_REGINFO_MC_DESC
44 #include "AArch64GenRegisterInfo.inc"
45
createAArch64MCInstrInfo()46 static MCInstrInfo *createAArch64MCInstrInfo() {
47 MCInstrInfo *X = new MCInstrInfo();
48 InitAArch64MCInstrInfo(X);
49 return X;
50 }
51
52 static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)53 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
54 if (CPU.empty()) {
55 CPU = "generic";
56 if (FS.empty())
57 FS = "+v8a";
58
59 if (TT.isArm64e())
60 CPU = "apple-a12";
61 }
62
63 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
64 }
65
initLLVMToCVRegMapping(MCRegisterInfo * MRI)66 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
67 // Mapping from CodeView to MC register id.
68 static const struct {
69 codeview::RegisterId CVReg;
70 MCPhysReg Reg;
71 } RegMap[] = {
72 {codeview::RegisterId::ARM64_W0, AArch64::W0},
73 {codeview::RegisterId::ARM64_W1, AArch64::W1},
74 {codeview::RegisterId::ARM64_W2, AArch64::W2},
75 {codeview::RegisterId::ARM64_W3, AArch64::W3},
76 {codeview::RegisterId::ARM64_W4, AArch64::W4},
77 {codeview::RegisterId::ARM64_W5, AArch64::W5},
78 {codeview::RegisterId::ARM64_W6, AArch64::W6},
79 {codeview::RegisterId::ARM64_W7, AArch64::W7},
80 {codeview::RegisterId::ARM64_W8, AArch64::W8},
81 {codeview::RegisterId::ARM64_W9, AArch64::W9},
82 {codeview::RegisterId::ARM64_W10, AArch64::W10},
83 {codeview::RegisterId::ARM64_W11, AArch64::W11},
84 {codeview::RegisterId::ARM64_W12, AArch64::W12},
85 {codeview::RegisterId::ARM64_W13, AArch64::W13},
86 {codeview::RegisterId::ARM64_W14, AArch64::W14},
87 {codeview::RegisterId::ARM64_W15, AArch64::W15},
88 {codeview::RegisterId::ARM64_W16, AArch64::W16},
89 {codeview::RegisterId::ARM64_W17, AArch64::W17},
90 {codeview::RegisterId::ARM64_W18, AArch64::W18},
91 {codeview::RegisterId::ARM64_W19, AArch64::W19},
92 {codeview::RegisterId::ARM64_W20, AArch64::W20},
93 {codeview::RegisterId::ARM64_W21, AArch64::W21},
94 {codeview::RegisterId::ARM64_W22, AArch64::W22},
95 {codeview::RegisterId::ARM64_W23, AArch64::W23},
96 {codeview::RegisterId::ARM64_W24, AArch64::W24},
97 {codeview::RegisterId::ARM64_W25, AArch64::W25},
98 {codeview::RegisterId::ARM64_W26, AArch64::W26},
99 {codeview::RegisterId::ARM64_W27, AArch64::W27},
100 {codeview::RegisterId::ARM64_W28, AArch64::W28},
101 {codeview::RegisterId::ARM64_W29, AArch64::W29},
102 {codeview::RegisterId::ARM64_W30, AArch64::W30},
103 {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
104 {codeview::RegisterId::ARM64_X0, AArch64::X0},
105 {codeview::RegisterId::ARM64_X1, AArch64::X1},
106 {codeview::RegisterId::ARM64_X2, AArch64::X2},
107 {codeview::RegisterId::ARM64_X3, AArch64::X3},
108 {codeview::RegisterId::ARM64_X4, AArch64::X4},
109 {codeview::RegisterId::ARM64_X5, AArch64::X5},
110 {codeview::RegisterId::ARM64_X6, AArch64::X6},
111 {codeview::RegisterId::ARM64_X7, AArch64::X7},
112 {codeview::RegisterId::ARM64_X8, AArch64::X8},
113 {codeview::RegisterId::ARM64_X9, AArch64::X9},
114 {codeview::RegisterId::ARM64_X10, AArch64::X10},
115 {codeview::RegisterId::ARM64_X11, AArch64::X11},
116 {codeview::RegisterId::ARM64_X12, AArch64::X12},
117 {codeview::RegisterId::ARM64_X13, AArch64::X13},
118 {codeview::RegisterId::ARM64_X14, AArch64::X14},
119 {codeview::RegisterId::ARM64_X15, AArch64::X15},
120 {codeview::RegisterId::ARM64_X16, AArch64::X16},
121 {codeview::RegisterId::ARM64_X17, AArch64::X17},
122 {codeview::RegisterId::ARM64_X18, AArch64::X18},
123 {codeview::RegisterId::ARM64_X19, AArch64::X19},
124 {codeview::RegisterId::ARM64_X20, AArch64::X20},
125 {codeview::RegisterId::ARM64_X21, AArch64::X21},
126 {codeview::RegisterId::ARM64_X22, AArch64::X22},
127 {codeview::RegisterId::ARM64_X23, AArch64::X23},
128 {codeview::RegisterId::ARM64_X24, AArch64::X24},
129 {codeview::RegisterId::ARM64_X25, AArch64::X25},
130 {codeview::RegisterId::ARM64_X26, AArch64::X26},
131 {codeview::RegisterId::ARM64_X27, AArch64::X27},
132 {codeview::RegisterId::ARM64_X28, AArch64::X28},
133 {codeview::RegisterId::ARM64_FP, AArch64::FP},
134 {codeview::RegisterId::ARM64_LR, AArch64::LR},
135 {codeview::RegisterId::ARM64_SP, AArch64::SP},
136 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
137 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
138 {codeview::RegisterId::ARM64_S0, AArch64::S0},
139 {codeview::RegisterId::ARM64_S1, AArch64::S1},
140 {codeview::RegisterId::ARM64_S2, AArch64::S2},
141 {codeview::RegisterId::ARM64_S3, AArch64::S3},
142 {codeview::RegisterId::ARM64_S4, AArch64::S4},
143 {codeview::RegisterId::ARM64_S5, AArch64::S5},
144 {codeview::RegisterId::ARM64_S6, AArch64::S6},
145 {codeview::RegisterId::ARM64_S7, AArch64::S7},
146 {codeview::RegisterId::ARM64_S8, AArch64::S8},
147 {codeview::RegisterId::ARM64_S9, AArch64::S9},
148 {codeview::RegisterId::ARM64_S10, AArch64::S10},
149 {codeview::RegisterId::ARM64_S11, AArch64::S11},
150 {codeview::RegisterId::ARM64_S12, AArch64::S12},
151 {codeview::RegisterId::ARM64_S13, AArch64::S13},
152 {codeview::RegisterId::ARM64_S14, AArch64::S14},
153 {codeview::RegisterId::ARM64_S15, AArch64::S15},
154 {codeview::RegisterId::ARM64_S16, AArch64::S16},
155 {codeview::RegisterId::ARM64_S17, AArch64::S17},
156 {codeview::RegisterId::ARM64_S18, AArch64::S18},
157 {codeview::RegisterId::ARM64_S19, AArch64::S19},
158 {codeview::RegisterId::ARM64_S20, AArch64::S20},
159 {codeview::RegisterId::ARM64_S21, AArch64::S21},
160 {codeview::RegisterId::ARM64_S22, AArch64::S22},
161 {codeview::RegisterId::ARM64_S23, AArch64::S23},
162 {codeview::RegisterId::ARM64_S24, AArch64::S24},
163 {codeview::RegisterId::ARM64_S25, AArch64::S25},
164 {codeview::RegisterId::ARM64_S26, AArch64::S26},
165 {codeview::RegisterId::ARM64_S27, AArch64::S27},
166 {codeview::RegisterId::ARM64_S28, AArch64::S28},
167 {codeview::RegisterId::ARM64_S29, AArch64::S29},
168 {codeview::RegisterId::ARM64_S30, AArch64::S30},
169 {codeview::RegisterId::ARM64_S31, AArch64::S31},
170 {codeview::RegisterId::ARM64_D0, AArch64::D0},
171 {codeview::RegisterId::ARM64_D1, AArch64::D1},
172 {codeview::RegisterId::ARM64_D2, AArch64::D2},
173 {codeview::RegisterId::ARM64_D3, AArch64::D3},
174 {codeview::RegisterId::ARM64_D4, AArch64::D4},
175 {codeview::RegisterId::ARM64_D5, AArch64::D5},
176 {codeview::RegisterId::ARM64_D6, AArch64::D6},
177 {codeview::RegisterId::ARM64_D7, AArch64::D7},
178 {codeview::RegisterId::ARM64_D8, AArch64::D8},
179 {codeview::RegisterId::ARM64_D9, AArch64::D9},
180 {codeview::RegisterId::ARM64_D10, AArch64::D10},
181 {codeview::RegisterId::ARM64_D11, AArch64::D11},
182 {codeview::RegisterId::ARM64_D12, AArch64::D12},
183 {codeview::RegisterId::ARM64_D13, AArch64::D13},
184 {codeview::RegisterId::ARM64_D14, AArch64::D14},
185 {codeview::RegisterId::ARM64_D15, AArch64::D15},
186 {codeview::RegisterId::ARM64_D16, AArch64::D16},
187 {codeview::RegisterId::ARM64_D17, AArch64::D17},
188 {codeview::RegisterId::ARM64_D18, AArch64::D18},
189 {codeview::RegisterId::ARM64_D19, AArch64::D19},
190 {codeview::RegisterId::ARM64_D20, AArch64::D20},
191 {codeview::RegisterId::ARM64_D21, AArch64::D21},
192 {codeview::RegisterId::ARM64_D22, AArch64::D22},
193 {codeview::RegisterId::ARM64_D23, AArch64::D23},
194 {codeview::RegisterId::ARM64_D24, AArch64::D24},
195 {codeview::RegisterId::ARM64_D25, AArch64::D25},
196 {codeview::RegisterId::ARM64_D26, AArch64::D26},
197 {codeview::RegisterId::ARM64_D27, AArch64::D27},
198 {codeview::RegisterId::ARM64_D28, AArch64::D28},
199 {codeview::RegisterId::ARM64_D29, AArch64::D29},
200 {codeview::RegisterId::ARM64_D30, AArch64::D30},
201 {codeview::RegisterId::ARM64_D31, AArch64::D31},
202 {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
203 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
204 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
205 {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
206 {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
207 {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
208 {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
209 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
210 {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
211 {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
212 {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
213 {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
214 {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
215 {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
216 {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
217 {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
218 {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
219 {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
220 {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
221 {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
222 {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
223 {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
224 {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
225 {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
226 {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
227 {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
228 {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
229 {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
230 {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
231 {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
232 {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
233 {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
234 {codeview::RegisterId::ARM64_B0, AArch64::B0},
235 {codeview::RegisterId::ARM64_B1, AArch64::B1},
236 {codeview::RegisterId::ARM64_B2, AArch64::B2},
237 {codeview::RegisterId::ARM64_B3, AArch64::B3},
238 {codeview::RegisterId::ARM64_B4, AArch64::B4},
239 {codeview::RegisterId::ARM64_B5, AArch64::B5},
240 {codeview::RegisterId::ARM64_B6, AArch64::B6},
241 {codeview::RegisterId::ARM64_B7, AArch64::B7},
242 {codeview::RegisterId::ARM64_B8, AArch64::B8},
243 {codeview::RegisterId::ARM64_B9, AArch64::B9},
244 {codeview::RegisterId::ARM64_B10, AArch64::B10},
245 {codeview::RegisterId::ARM64_B11, AArch64::B11},
246 {codeview::RegisterId::ARM64_B12, AArch64::B12},
247 {codeview::RegisterId::ARM64_B13, AArch64::B13},
248 {codeview::RegisterId::ARM64_B14, AArch64::B14},
249 {codeview::RegisterId::ARM64_B15, AArch64::B15},
250 {codeview::RegisterId::ARM64_B16, AArch64::B16},
251 {codeview::RegisterId::ARM64_B17, AArch64::B17},
252 {codeview::RegisterId::ARM64_B18, AArch64::B18},
253 {codeview::RegisterId::ARM64_B19, AArch64::B19},
254 {codeview::RegisterId::ARM64_B20, AArch64::B20},
255 {codeview::RegisterId::ARM64_B21, AArch64::B21},
256 {codeview::RegisterId::ARM64_B22, AArch64::B22},
257 {codeview::RegisterId::ARM64_B23, AArch64::B23},
258 {codeview::RegisterId::ARM64_B24, AArch64::B24},
259 {codeview::RegisterId::ARM64_B25, AArch64::B25},
260 {codeview::RegisterId::ARM64_B26, AArch64::B26},
261 {codeview::RegisterId::ARM64_B27, AArch64::B27},
262 {codeview::RegisterId::ARM64_B28, AArch64::B28},
263 {codeview::RegisterId::ARM64_B29, AArch64::B29},
264 {codeview::RegisterId::ARM64_B30, AArch64::B30},
265 {codeview::RegisterId::ARM64_B31, AArch64::B31},
266 {codeview::RegisterId::ARM64_H0, AArch64::H0},
267 {codeview::RegisterId::ARM64_H1, AArch64::H1},
268 {codeview::RegisterId::ARM64_H2, AArch64::H2},
269 {codeview::RegisterId::ARM64_H3, AArch64::H3},
270 {codeview::RegisterId::ARM64_H4, AArch64::H4},
271 {codeview::RegisterId::ARM64_H5, AArch64::H5},
272 {codeview::RegisterId::ARM64_H6, AArch64::H6},
273 {codeview::RegisterId::ARM64_H7, AArch64::H7},
274 {codeview::RegisterId::ARM64_H8, AArch64::H8},
275 {codeview::RegisterId::ARM64_H9, AArch64::H9},
276 {codeview::RegisterId::ARM64_H10, AArch64::H10},
277 {codeview::RegisterId::ARM64_H11, AArch64::H11},
278 {codeview::RegisterId::ARM64_H12, AArch64::H12},
279 {codeview::RegisterId::ARM64_H13, AArch64::H13},
280 {codeview::RegisterId::ARM64_H14, AArch64::H14},
281 {codeview::RegisterId::ARM64_H15, AArch64::H15},
282 {codeview::RegisterId::ARM64_H16, AArch64::H16},
283 {codeview::RegisterId::ARM64_H17, AArch64::H17},
284 {codeview::RegisterId::ARM64_H18, AArch64::H18},
285 {codeview::RegisterId::ARM64_H19, AArch64::H19},
286 {codeview::RegisterId::ARM64_H20, AArch64::H20},
287 {codeview::RegisterId::ARM64_H21, AArch64::H21},
288 {codeview::RegisterId::ARM64_H22, AArch64::H22},
289 {codeview::RegisterId::ARM64_H23, AArch64::H23},
290 {codeview::RegisterId::ARM64_H24, AArch64::H24},
291 {codeview::RegisterId::ARM64_H25, AArch64::H25},
292 {codeview::RegisterId::ARM64_H26, AArch64::H26},
293 {codeview::RegisterId::ARM64_H27, AArch64::H27},
294 {codeview::RegisterId::ARM64_H28, AArch64::H28},
295 {codeview::RegisterId::ARM64_H29, AArch64::H29},
296 {codeview::RegisterId::ARM64_H30, AArch64::H30},
297 {codeview::RegisterId::ARM64_H31, AArch64::H31},
298 };
299 for (const auto &I : RegMap)
300 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
301 }
302
isHForm(const MCInst & MI,const MCInstrInfo * MCII)303 bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {
304 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
305 return llvm::any_of(MI, [&](const MCOperand &Op) {
306 return Op.isReg() && FPR16.contains(Op.getReg());
307 });
308 }
309
isQForm(const MCInst & MI,const MCInstrInfo * MCII)310 bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
311 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
312 return llvm::any_of(MI, [&](const MCOperand &Op) {
313 return Op.isReg() && FPR128.contains(Op.getReg());
314 });
315 }
316
isFpOrNEON(const MCInst & MI,const MCInstrInfo * MCII)317 bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
318 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
319 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];
320 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];
321 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
322 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];
323
324 auto IsFPR = [&](const MCOperand &Op) {
325 if (!Op.isReg())
326 return false;
327 auto Reg = Op.getReg();
328 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
329 FPR16.contains(Reg) || FPR8.contains(Reg);
330 };
331
332 return llvm::any_of(MI, IsFPR);
333 }
334
createAArch64MCRegisterInfo(const Triple & Triple)335 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
336 MCRegisterInfo *X = new MCRegisterInfo();
337 InitAArch64MCRegisterInfo(X, AArch64::LR);
338 AArch64_MC::initLLVMToCVRegMapping(X);
339 return X;
340 }
341
createAArch64MCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple,const MCTargetOptions & Options)342 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
343 const Triple &TheTriple,
344 const MCTargetOptions &Options) {
345 MCAsmInfo *MAI;
346 if (TheTriple.isOSBinFormatMachO())
347 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
348 else if (TheTriple.isWindowsMSVCEnvironment())
349 MAI = new AArch64MCAsmInfoMicrosoftCOFF();
350 else if (TheTriple.isOSBinFormatCOFF())
351 MAI = new AArch64MCAsmInfoGNUCOFF();
352 else {
353 assert(TheTriple.isOSBinFormatELF() && "Invalid target");
354 MAI = new AArch64MCAsmInfoELF(TheTriple);
355 }
356
357 // Initial state of the frame pointer is SP.
358 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
359 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
360 MAI->addInitialFrameState(Inst);
361
362 return MAI;
363 }
364
createAArch64MCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)365 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
366 unsigned SyntaxVariant,
367 const MCAsmInfo &MAI,
368 const MCInstrInfo &MII,
369 const MCRegisterInfo &MRI) {
370 if (SyntaxVariant == 0)
371 return new AArch64InstPrinter(MAI, MII, MRI);
372 if (SyntaxVariant == 1)
373 return new AArch64AppleInstPrinter(MAI, MII, MRI);
374
375 return nullptr;
376 }
377
createELFStreamer(const Triple & T,MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)378 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
379 std::unique_ptr<MCAsmBackend> &&TAB,
380 std::unique_ptr<MCObjectWriter> &&OW,
381 std::unique_ptr<MCCodeEmitter> &&Emitter,
382 bool RelaxAll) {
383 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
384 std::move(Emitter), RelaxAll);
385 }
386
createMachOStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll,bool DWARFMustBeAtTheEnd)387 static MCStreamer *createMachOStreamer(MCContext &Ctx,
388 std::unique_ptr<MCAsmBackend> &&TAB,
389 std::unique_ptr<MCObjectWriter> &&OW,
390 std::unique_ptr<MCCodeEmitter> &&Emitter,
391 bool RelaxAll,
392 bool DWARFMustBeAtTheEnd) {
393 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
394 std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
395 /*LabelSections*/ true);
396 }
397
398 static MCStreamer *
createWinCOFFStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll,bool IncrementalLinkerCompatible)399 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
400 std::unique_ptr<MCObjectWriter> &&OW,
401 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
402 bool IncrementalLinkerCompatible) {
403 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
404 std::move(Emitter), RelaxAll,
405 IncrementalLinkerCompatible);
406 }
407
408 namespace {
409
410 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
411 public:
AArch64MCInstrAnalysis(const MCInstrInfo * Info)412 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
413
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const414 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
415 uint64_t &Target) const override {
416 // Search for a PC-relative argument.
417 // This will handle instructions like bcc (where the first argument is the
418 // condition code) and cbz (where it is a register).
419 const auto &Desc = Info->get(Inst.getOpcode());
420 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
421 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {
422 int64_t Imm = Inst.getOperand(i).getImm();
423 if (Inst.getOpcode() == AArch64::ADR)
424 Target = Addr + Imm;
425 else if (Inst.getOpcode() == AArch64::ADRP)
426 Target = (Addr & -4096) + Imm * 4096;
427 else
428 Target = Addr + Imm * 4;
429 return true;
430 }
431 }
432 return false;
433 }
434
435 std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(uint64_t PltSectionVA,ArrayRef<uint8_t> PltContents,const Triple & TargetTriple) const436 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
437 const Triple &TargetTriple) const override {
438 // Do a lightweight parsing of PLT entries.
439 std::vector<std::pair<uint64_t, uint64_t>> Result;
440 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
441 Byte += 4) {
442 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
443 uint64_t Off = 0;
444 // Check for optional bti c that prefixes adrp in BTI enabled entries
445 if (Insn == 0xd503245f) {
446 Off = 4;
447 Insn = support::endian::read32le(PltContents.data() + Byte + Off);
448 }
449 // Check for adrp.
450 if ((Insn & 0x9f000000) != 0x90000000)
451 continue;
452 Off += 4;
453 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
454 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
455 uint32_t Insn2 =
456 support::endian::read32le(PltContents.data() + Byte + Off);
457 // Check for: ldr Xt, [Xn, #pimm].
458 if (Insn2 >> 22 == 0x3e5) {
459 Imm += ((Insn2 >> 10) & 0xfff) << 3;
460 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
461 Byte += 4;
462 }
463 }
464 return Result;
465 }
466 };
467
468 } // end anonymous namespace
469
createAArch64InstrAnalysis(const MCInstrInfo * Info)470 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
471 return new AArch64MCInstrAnalysis(Info);
472 }
473
474 // Force static initialization.
LLVMInitializeAArch64TargetMC()475 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() {
476 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
477 &getTheAArch64_32Target(), &getTheARM64Target(),
478 &getTheARM64_32Target()}) {
479 // Register the MC asm info.
480 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
481
482 // Register the MC instruction info.
483 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
484
485 // Register the MC register info.
486 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
487
488 // Register the MC subtarget info.
489 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
490
491 // Register the MC instruction analyzer.
492 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
493
494 // Register the MC Code Emitter
495 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
496
497 // Register the obj streamers.
498 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
499 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
500 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
501
502 // Register the obj target streamer.
503 TargetRegistry::RegisterObjectTargetStreamer(
504 *T, createAArch64ObjectTargetStreamer);
505
506 // Register the asm streamer.
507 TargetRegistry::RegisterAsmTargetStreamer(*T,
508 createAArch64AsmTargetStreamer);
509 // Register the null streamer.
510 TargetRegistry::RegisterNullTargetStreamer(*T,
511 createAArch64NullTargetStreamer);
512
513 // Register the MCInstPrinter.
514 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
515 }
516
517 // Register the asm backend.
518 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
519 &getTheARM64Target(), &getTheARM64_32Target()})
520 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
521 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
522 createAArch64beAsmBackend);
523 }
524