1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AArch64 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64MCTargetDesc.h" 14 #include "AArch64ELFStreamer.h" 15 #include "AArch64MCAsmInfo.h" 16 #include "AArch64WinCOFFStreamer.h" 17 #include "MCTargetDesc/AArch64AddressingModes.h" 18 #include "MCTargetDesc/AArch64InstPrinter.h" 19 #include "TargetInfo/AArch64TargetInfo.h" 20 #include "llvm/DebugInfo/CodeView/CodeView.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/ErrorHandling.h" 32 33 using namespace llvm; 34 35 #define GET_INSTRINFO_MC_DESC 36 #define GET_INSTRINFO_MC_HELPERS 37 #include "AArch64GenInstrInfo.inc" 38 39 #define GET_SUBTARGETINFO_MC_DESC 40 #include "AArch64GenSubtargetInfo.inc" 41 42 #define GET_REGINFO_MC_DESC 43 #include "AArch64GenRegisterInfo.inc" 44 45 static MCInstrInfo *createAArch64MCInstrInfo() { 46 MCInstrInfo *X = new MCInstrInfo(); 47 InitAArch64MCInstrInfo(X); 48 return X; 49 } 50 51 static MCSubtargetInfo * 52 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 53 if (CPU.empty()) { 54 CPU = "generic"; 55 if (FS.empty()) 56 FS = "+v8a"; 57 58 if (TT.isArm64e()) 59 CPU = "apple-a12"; 60 } 61 62 // Most of the NEON instruction set isn't supported in streaming mode on SME 63 // targets, disable NEON unless explicitly requested. 64 bool RequestedNEON = FS.contains("neon"); 65 bool RequestedStreamingSVE = FS.contains("streaming-sve"); 66 MCSubtargetInfo *STI = 67 createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 68 if (RequestedStreamingSVE && !RequestedNEON && 69 STI->hasFeature(AArch64::FeatureNEON)) 70 STI->ToggleFeature(AArch64::FeatureNEON); 71 return STI; 72 } 73 74 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 75 // Mapping from CodeView to MC register id. 76 static const struct { 77 codeview::RegisterId CVReg; 78 MCPhysReg Reg; 79 } RegMap[] = { 80 {codeview::RegisterId::ARM64_W0, AArch64::W0}, 81 {codeview::RegisterId::ARM64_W1, AArch64::W1}, 82 {codeview::RegisterId::ARM64_W2, AArch64::W2}, 83 {codeview::RegisterId::ARM64_W3, AArch64::W3}, 84 {codeview::RegisterId::ARM64_W4, AArch64::W4}, 85 {codeview::RegisterId::ARM64_W5, AArch64::W5}, 86 {codeview::RegisterId::ARM64_W6, AArch64::W6}, 87 {codeview::RegisterId::ARM64_W7, AArch64::W7}, 88 {codeview::RegisterId::ARM64_W8, AArch64::W8}, 89 {codeview::RegisterId::ARM64_W9, AArch64::W9}, 90 {codeview::RegisterId::ARM64_W10, AArch64::W10}, 91 {codeview::RegisterId::ARM64_W11, AArch64::W11}, 92 {codeview::RegisterId::ARM64_W12, AArch64::W12}, 93 {codeview::RegisterId::ARM64_W13, AArch64::W13}, 94 {codeview::RegisterId::ARM64_W14, AArch64::W14}, 95 {codeview::RegisterId::ARM64_W15, AArch64::W15}, 96 {codeview::RegisterId::ARM64_W16, AArch64::W16}, 97 {codeview::RegisterId::ARM64_W17, AArch64::W17}, 98 {codeview::RegisterId::ARM64_W18, AArch64::W18}, 99 {codeview::RegisterId::ARM64_W19, AArch64::W19}, 100 {codeview::RegisterId::ARM64_W20, AArch64::W20}, 101 {codeview::RegisterId::ARM64_W21, AArch64::W21}, 102 {codeview::RegisterId::ARM64_W22, AArch64::W22}, 103 {codeview::RegisterId::ARM64_W23, AArch64::W23}, 104 {codeview::RegisterId::ARM64_W24, AArch64::W24}, 105 {codeview::RegisterId::ARM64_W25, AArch64::W25}, 106 {codeview::RegisterId::ARM64_W26, AArch64::W26}, 107 {codeview::RegisterId::ARM64_W27, AArch64::W27}, 108 {codeview::RegisterId::ARM64_W28, AArch64::W28}, 109 {codeview::RegisterId::ARM64_W29, AArch64::W29}, 110 {codeview::RegisterId::ARM64_W30, AArch64::W30}, 111 {codeview::RegisterId::ARM64_WZR, AArch64::WZR}, 112 {codeview::RegisterId::ARM64_X0, AArch64::X0}, 113 {codeview::RegisterId::ARM64_X1, AArch64::X1}, 114 {codeview::RegisterId::ARM64_X2, AArch64::X2}, 115 {codeview::RegisterId::ARM64_X3, AArch64::X3}, 116 {codeview::RegisterId::ARM64_X4, AArch64::X4}, 117 {codeview::RegisterId::ARM64_X5, AArch64::X5}, 118 {codeview::RegisterId::ARM64_X6, AArch64::X6}, 119 {codeview::RegisterId::ARM64_X7, AArch64::X7}, 120 {codeview::RegisterId::ARM64_X8, AArch64::X8}, 121 {codeview::RegisterId::ARM64_X9, AArch64::X9}, 122 {codeview::RegisterId::ARM64_X10, AArch64::X10}, 123 {codeview::RegisterId::ARM64_X11, AArch64::X11}, 124 {codeview::RegisterId::ARM64_X12, AArch64::X12}, 125 {codeview::RegisterId::ARM64_X13, AArch64::X13}, 126 {codeview::RegisterId::ARM64_X14, AArch64::X14}, 127 {codeview::RegisterId::ARM64_X15, AArch64::X15}, 128 {codeview::RegisterId::ARM64_X16, AArch64::X16}, 129 {codeview::RegisterId::ARM64_X17, AArch64::X17}, 130 {codeview::RegisterId::ARM64_X18, AArch64::X18}, 131 {codeview::RegisterId::ARM64_X19, AArch64::X19}, 132 {codeview::RegisterId::ARM64_X20, AArch64::X20}, 133 {codeview::RegisterId::ARM64_X21, AArch64::X21}, 134 {codeview::RegisterId::ARM64_X22, AArch64::X22}, 135 {codeview::RegisterId::ARM64_X23, AArch64::X23}, 136 {codeview::RegisterId::ARM64_X24, AArch64::X24}, 137 {codeview::RegisterId::ARM64_X25, AArch64::X25}, 138 {codeview::RegisterId::ARM64_X26, AArch64::X26}, 139 {codeview::RegisterId::ARM64_X27, AArch64::X27}, 140 {codeview::RegisterId::ARM64_X28, AArch64::X28}, 141 {codeview::RegisterId::ARM64_FP, AArch64::FP}, 142 {codeview::RegisterId::ARM64_LR, AArch64::LR}, 143 {codeview::RegisterId::ARM64_SP, AArch64::SP}, 144 {codeview::RegisterId::ARM64_ZR, AArch64::XZR}, 145 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, 146 {codeview::RegisterId::ARM64_S0, AArch64::S0}, 147 {codeview::RegisterId::ARM64_S1, AArch64::S1}, 148 {codeview::RegisterId::ARM64_S2, AArch64::S2}, 149 {codeview::RegisterId::ARM64_S3, AArch64::S3}, 150 {codeview::RegisterId::ARM64_S4, AArch64::S4}, 151 {codeview::RegisterId::ARM64_S5, AArch64::S5}, 152 {codeview::RegisterId::ARM64_S6, AArch64::S6}, 153 {codeview::RegisterId::ARM64_S7, AArch64::S7}, 154 {codeview::RegisterId::ARM64_S8, AArch64::S8}, 155 {codeview::RegisterId::ARM64_S9, AArch64::S9}, 156 {codeview::RegisterId::ARM64_S10, AArch64::S10}, 157 {codeview::RegisterId::ARM64_S11, AArch64::S11}, 158 {codeview::RegisterId::ARM64_S12, AArch64::S12}, 159 {codeview::RegisterId::ARM64_S13, AArch64::S13}, 160 {codeview::RegisterId::ARM64_S14, AArch64::S14}, 161 {codeview::RegisterId::ARM64_S15, AArch64::S15}, 162 {codeview::RegisterId::ARM64_S16, AArch64::S16}, 163 {codeview::RegisterId::ARM64_S17, AArch64::S17}, 164 {codeview::RegisterId::ARM64_S18, AArch64::S18}, 165 {codeview::RegisterId::ARM64_S19, AArch64::S19}, 166 {codeview::RegisterId::ARM64_S20, AArch64::S20}, 167 {codeview::RegisterId::ARM64_S21, AArch64::S21}, 168 {codeview::RegisterId::ARM64_S22, AArch64::S22}, 169 {codeview::RegisterId::ARM64_S23, AArch64::S23}, 170 {codeview::RegisterId::ARM64_S24, AArch64::S24}, 171 {codeview::RegisterId::ARM64_S25, AArch64::S25}, 172 {codeview::RegisterId::ARM64_S26, AArch64::S26}, 173 {codeview::RegisterId::ARM64_S27, AArch64::S27}, 174 {codeview::RegisterId::ARM64_S28, AArch64::S28}, 175 {codeview::RegisterId::ARM64_S29, AArch64::S29}, 176 {codeview::RegisterId::ARM64_S30, AArch64::S30}, 177 {codeview::RegisterId::ARM64_S31, AArch64::S31}, 178 {codeview::RegisterId::ARM64_D0, AArch64::D0}, 179 {codeview::RegisterId::ARM64_D1, AArch64::D1}, 180 {codeview::RegisterId::ARM64_D2, AArch64::D2}, 181 {codeview::RegisterId::ARM64_D3, AArch64::D3}, 182 {codeview::RegisterId::ARM64_D4, AArch64::D4}, 183 {codeview::RegisterId::ARM64_D5, AArch64::D5}, 184 {codeview::RegisterId::ARM64_D6, AArch64::D6}, 185 {codeview::RegisterId::ARM64_D7, AArch64::D7}, 186 {codeview::RegisterId::ARM64_D8, AArch64::D8}, 187 {codeview::RegisterId::ARM64_D9, AArch64::D9}, 188 {codeview::RegisterId::ARM64_D10, AArch64::D10}, 189 {codeview::RegisterId::ARM64_D11, AArch64::D11}, 190 {codeview::RegisterId::ARM64_D12, AArch64::D12}, 191 {codeview::RegisterId::ARM64_D13, AArch64::D13}, 192 {codeview::RegisterId::ARM64_D14, AArch64::D14}, 193 {codeview::RegisterId::ARM64_D15, AArch64::D15}, 194 {codeview::RegisterId::ARM64_D16, AArch64::D16}, 195 {codeview::RegisterId::ARM64_D17, AArch64::D17}, 196 {codeview::RegisterId::ARM64_D18, AArch64::D18}, 197 {codeview::RegisterId::ARM64_D19, AArch64::D19}, 198 {codeview::RegisterId::ARM64_D20, AArch64::D20}, 199 {codeview::RegisterId::ARM64_D21, AArch64::D21}, 200 {codeview::RegisterId::ARM64_D22, AArch64::D22}, 201 {codeview::RegisterId::ARM64_D23, AArch64::D23}, 202 {codeview::RegisterId::ARM64_D24, AArch64::D24}, 203 {codeview::RegisterId::ARM64_D25, AArch64::D25}, 204 {codeview::RegisterId::ARM64_D26, AArch64::D26}, 205 {codeview::RegisterId::ARM64_D27, AArch64::D27}, 206 {codeview::RegisterId::ARM64_D28, AArch64::D28}, 207 {codeview::RegisterId::ARM64_D29, AArch64::D29}, 208 {codeview::RegisterId::ARM64_D30, AArch64::D30}, 209 {codeview::RegisterId::ARM64_D31, AArch64::D31}, 210 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, 211 {codeview::RegisterId::ARM64_Q1, AArch64::Q1}, 212 {codeview::RegisterId::ARM64_Q2, AArch64::Q2}, 213 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, 214 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, 215 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, 216 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, 217 {codeview::RegisterId::ARM64_Q7, AArch64::Q7}, 218 {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, 219 {codeview::RegisterId::ARM64_Q9, AArch64::Q9}, 220 {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, 221 {codeview::RegisterId::ARM64_Q11, AArch64::Q11}, 222 {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, 223 {codeview::RegisterId::ARM64_Q13, AArch64::Q13}, 224 {codeview::RegisterId::ARM64_Q14, AArch64::Q14}, 225 {codeview::RegisterId::ARM64_Q15, AArch64::Q15}, 226 {codeview::RegisterId::ARM64_Q16, AArch64::Q16}, 227 {codeview::RegisterId::ARM64_Q17, AArch64::Q17}, 228 {codeview::RegisterId::ARM64_Q18, AArch64::Q18}, 229 {codeview::RegisterId::ARM64_Q19, AArch64::Q19}, 230 {codeview::RegisterId::ARM64_Q20, AArch64::Q20}, 231 {codeview::RegisterId::ARM64_Q21, AArch64::Q21}, 232 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, 233 {codeview::RegisterId::ARM64_Q23, AArch64::Q23}, 234 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, 235 {codeview::RegisterId::ARM64_Q25, AArch64::Q25}, 236 {codeview::RegisterId::ARM64_Q26, AArch64::Q26}, 237 {codeview::RegisterId::ARM64_Q27, AArch64::Q27}, 238 {codeview::RegisterId::ARM64_Q28, AArch64::Q28}, 239 {codeview::RegisterId::ARM64_Q29, AArch64::Q29}, 240 {codeview::RegisterId::ARM64_Q30, AArch64::Q30}, 241 {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, 242 243 }; 244 for (const auto &I : RegMap) 245 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 246 } 247 248 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { 249 MCRegisterInfo *X = new MCRegisterInfo(); 250 InitAArch64MCRegisterInfo(X, AArch64::LR); 251 AArch64_MC::initLLVMToCVRegMapping(X); 252 return X; 253 } 254 255 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, 256 const Triple &TheTriple, 257 const MCTargetOptions &Options) { 258 MCAsmInfo *MAI; 259 if (TheTriple.isOSBinFormatMachO()) 260 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); 261 else if (TheTriple.isWindowsMSVCEnvironment()) 262 MAI = new AArch64MCAsmInfoMicrosoftCOFF(); 263 else if (TheTriple.isOSBinFormatCOFF()) 264 MAI = new AArch64MCAsmInfoGNUCOFF(); 265 else { 266 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 267 MAI = new AArch64MCAsmInfoELF(TheTriple); 268 } 269 270 // Initial state of the frame pointer is SP. 271 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); 272 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); 273 MAI->addInitialFrameState(Inst); 274 275 return MAI; 276 } 277 278 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, 279 unsigned SyntaxVariant, 280 const MCAsmInfo &MAI, 281 const MCInstrInfo &MII, 282 const MCRegisterInfo &MRI) { 283 if (SyntaxVariant == 0) 284 return new AArch64InstPrinter(MAI, MII, MRI); 285 if (SyntaxVariant == 1) 286 return new AArch64AppleInstPrinter(MAI, MII, MRI); 287 288 return nullptr; 289 } 290 291 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 292 std::unique_ptr<MCAsmBackend> &&TAB, 293 std::unique_ptr<MCObjectWriter> &&OW, 294 std::unique_ptr<MCCodeEmitter> &&Emitter, 295 bool RelaxAll) { 296 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW), 297 std::move(Emitter), RelaxAll); 298 } 299 300 static MCStreamer *createMachOStreamer(MCContext &Ctx, 301 std::unique_ptr<MCAsmBackend> &&TAB, 302 std::unique_ptr<MCObjectWriter> &&OW, 303 std::unique_ptr<MCCodeEmitter> &&Emitter, 304 bool RelaxAll, 305 bool DWARFMustBeAtTheEnd) { 306 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW), 307 std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd, 308 /*LabelSections*/ true); 309 } 310 311 static MCStreamer * 312 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 313 std::unique_ptr<MCObjectWriter> &&OW, 314 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, 315 bool IncrementalLinkerCompatible) { 316 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW), 317 std::move(Emitter), RelaxAll, 318 IncrementalLinkerCompatible); 319 } 320 321 namespace { 322 323 class AArch64MCInstrAnalysis : public MCInstrAnalysis { 324 public: 325 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 326 327 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 328 uint64_t &Target) const override { 329 // Search for a PC-relative argument. 330 // This will handle instructions like bcc (where the first argument is the 331 // condition code) and cbz (where it is a register). 332 const auto &Desc = Info->get(Inst.getOpcode()); 333 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 334 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) { 335 int64_t Imm = Inst.getOperand(i).getImm() * 4; 336 Target = Addr + Imm; 337 return true; 338 } 339 } 340 return false; 341 } 342 343 std::vector<std::pair<uint64_t, uint64_t>> 344 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 345 uint64_t GotPltSectionVA, 346 const Triple &TargetTriple) const override { 347 // Do a lightweight parsing of PLT entries. 348 std::vector<std::pair<uint64_t, uint64_t>> Result; 349 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End; 350 Byte += 4) { 351 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); 352 uint64_t Off = 0; 353 // Check for optional bti c that prefixes adrp in BTI enabled entries 354 if (Insn == 0xd503245f) { 355 Off = 4; 356 Insn = support::endian::read32le(PltContents.data() + Byte + Off); 357 } 358 // Check for adrp. 359 if ((Insn & 0x9f000000) != 0x90000000) 360 continue; 361 Off += 4; 362 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) + 363 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); 364 uint32_t Insn2 = 365 support::endian::read32le(PltContents.data() + Byte + Off); 366 // Check for: ldr Xt, [Xn, #pimm]. 367 if (Insn2 >> 22 == 0x3e5) { 368 Imm += ((Insn2 >> 10) & 0xfff) << 3; 369 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 370 Byte += 4; 371 } 372 } 373 return Result; 374 } 375 }; 376 377 } // end anonymous namespace 378 379 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { 380 return new AArch64MCInstrAnalysis(Info); 381 } 382 383 // Force static initialization. 384 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() { 385 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), 386 &getTheAArch64_32Target(), &getTheARM64Target(), 387 &getTheARM64_32Target()}) { 388 // Register the MC asm info. 389 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 390 391 // Register the MC instruction info. 392 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 393 394 // Register the MC register info. 395 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 396 397 // Register the MC subtarget info. 398 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 399 400 // Register the MC instruction analyzer. 401 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); 402 403 // Register the MC Code Emitter 404 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 405 406 // Register the obj streamers. 407 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 408 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); 409 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); 410 411 // Register the obj target streamer. 412 TargetRegistry::RegisterObjectTargetStreamer( 413 *T, createAArch64ObjectTargetStreamer); 414 415 // Register the asm streamer. 416 TargetRegistry::RegisterAsmTargetStreamer(*T, 417 createAArch64AsmTargetStreamer); 418 // Register the MCInstPrinter. 419 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); 420 } 421 422 // Register the asm backend. 423 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(), 424 &getTheARM64Target(), &getTheARM64_32Target()}) 425 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 426 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), 427 createAArch64beAsmBackend); 428 } 429