1 //=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //==-----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// AMDGPU R600 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
16 
17 #include "AMDGPUSubtarget.h"
18 #include "R600FrameLowering.h"
19 #include "R600ISelLowering.h"
20 #include "R600InstrInfo.h"
21 #include "Utils/AMDGPUBaseInfo.h"
22 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
23 
24 #define GET_SUBTARGETINFO_HEADER
25 #include "R600GenSubtargetInfo.inc"
26 
27 namespace llvm {
28 
29 class R600Subtarget final : public R600GenSubtargetInfo,
30                             public AMDGPUSubtarget {
31 private:
32   R600InstrInfo InstrInfo;
33   R600FrameLowering FrameLowering;
34   bool FMA = false;
35   bool CaymanISA = false;
36   bool CFALUBug = false;
37   bool HasVertexCache = false;
38   bool R600ALUInst = false;
39   bool FP64 = false;
40   short TexVTXClauseSize = 0;
41   Generation Gen = R600;
42   R600TargetLowering TLInfo;
43   InstrItineraryData InstrItins;
44   SelectionDAGTargetInfo TSInfo;
45 
46 public:
47   R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
48                 const TargetMachine &TM);
49 
getInstrInfo()50   const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
51 
getFrameLowering()52   const R600FrameLowering *getFrameLowering() const override {
53     return &FrameLowering;
54   }
55 
getTargetLowering()56   const R600TargetLowering *getTargetLowering() const override {
57     return &TLInfo;
58   }
59 
getRegisterInfo()60   const R600RegisterInfo *getRegisterInfo() const override {
61     return &InstrInfo.getRegisterInfo();
62   }
63 
getInstrItineraryData()64   const InstrItineraryData *getInstrItineraryData() const override {
65     return &InstrItins;
66   }
67 
68   // Nothing implemented, just prevent crashes on use.
getSelectionDAGInfo()69   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
70     return &TSInfo;
71   }
72 
73   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
74 
getGeneration()75   Generation getGeneration() const {
76     return Gen;
77   }
78 
getStackAlignment()79   Align getStackAlignment() const { return Align(4); }
80 
81   R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
82                                                  StringRef GPU, StringRef FS);
83 
hasBFE()84   bool hasBFE() const {
85     return (getGeneration() >= EVERGREEN);
86   }
87 
hasBFI()88   bool hasBFI() const {
89     return (getGeneration() >= EVERGREEN);
90   }
91 
hasBCNT(unsigned Size)92   bool hasBCNT(unsigned Size) const {
93     if (Size == 32)
94       return (getGeneration() >= EVERGREEN);
95 
96     return false;
97   }
98 
hasBORROW()99   bool hasBORROW() const {
100     return (getGeneration() >= EVERGREEN);
101   }
102 
hasCARRY()103   bool hasCARRY() const {
104     return (getGeneration() >= EVERGREEN);
105   }
106 
hasCaymanISA()107   bool hasCaymanISA() const {
108     return CaymanISA;
109   }
110 
hasFFBL()111   bool hasFFBL() const {
112     return (getGeneration() >= EVERGREEN);
113   }
114 
hasFFBH()115   bool hasFFBH() const {
116     return (getGeneration() >= EVERGREEN);
117   }
118 
hasFMA()119   bool hasFMA() const { return FMA; }
120 
hasCFAluBug()121   bool hasCFAluBug() const { return CFALUBug; }
122 
hasVertexCache()123   bool hasVertexCache() const { return HasVertexCache; }
124 
getTexVTXClauseSize()125   short getTexVTXClauseSize() const { return TexVTXClauseSize; }
126 
enableMachineScheduler()127   bool enableMachineScheduler() const override {
128     return true;
129   }
130 
enableSubRegLiveness()131   bool enableSubRegLiveness() const override {
132     return true;
133   }
134 
135   /// \returns Maximum number of work groups per compute unit supported by the
136   /// subtarget and limited by given \p FlatWorkGroupSize.
getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize)137   unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
138     return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
139   }
140 
141   /// \returns Minimum flat work group size supported by the subtarget.
getMinFlatWorkGroupSize()142   unsigned getMinFlatWorkGroupSize() const override {
143     return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
144   }
145 
146   /// \returns Maximum flat work group size supported by the subtarget.
getMaxFlatWorkGroupSize()147   unsigned getMaxFlatWorkGroupSize() const override {
148     return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
149   }
150 
151   /// \returns Number of waves per execution unit required to support the given
152   /// \p FlatWorkGroupSize.
153   unsigned
getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize)154   getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
155     return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
156   }
157 
158   /// \returns Minimum number of waves per execution unit supported by the
159   /// subtarget.
getMinWavesPerEU()160   unsigned getMinWavesPerEU() const override {
161     return AMDGPU::IsaInfo::getMinWavesPerEU(this);
162   }
163 };
164 
165 } // end namespace llvm
166 
167 #endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
168