1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the symbolic operands permitted for various kinds of
10// RISC-V system instruction.
11//
12//===----------------------------------------------------------------------===//
13
14include "llvm/TableGen/SearchableTable.td"
15
16//===----------------------------------------------------------------------===//
17// CSR (control and status register read/write) instruction options.
18//===----------------------------------------------------------------------===//
19
20class SysReg<string name, bits<12> op> {
21  string Name = name;
22  // A maximum of one alias is supported right now.
23  string AltName = name;
24  // A maximum of one deprecated name is supported right now.  Unlike the
25  // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is
26  // used to encourage software to migrate away from the name.
27  string DeprecatedName = "";
28  bits<12> Encoding = op;
29  // FIXME: add these additional fields when needed.
30  // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31  // Privilege Mode: User = 0, System = 1 or Machine = 3.
32  // bits<2> ReadWrite = op{11 - 10};
33  // bits<2> XMode = op{9 - 8};
34  // Check Extra field name and what bits 7-6 correspond to.
35  // bits<2> Extra = op{7 - 6};
36  // Register number without the privilege bits.
37  // bits<6> Number = op{5 - 0};
38  code FeaturesRequired = [{ {} }];
39  bit isRV32Only = 0;
40}
41
42def SysRegsList : GenericTable {
43  let FilterClass = "SysReg";
44  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
45  let Fields = [
46    "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired",
47    "isRV32Only",
48  ];
49
50  let PrimaryKey = [ "Encoding" ];
51  let PrimaryKeyName = "lookupSysRegByEncoding";
52}
53
54def lookupSysRegByName : SearchIndex {
55  let Table = SysRegsList;
56  let Key = [ "Name" ];
57}
58
59def lookupSysRegByAltName : SearchIndex {
60  let Table = SysRegsList;
61  let Key = [ "AltName" ];
62}
63
64def lookupSysRegByDeprecatedName : SearchIndex {
65  let Table = SysRegsList;
66  let Key = [ "DeprecatedName" ];
67}
68
69// The following CSR encodings match those given in Tables 2.2,
70// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
71// Volume II: Privileged Architecture.
72
73//===----------------------------------------------------------------------===//
74// User Floating-Point CSRs
75//===----------------------------------------------------------------------===//
76
77def SysRegFFLAGS : SysReg<"fflags", 0x001>;
78def SysRegFRM    : SysReg<"frm", 0x002>;
79def SysRegFCSR   : SysReg<"fcsr", 0x003>;
80
81//===----------------------------------------------------------------------===//
82// User Counter/Timers
83//===----------------------------------------------------------------------===//
84def CYCLE   : SysReg<"cycle", 0xC00>;
85def TIME    : SysReg<"time", 0xC01>;
86def INSTRET : SysReg<"instret", 0xC02>;
87
88// hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
89foreach i = 3...31 in
90  def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>;
91
92let isRV32Only = 1 in {
93def CYCLEH   : SysReg<"cycleh", 0xC80>;
94def TIMEH    : SysReg<"timeh", 0xC81>;
95def INSTRETH : SysReg<"instreth", 0xC82>;
96
97// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
98foreach i = 3...31 in
99  def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
100}
101
102//===----------------------------------------------------------------------===//
103// Supervisor Trap Setup
104//===----------------------------------------------------------------------===//
105def : SysReg<"sstatus", 0x100>;
106def : SysReg<"sie", 0x104>;
107def : SysReg<"stvec", 0x105>;
108def : SysReg<"scounteren", 0x106>;
109def : SysReg<"stimecmp", 0x14D>;
110let isRV32Only = 1 in
111def : SysReg<"stimecmph", 0x15D>;
112
113//===----------------------------------------------------------------------===//
114// Supervisor Configuration
115//===----------------------------------------------------------------------===//
116
117def : SysReg<"senvcfg", 0x10A>;
118
119//===----------------------------------------------------------------------===//
120// Supervisor Trap Handling
121//===----------------------------------------------------------------------===//
122def : SysReg<"sscratch", 0x140>;
123def : SysReg<"sepc", 0x141>;
124def : SysReg<"scause", 0x142>;
125let DeprecatedName = "sbadaddr" in
126def : SysReg<"stval", 0x143>;
127def : SysReg<"sip", 0x144>;
128
129//===----------------------------------------------------------------------===//
130// Supervisor Protection and Translation
131//===----------------------------------------------------------------------===//
132let DeprecatedName = "sptbr" in
133def : SysReg<"satp", 0x180>;
134
135//===----------------------------------------------------------------------===//
136// Debug/Trace Registers
137//===----------------------------------------------------------------------===//
138
139def : SysReg<"scontext", 0x5A8>;
140
141//===----------------------------------------------------------------------===//
142// Supervisor Count Overflow (defined in Sscofpmf)
143//===----------------------------------------------------------------------===//
144
145def : SysReg<"scountovf", 0xDA0>;
146
147//===----------------------------------------------------------------------===//
148// Hypervisor Trap Setup
149//===----------------------------------------------------------------------===//
150
151def : SysReg<"hstatus", 0x600>;
152def : SysReg<"hedeleg", 0x602>;
153def : SysReg<"hideleg", 0x603>;
154def : SysReg<"hie", 0x604>;
155def : SysReg<"hcounteren", 0x606>;
156def : SysReg<"hgeie", 0x607>;
157
158//===----------------------------------------------------------------------===//
159// Hypervisor Trap Handling
160//===----------------------------------------------------------------------===//
161
162def : SysReg<"htval", 0x643>;
163def : SysReg<"hip", 0x644>;
164def : SysReg<"hvip", 0x645>;
165def : SysReg<"htinst", 0x64A>;
166def : SysReg<"hgeip", 0xE12>;
167
168//===----------------------------------------------------------------------===//
169// Hypervisor Configuration
170//===----------------------------------------------------------------------===//
171
172def : SysReg<"henvcfg", 0x60A>;
173let isRV32Only = 1 in
174def : SysReg<"henvcfgh", 0x61A>;
175
176//===----------------------------------------------------------------------===//
177// Hypervisor Protection and Translation
178//===----------------------------------------------------------------------===//
179
180def : SysReg<"hgatp", 0x680>;
181
182//===----------------------------------------------------------------------===//
183// Debug/Trace Registers
184//===----------------------------------------------------------------------===//
185
186def : SysReg<"hcontext", 0x6A8>;
187
188//===----------------------------------------------------------------------===//
189// Hypervisor Counter/Timer Virtualization Registers
190//===----------------------------------------------------------------------===//
191
192def : SysReg<"htimedelta", 0x605>;
193let isRV32Only = 1 in
194def : SysReg<"htimedeltah", 0x615>;
195
196//===----------------------------------------------------------------------===//
197// Virtual Supervisor Registers
198//===----------------------------------------------------------------------===//
199
200def : SysReg<"vsstatus", 0x200>;
201def : SysReg<"vsie", 0x204>;
202def : SysReg<"vstvec", 0x205>;
203def : SysReg<"vsscratch", 0x240>;
204def : SysReg<"vsepc", 0x241>;
205def : SysReg<"vscause", 0x242>;
206def : SysReg<"vstval", 0x243>;
207def : SysReg<"vsip", 0x244>;
208def : SysReg<"vstimecmp", 0x24D>;
209let isRV32Only = 1 in
210def : SysReg<"vstimecmph", 0x25D>;
211def : SysReg<"vsatp", 0x280>;
212
213//===----------------------------------------------------------------------===//
214// Machine Information Registers
215//===----------------------------------------------------------------------===//
216
217def : SysReg<"mvendorid", 0xF11>;
218def : SysReg<"marchid", 0xF12>;
219def : SysReg<"mimpid", 0xF13>;
220def : SysReg<"mhartid", 0xF14>;
221def : SysReg<"mconfigptr", 0xF15>;
222
223//===----------------------------------------------------------------------===//
224// Machine Trap Setup
225//===----------------------------------------------------------------------===//
226def : SysReg<"mstatus", 0x300>;
227def : SysReg<"misa", 0x301>;
228def : SysReg<"medeleg", 0x302>;
229def : SysReg<"mideleg", 0x303>;
230def : SysReg<"mie", 0x304>;
231def : SysReg<"mtvec", 0x305>;
232def : SysReg<"mcounteren", 0x306>;
233let isRV32Only = 1 in
234def : SysReg<"mstatush", 0x310>;
235
236//===----------------------------------------------------------------------===//
237// Machine Trap Handling
238//===----------------------------------------------------------------------===//
239def : SysReg<"mscratch", 0x340>;
240def : SysReg<"mepc", 0x341>;
241def : SysReg<"mcause", 0x342>;
242let DeprecatedName = "mbadaddr" in
243def : SysReg<"mtval", 0x343>;
244def : SysReg<"mip", 0x344>;
245def : SysReg<"mtinst", 0x34A>;
246def : SysReg<"mtval2", 0x34B>;
247
248//===----------------------------------------------------------------------===//
249// Machine Configuration
250//===----------------------------------------------------------------------===//
251
252def : SysReg<"menvcfg", 0x30A>;
253let isRV32Only = 1 in
254def : SysReg<"menvcfgh", 0x31A>;
255def : SysReg<"mseccfg", 0x747>;
256let isRV32Only = 1 in
257def : SysReg<"mseccfgh", 0x757>;
258
259//===----------------------------------------------------------------------===//
260// Machine Protection and Translation
261//===----------------------------------------------------------------------===//
262
263// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
264foreach i = 0...15 in {
265  let isRV32Only = !and(i, 1) in
266  def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
267}
268
269// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
270foreach i = 0...63 in
271  def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
272
273//===----------------------------------------------------------------------===//
274// Machine Counter and Timers
275//===----------------------------------------------------------------------===//
276def : SysReg<"mcycle", 0xB00>;
277def : SysReg<"minstret", 0xB02>;
278
279// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
280foreach i = 3...31 in
281  def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>;
282
283let isRV32Only = 1 in {
284def: SysReg<"mcycleh", 0xB80>;
285def: SysReg<"minstreth", 0xB82>;
286
287// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
288foreach i = 3...31 in
289  def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
290}
291
292//===----------------------------------------------------------------------===//
293// Machine Counter Setup
294//===----------------------------------------------------------------------===//
295let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
296def : SysReg<"mcountinhibit", 0x320>;
297
298// mhpmevent3-mhpmevent31 at 0x323-0x33F.
299foreach i = 3...31 in
300  def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
301
302// mhpmevent3h-mhpmevent31h at 0x723-0x73F
303foreach i = 3...31 in {
304  let isRV32Only = 1 in
305  def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
306}
307
308//===----------------------------------------------------------------------===//
309// Debug/ Trace Registers (shared with Debug Mode)
310//===----------------------------------------------------------------------===//
311def : SysReg<"tselect", 0x7A0>;
312def : SysReg<"tdata1", 0x7A1>;
313def : SysReg<"tdata2", 0x7A2>;
314def : SysReg<"tdata3", 0x7A3>;
315def : SysReg<"mcontext", 0x7A8>;
316
317//===----------------------------------------------------------------------===//
318// Debug Mode Registers
319//===----------------------------------------------------------------------===//
320def : SysReg<"dcsr", 0x7B0>;
321def : SysReg<"dpc", 0x7B1>;
322
323// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
324// drafts of the RISC-V debug spec
325let AltName = "dscratch" in
326def : SysReg<"dscratch0", 0x7B2>;
327def : SysReg<"dscratch1", 0x7B3>;
328
329//===----------------------------------------------------------------------===//
330// User Vector CSRs
331//===----------------------------------------------------------------------===//
332def : SysReg<"vstart", 0x008>;
333def : SysReg<"vxsat", 0x009>;
334def SysRegVXRM : SysReg<"vxrm", 0x00A>;
335def : SysReg<"vcsr", 0x00F>;
336def SysRegVL : SysReg<"vl", 0xC20>;
337def : SysReg<"vtype", 0xC21>;
338def SysRegVLENB: SysReg<"vlenb", 0xC22>;
339
340//===----------------------------------------------------------------------===//
341// State Enable Extension (Smstateen)
342//===----------------------------------------------------------------------===//
343
344// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
345// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
346// and hstateen0h-hstateen3h at 0x61C-0x61F.
347foreach i = 0...3 in {
348  def : SysReg<"sstateen"#i, !add(0x10C, i)>;
349  def : SysReg<"mstateen"#i, !add(0x30C, i)>;
350  let isRV32Only = 1 in
351  def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
352  def : SysReg<"hstateen"#i, !add(0x60C, i)>;
353  let isRV32Only = 1 in
354  def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
355}
356
357//===-----------------------------------------------
358// Entropy Source CSR
359//===-----------------------------------------------
360
361def SEED : SysReg<"seed", 0x015>;
362
363//===-----------------------------------------------
364// Advanced Interrupt Architecture
365//===-----------------------------------------------
366
367// Machine-level CSRs
368def : SysReg<"miselect", 0x350>;
369def : SysReg<"mireg", 0x351>;
370def : SysReg<"mtopei", 0x35C>;
371def : SysReg<"mtopi", 0xFB0>;
372def : SysReg<"mvien", 0x308>;
373def : SysReg<"mvip", 0x309>;
374let isRV32Only = 1 in {
375def : SysReg<"midelegh", 0x313>;
376def : SysReg<"mieh", 0x314>;
377def : SysReg<"mvienh", 0x318>;
378def : SysReg<"mviph", 0x319>;
379def : SysReg<"miph", 0x354>;
380} // isRV32Only
381
382// Supervisor-level CSRs
383def : SysReg<"siselect", 0x150>;
384def : SysReg<"sireg", 0x151>;
385def : SysReg<"stopei", 0x15C>;
386def : SysReg<"stopi", 0xDB0>;
387let isRV32Only = 1 in {
388def : SysReg<"sieh", 0x114>;
389def : SysReg<"siph", 0x154>;
390} // isRV32Only
391
392// Hypervisor and VS CSRs
393def : SysReg<"hvien", 0x608>;
394def : SysReg<"hvictl", 0x609>;
395def : SysReg<"hviprio1", 0x646>;
396def : SysReg<"hviprio2", 0x647>;
397def : SysReg<"vsiselect", 0x250>;
398def : SysReg<"vsireg", 0x251>;
399def : SysReg<"vstopei", 0x25C>;
400def : SysReg<"vstopi", 0xEB0>;
401let isRV32Only = 1 in {
402def : SysReg<"hidelegh", 0x613>;
403def : SysReg<"hvienh", 0x618>;
404def : SysReg<"hviph", 0x655>;
405def : SysReg<"hviprio1h", 0x656>;
406def : SysReg<"hviprio2h", 0x657>;
407def : SysReg<"vsieh", 0x214>;
408def : SysReg<"vsiph", 0x254>;
409} // isRV32Only
410
411// Jump Vector Table CSR
412//===-----------------------------------------------
413
414def : SysReg<"jvt", 0x017>;
415