104eeddc0SDimitry Andric//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the symbolic operands permitted for various kinds of 100b57cec5SDimitry Andric// RISC-V system instruction. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andricinclude "llvm/TableGen/SearchableTable.td" 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 170b57cec5SDimitry Andric// CSR (control and status register read/write) instruction options. 180b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 190b57cec5SDimitry Andric 200b57cec5SDimitry Andricclass SysReg<string name, bits<12> op> { 210b57cec5SDimitry Andric string Name = name; 22647cbc5dSDimitry Andric // A maximum of one alias is supported right now. 23647cbc5dSDimitry Andric string AltName = name; 24647cbc5dSDimitry Andric // A maximum of one deprecated name is supported right now. Unlike the 25647cbc5dSDimitry Andric // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is 26647cbc5dSDimitry Andric // used to encourage software to migrate away from the name. 27fe6060f1SDimitry Andric string DeprecatedName = ""; 28fe6060f1SDimitry Andric bits<12> Encoding = op; 290b57cec5SDimitry Andric // FIXME: add these additional fields when needed. 300b57cec5SDimitry Andric // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. 310b57cec5SDimitry Andric // Privilege Mode: User = 0, System = 1 or Machine = 3. 320b57cec5SDimitry Andric // bits<2> ReadWrite = op{11 - 10}; 330b57cec5SDimitry Andric // bits<2> XMode = op{9 - 8}; 340b57cec5SDimitry Andric // Check Extra field name and what bits 7-6 correspond to. 350b57cec5SDimitry Andric // bits<2> Extra = op{7 - 6}; 360b57cec5SDimitry Andric // Register number without the privilege bits. 370b57cec5SDimitry Andric // bits<6> Number = op{5 - 0}; 380b57cec5SDimitry Andric code FeaturesRequired = [{ {} }]; 390b57cec5SDimitry Andric bit isRV32Only = 0; 400b57cec5SDimitry Andric} 410b57cec5SDimitry Andric 420b57cec5SDimitry Andricdef SysRegsList : GenericTable { 430b57cec5SDimitry Andric let FilterClass = "SysReg"; 440b57cec5SDimitry Andric // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. 45fe6060f1SDimitry Andric let Fields = [ 46647cbc5dSDimitry Andric "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired", 47fe6060f1SDimitry Andric "isRV32Only", 48fe6060f1SDimitry Andric ]; 490b57cec5SDimitry Andric 500b57cec5SDimitry Andric let PrimaryKey = [ "Encoding" ]; 510b57cec5SDimitry Andric let PrimaryKeyName = "lookupSysRegByEncoding"; 520b57cec5SDimitry Andric} 530b57cec5SDimitry Andric 540b57cec5SDimitry Andricdef lookupSysRegByName : SearchIndex { 550b57cec5SDimitry Andric let Table = SysRegsList; 560b57cec5SDimitry Andric let Key = [ "Name" ]; 570b57cec5SDimitry Andric} 580b57cec5SDimitry Andric 59647cbc5dSDimitry Andricdef lookupSysRegByAltName : SearchIndex { 60647cbc5dSDimitry Andric let Table = SysRegsList; 61647cbc5dSDimitry Andric let Key = [ "AltName" ]; 62647cbc5dSDimitry Andric} 63647cbc5dSDimitry Andric 64fe6060f1SDimitry Andricdef lookupSysRegByDeprecatedName : SearchIndex { 65fe6060f1SDimitry Andric let Table = SysRegsList; 66fe6060f1SDimitry Andric let Key = [ "DeprecatedName" ]; 67fe6060f1SDimitry Andric} 68fe6060f1SDimitry Andric 690b57cec5SDimitry Andric// The following CSR encodings match those given in Tables 2.2, 7006c3fb27SDimitry Andric// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual 710b57cec5SDimitry Andric// Volume II: Privileged Architecture. 720b57cec5SDimitry Andric 7304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 740b57cec5SDimitry Andric// User Floating-Point CSRs 7504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 760b57cec5SDimitry Andric 77fe6060f1SDimitry Andricdef SysRegFFLAGS : SysReg<"fflags", 0x001>; 78fe6060f1SDimitry Andricdef SysRegFRM : SysReg<"frm", 0x002>; 79fe6060f1SDimitry Andricdef SysRegFCSR : SysReg<"fcsr", 0x003>; 800b57cec5SDimitry Andric 8104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 820b57cec5SDimitry Andric// User Counter/Timers 8304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 840b57cec5SDimitry Andricdef CYCLE : SysReg<"cycle", 0xC00>; 850b57cec5SDimitry Andricdef TIME : SysReg<"time", 0xC01>; 860b57cec5SDimitry Andricdef INSTRET : SysReg<"instret", 0xC02>; 870b57cec5SDimitry Andric 8804eeddc0SDimitry Andric// hpmcounter3-hpmcounter31 at 0xC03-0xC1F. 8904eeddc0SDimitry Andricforeach i = 3...31 in 9004eeddc0SDimitry Andric def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>; 910b57cec5SDimitry Andric 920b57cec5SDimitry Andriclet isRV32Only = 1 in { 930b57cec5SDimitry Andricdef CYCLEH : SysReg<"cycleh", 0xC80>; 940b57cec5SDimitry Andricdef TIMEH : SysReg<"timeh", 0xC81>; 950b57cec5SDimitry Andricdef INSTRETH : SysReg<"instreth", 0xC82>; 960b57cec5SDimitry Andric 9704eeddc0SDimitry Andric// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F. 9804eeddc0SDimitry Andricforeach i = 3...31 in 9904eeddc0SDimitry Andric def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>; 1000b57cec5SDimitry Andric} 1010b57cec5SDimitry Andric 10204eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 1030b57cec5SDimitry Andric// Supervisor Trap Setup 10404eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 1050b57cec5SDimitry Andricdef : SysReg<"sstatus", 0x100>; 1060b57cec5SDimitry Andricdef : SysReg<"sie", 0x104>; 1070b57cec5SDimitry Andricdef : SysReg<"stvec", 0x105>; 1080b57cec5SDimitry Andricdef : SysReg<"scounteren", 0x106>; 10904eeddc0SDimitry Andricdef : SysReg<"stimecmp", 0x14D>; 11004eeddc0SDimitry Andriclet isRV32Only = 1 in 11104eeddc0SDimitry Andricdef : SysReg<"stimecmph", 0x15D>; 1120b57cec5SDimitry Andric 11304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 11404eeddc0SDimitry Andric// Supervisor Configuration 11504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 11604eeddc0SDimitry Andric 11704eeddc0SDimitry Andricdef : SysReg<"senvcfg", 0x10A>; 11804eeddc0SDimitry Andric 11904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 1200b57cec5SDimitry Andric// Supervisor Trap Handling 12104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 1220b57cec5SDimitry Andricdef : SysReg<"sscratch", 0x140>; 1230b57cec5SDimitry Andricdef : SysReg<"sepc", 0x141>; 1240b57cec5SDimitry Andricdef : SysReg<"scause", 0x142>; 125fe6060f1SDimitry Andriclet DeprecatedName = "sbadaddr" in 1260b57cec5SDimitry Andricdef : SysReg<"stval", 0x143>; 1270b57cec5SDimitry Andricdef : SysReg<"sip", 0x144>; 1280b57cec5SDimitry Andric 12904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 1300b57cec5SDimitry Andric// Supervisor Protection and Translation 13104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 132fe6060f1SDimitry Andriclet DeprecatedName = "sptbr" in 1330b57cec5SDimitry Andricdef : SysReg<"satp", 0x180>; 1340b57cec5SDimitry Andric 13504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 13604eeddc0SDimitry Andric// Debug/Trace Registers 13704eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 13804eeddc0SDimitry Andric 13904eeddc0SDimitry Andricdef : SysReg<"scontext", 0x5A8>; 14004eeddc0SDimitry Andric 14104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 14204eeddc0SDimitry Andric// Supervisor Count Overflow (defined in Sscofpmf) 14304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 14404eeddc0SDimitry Andric 14504eeddc0SDimitry Andricdef : SysReg<"scountovf", 0xDA0>; 14604eeddc0SDimitry Andric 14704eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 14804eeddc0SDimitry Andric// Hypervisor Trap Setup 14904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 15004eeddc0SDimitry Andric 15104eeddc0SDimitry Andricdef : SysReg<"hstatus", 0x600>; 15204eeddc0SDimitry Andricdef : SysReg<"hedeleg", 0x602>; 15304eeddc0SDimitry Andricdef : SysReg<"hideleg", 0x603>; 15404eeddc0SDimitry Andricdef : SysReg<"hie", 0x604>; 15504eeddc0SDimitry Andricdef : SysReg<"hcounteren", 0x606>; 15604eeddc0SDimitry Andricdef : SysReg<"hgeie", 0x607>; 15704eeddc0SDimitry Andric 15804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 15904eeddc0SDimitry Andric// Hypervisor Trap Handling 16004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 16104eeddc0SDimitry Andric 16204eeddc0SDimitry Andricdef : SysReg<"htval", 0x643>; 16304eeddc0SDimitry Andricdef : SysReg<"hip", 0x644>; 16404eeddc0SDimitry Andricdef : SysReg<"hvip", 0x645>; 16504eeddc0SDimitry Andricdef : SysReg<"htinst", 0x64A>; 16604eeddc0SDimitry Andricdef : SysReg<"hgeip", 0xE12>; 16704eeddc0SDimitry Andric 16804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 16904eeddc0SDimitry Andric// Hypervisor Configuration 17004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 17104eeddc0SDimitry Andric 17204eeddc0SDimitry Andricdef : SysReg<"henvcfg", 0x60A>; 17304eeddc0SDimitry Andriclet isRV32Only = 1 in 17404eeddc0SDimitry Andricdef : SysReg<"henvcfgh", 0x61A>; 17504eeddc0SDimitry Andric 17604eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 17704eeddc0SDimitry Andric// Hypervisor Protection and Translation 17804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 17904eeddc0SDimitry Andric 18004eeddc0SDimitry Andricdef : SysReg<"hgatp", 0x680>; 18104eeddc0SDimitry Andric 18204eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 18304eeddc0SDimitry Andric// Debug/Trace Registers 18404eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 18504eeddc0SDimitry Andric 18604eeddc0SDimitry Andricdef : SysReg<"hcontext", 0x6A8>; 18704eeddc0SDimitry Andric 18804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 18904eeddc0SDimitry Andric// Hypervisor Counter/Timer Virtualization Registers 19004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 19104eeddc0SDimitry Andric 19204eeddc0SDimitry Andricdef : SysReg<"htimedelta", 0x605>; 19304eeddc0SDimitry Andriclet isRV32Only = 1 in 19404eeddc0SDimitry Andricdef : SysReg<"htimedeltah", 0x615>; 19504eeddc0SDimitry Andric 19604eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 19704eeddc0SDimitry Andric// Virtual Supervisor Registers 19804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 19904eeddc0SDimitry Andric 20004eeddc0SDimitry Andricdef : SysReg<"vsstatus", 0x200>; 20104eeddc0SDimitry Andricdef : SysReg<"vsie", 0x204>; 20204eeddc0SDimitry Andricdef : SysReg<"vstvec", 0x205>; 20304eeddc0SDimitry Andricdef : SysReg<"vsscratch", 0x240>; 20404eeddc0SDimitry Andricdef : SysReg<"vsepc", 0x241>; 20504eeddc0SDimitry Andricdef : SysReg<"vscause", 0x242>; 20604eeddc0SDimitry Andricdef : SysReg<"vstval", 0x243>; 20704eeddc0SDimitry Andricdef : SysReg<"vsip", 0x244>; 20804eeddc0SDimitry Andricdef : SysReg<"vstimecmp", 0x24D>; 20904eeddc0SDimitry Andriclet isRV32Only = 1 in 21004eeddc0SDimitry Andricdef : SysReg<"vstimecmph", 0x25D>; 21104eeddc0SDimitry Andricdef : SysReg<"vsatp", 0x280>; 21204eeddc0SDimitry Andric 21304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2140b57cec5SDimitry Andric// Machine Information Registers 21504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2160b57cec5SDimitry Andric 2170b57cec5SDimitry Andricdef : SysReg<"mvendorid", 0xF11>; 2180b57cec5SDimitry Andricdef : SysReg<"marchid", 0xF12>; 2190b57cec5SDimitry Andricdef : SysReg<"mimpid", 0xF13>; 2200b57cec5SDimitry Andricdef : SysReg<"mhartid", 0xF14>; 22104eeddc0SDimitry Andricdef : SysReg<"mconfigptr", 0xF15>; 2220b57cec5SDimitry Andric 22304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2240b57cec5SDimitry Andric// Machine Trap Setup 22504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2260b57cec5SDimitry Andricdef : SysReg<"mstatus", 0x300>; 2270b57cec5SDimitry Andricdef : SysReg<"misa", 0x301>; 2280b57cec5SDimitry Andricdef : SysReg<"medeleg", 0x302>; 2290b57cec5SDimitry Andricdef : SysReg<"mideleg", 0x303>; 2300b57cec5SDimitry Andricdef : SysReg<"mie", 0x304>; 2310b57cec5SDimitry Andricdef : SysReg<"mtvec", 0x305>; 2320b57cec5SDimitry Andricdef : SysReg<"mcounteren", 0x306>; 23304eeddc0SDimitry Andriclet isRV32Only = 1 in 23404eeddc0SDimitry Andricdef : SysReg<"mstatush", 0x310>; 2350b57cec5SDimitry Andric 23604eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2370b57cec5SDimitry Andric// Machine Trap Handling 23804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2390b57cec5SDimitry Andricdef : SysReg<"mscratch", 0x340>; 2400b57cec5SDimitry Andricdef : SysReg<"mepc", 0x341>; 2410b57cec5SDimitry Andricdef : SysReg<"mcause", 0x342>; 242fe6060f1SDimitry Andriclet DeprecatedName = "mbadaddr" in 2430b57cec5SDimitry Andricdef : SysReg<"mtval", 0x343>; 2440b57cec5SDimitry Andricdef : SysReg<"mip", 0x344>; 24504eeddc0SDimitry Andricdef : SysReg<"mtinst", 0x34A>; 24604eeddc0SDimitry Andricdef : SysReg<"mtval2", 0x34B>; 2470b57cec5SDimitry Andric 24804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 24904eeddc0SDimitry Andric// Machine Configuration 25004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 25104eeddc0SDimitry Andric 25204eeddc0SDimitry Andricdef : SysReg<"menvcfg", 0x30A>; 25304eeddc0SDimitry Andriclet isRV32Only = 1 in 25404eeddc0SDimitry Andricdef : SysReg<"menvcfgh", 0x31A>; 25504eeddc0SDimitry Andricdef : SysReg<"mseccfg", 0x747>; 25604eeddc0SDimitry Andriclet isRV32Only = 1 in 25704eeddc0SDimitry Andricdef : SysReg<"mseccfgh", 0x757>; 25804eeddc0SDimitry Andric 25904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2600b57cec5SDimitry Andric// Machine Protection and Translation 26104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 26204eeddc0SDimitry Andric 26304eeddc0SDimitry Andric// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only. 26404eeddc0SDimitry Andricforeach i = 0...15 in { 26504eeddc0SDimitry Andric let isRV32Only = !and(i, 1) in 26604eeddc0SDimitry Andric def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>; 2670b57cec5SDimitry Andric} 2680b57cec5SDimitry Andric 26904eeddc0SDimitry Andric// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF. 27004eeddc0SDimitry Andricforeach i = 0...63 in 27104eeddc0SDimitry Andric def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; 2720b57cec5SDimitry Andric 27304eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2740b57cec5SDimitry Andric// Machine Counter and Timers 27504eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2760b57cec5SDimitry Andricdef : SysReg<"mcycle", 0xB00>; 2770b57cec5SDimitry Andricdef : SysReg<"minstret", 0xB02>; 2780b57cec5SDimitry Andric 27904eeddc0SDimitry Andric// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F. 28004eeddc0SDimitry Andricforeach i = 3...31 in 28104eeddc0SDimitry Andric def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>; 2820b57cec5SDimitry Andric 2830b57cec5SDimitry Andriclet isRV32Only = 1 in { 2840b57cec5SDimitry Andricdef: SysReg<"mcycleh", 0xB80>; 2850b57cec5SDimitry Andricdef: SysReg<"minstreth", 0xB82>; 2860b57cec5SDimitry Andric 28704eeddc0SDimitry Andric// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F. 28804eeddc0SDimitry Andricforeach i = 3...31 in 28904eeddc0SDimitry Andric def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>; 2900b57cec5SDimitry Andric} 2910b57cec5SDimitry Andric 29204eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 2930b57cec5SDimitry Andric// Machine Counter Setup 29404eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 295647cbc5dSDimitry Andriclet AltName = "mucounteren" in // Privileged spec v1.9.1 Name 2965ffd83dbSDimitry Andricdef : SysReg<"mcountinhibit", 0x320>; 297e8d8bef9SDimitry Andric 29804eeddc0SDimitry Andric// mhpmevent3-mhpmevent31 at 0x323-0x33F. 29904eeddc0SDimitry Andricforeach i = 3...31 in 30004eeddc0SDimitry Andric def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>; 3010b57cec5SDimitry Andric 30204eeddc0SDimitry Andric// mhpmevent3h-mhpmevent31h at 0x723-0x73F 30304eeddc0SDimitry Andricforeach i = 3...31 in { 30404eeddc0SDimitry Andric let isRV32Only = 1 in 30504eeddc0SDimitry Andric def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; 30604eeddc0SDimitry Andric} 30704eeddc0SDimitry Andric 30804eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3090b57cec5SDimitry Andric// Debug/ Trace Registers (shared with Debug Mode) 31004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3110b57cec5SDimitry Andricdef : SysReg<"tselect", 0x7A0>; 3120b57cec5SDimitry Andricdef : SysReg<"tdata1", 0x7A1>; 3130b57cec5SDimitry Andricdef : SysReg<"tdata2", 0x7A2>; 3140b57cec5SDimitry Andricdef : SysReg<"tdata3", 0x7A3>; 31504eeddc0SDimitry Andricdef : SysReg<"mcontext", 0x7A8>; 3160b57cec5SDimitry Andric 31704eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3180b57cec5SDimitry Andric// Debug Mode Registers 31904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3200b57cec5SDimitry Andricdef : SysReg<"dcsr", 0x7B0>; 3210b57cec5SDimitry Andricdef : SysReg<"dpc", 0x7B1>; 3225ffd83dbSDimitry Andric 3235ffd83dbSDimitry Andric// "dscratch" is an alternative name for "dscratch0" which appeared in earlier 3245ffd83dbSDimitry Andric// drafts of the RISC-V debug spec 325647cbc5dSDimitry Andriclet AltName = "dscratch" in 3265ffd83dbSDimitry Andricdef : SysReg<"dscratch0", 0x7B2>; 3275ffd83dbSDimitry Andricdef : SysReg<"dscratch1", 0x7B3>; 3285ffd83dbSDimitry Andric 32904eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3305ffd83dbSDimitry Andric// User Vector CSRs 33104eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 3325ffd83dbSDimitry Andricdef : SysReg<"vstart", 0x008>; 3335ffd83dbSDimitry Andricdef : SysReg<"vxsat", 0x009>; 33406c3fb27SDimitry Andricdef SysRegVXRM : SysReg<"vxrm", 0x00A>; 335349cc55cSDimitry Andricdef : SysReg<"vcsr", 0x00F>; 33606c3fb27SDimitry Andricdef SysRegVL : SysReg<"vl", 0xC20>; 3375ffd83dbSDimitry Andricdef : SysReg<"vtype", 0xC21>; 3384824e7fdSDimitry Andricdef SysRegVLENB: SysReg<"vlenb", 0xC22>; 33904eeddc0SDimitry Andric 34004eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 34104eeddc0SDimitry Andric// State Enable Extension (Smstateen) 34204eeddc0SDimitry Andric//===----------------------------------------------------------------------===// 34304eeddc0SDimitry Andric 34404eeddc0SDimitry Andric// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F, 34504eeddc0SDimitry Andric// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F, 34604eeddc0SDimitry Andric// and hstateen0h-hstateen3h at 0x61C-0x61F. 34704eeddc0SDimitry Andricforeach i = 0...3 in { 34804eeddc0SDimitry Andric def : SysReg<"sstateen"#i, !add(0x10C, i)>; 34904eeddc0SDimitry Andric def : SysReg<"mstateen"#i, !add(0x30C, i)>; 35004eeddc0SDimitry Andric let isRV32Only = 1 in 35104eeddc0SDimitry Andric def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>; 35204eeddc0SDimitry Andric def : SysReg<"hstateen"#i, !add(0x60C, i)>; 35304eeddc0SDimitry Andric let isRV32Only = 1 in 35404eeddc0SDimitry Andric def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>; 35504eeddc0SDimitry Andric} 35604eeddc0SDimitry Andric 35704eeddc0SDimitry Andric//===----------------------------------------------- 35804eeddc0SDimitry Andric// Entropy Source CSR 35904eeddc0SDimitry Andric//===----------------------------------------------- 36004eeddc0SDimitry Andric 36104eeddc0SDimitry Andricdef SEED : SysReg<"seed", 0x015>; 36206c3fb27SDimitry Andric 36306c3fb27SDimitry Andric//===----------------------------------------------- 36406c3fb27SDimitry Andric// Advanced Interrupt Architecture 36506c3fb27SDimitry Andric//===----------------------------------------------- 36606c3fb27SDimitry Andric 36706c3fb27SDimitry Andric// Machine-level CSRs 36806c3fb27SDimitry Andricdef : SysReg<"miselect", 0x350>; 36906c3fb27SDimitry Andricdef : SysReg<"mireg", 0x351>; 37006c3fb27SDimitry Andricdef : SysReg<"mtopei", 0x35C>; 37106c3fb27SDimitry Andricdef : SysReg<"mtopi", 0xFB0>; 37206c3fb27SDimitry Andricdef : SysReg<"mvien", 0x308>; 37306c3fb27SDimitry Andricdef : SysReg<"mvip", 0x309>; 37406c3fb27SDimitry Andriclet isRV32Only = 1 in { 37506c3fb27SDimitry Andricdef : SysReg<"midelegh", 0x313>; 37606c3fb27SDimitry Andricdef : SysReg<"mieh", 0x314>; 37706c3fb27SDimitry Andricdef : SysReg<"mvienh", 0x318>; 37806c3fb27SDimitry Andricdef : SysReg<"mviph", 0x319>; 37906c3fb27SDimitry Andricdef : SysReg<"miph", 0x354>; 38006c3fb27SDimitry Andric} // isRV32Only 38106c3fb27SDimitry Andric 38206c3fb27SDimitry Andric// Supervisor-level CSRs 38306c3fb27SDimitry Andricdef : SysReg<"siselect", 0x150>; 38406c3fb27SDimitry Andricdef : SysReg<"sireg", 0x151>; 38506c3fb27SDimitry Andricdef : SysReg<"stopei", 0x15C>; 38606c3fb27SDimitry Andricdef : SysReg<"stopi", 0xDB0>; 38706c3fb27SDimitry Andriclet isRV32Only = 1 in { 38806c3fb27SDimitry Andricdef : SysReg<"sieh", 0x114>; 38906c3fb27SDimitry Andricdef : SysReg<"siph", 0x154>; 39006c3fb27SDimitry Andric} // isRV32Only 39106c3fb27SDimitry Andric 39206c3fb27SDimitry Andric// Hypervisor and VS CSRs 39306c3fb27SDimitry Andricdef : SysReg<"hvien", 0x608>; 39406c3fb27SDimitry Andricdef : SysReg<"hvictl", 0x609>; 39506c3fb27SDimitry Andricdef : SysReg<"hviprio1", 0x646>; 39606c3fb27SDimitry Andricdef : SysReg<"hviprio2", 0x647>; 39706c3fb27SDimitry Andricdef : SysReg<"vsiselect", 0x250>; 39806c3fb27SDimitry Andricdef : SysReg<"vsireg", 0x251>; 39906c3fb27SDimitry Andricdef : SysReg<"vstopei", 0x25C>; 40006c3fb27SDimitry Andricdef : SysReg<"vstopi", 0xEB0>; 40106c3fb27SDimitry Andriclet isRV32Only = 1 in { 40206c3fb27SDimitry Andricdef : SysReg<"hidelegh", 0x613>; 40306c3fb27SDimitry Andricdef : SysReg<"hvienh", 0x618>; 40406c3fb27SDimitry Andricdef : SysReg<"hviph", 0x655>; 40506c3fb27SDimitry Andricdef : SysReg<"hviprio1h", 0x656>; 40606c3fb27SDimitry Andricdef : SysReg<"hviprio2h", 0x657>; 40706c3fb27SDimitry Andricdef : SysReg<"vsieh", 0x214>; 40806c3fb27SDimitry Andricdef : SysReg<"vsiph", 0x254>; 40906c3fb27SDimitry Andric} // isRV32Only 41006c3fb27SDimitry Andric 41106c3fb27SDimitry Andric// Jump Vector Table CSR 41206c3fb27SDimitry Andric//===----------------------------------------------- 41306c3fb27SDimitry Andric 41406c3fb27SDimitry Andricdef : SysReg<"jvt", 0x017>; 415