1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the symbolic operands permitted for various kinds of
10// RISC-V system instruction.
11//
12//===----------------------------------------------------------------------===//
13
14include "llvm/TableGen/SearchableTable.td"
15
16//===----------------------------------------------------------------------===//
17// CSR (control and status register read/write) instruction options.
18//===----------------------------------------------------------------------===//
19
20class SysReg<string name, bits<12> op> {
21  string Name = name;
22  // A maximum of one deprecated name is supported right now. It generates a
23  // diagnostic when the name is used to encourage software to migrate away from
24  // the name.
25  string DeprecatedName = "";
26  bits<12> Encoding = op;
27  // FIXME: add these additional fields when needed.
28  // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
29  // Privilege Mode: User = 0, System = 1 or Machine = 3.
30  // bits<2> ReadWrite = op{11 - 10};
31  // bits<2> XMode = op{9 - 8};
32  // Check Extra field name and what bits 7-6 correspond to.
33  // bits<2> Extra = op{7 - 6};
34  // Register number without the privilege bits.
35  // bits<6> Number = op{5 - 0};
36  code FeaturesRequired = [{ {} }];
37  bit isRV32Only = 0;
38}
39
40def SysRegsList : GenericTable {
41  let FilterClass = "SysReg";
42  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
43  let Fields = [
44    "Name", "DeprecatedName", "Encoding", "FeaturesRequired",
45    "isRV32Only",
46  ];
47
48  let PrimaryKey = [ "Encoding" ];
49  let PrimaryKeyName = "lookupSysRegByEncoding";
50}
51
52def lookupSysRegByName : SearchIndex {
53  let Table = SysRegsList;
54  let Key = [ "Name" ];
55}
56
57def lookupSysRegByDeprecatedName : SearchIndex {
58  let Table = SysRegsList;
59  let Key = [ "DeprecatedName" ];
60}
61
62class SiFiveReg<string name, bits<12> op> : SysReg<name, op>;
63
64def SiFiveRegsList : GenericTable {
65  let FilterClass = "SiFiveReg";
66  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
67  let Fields = [
68    "Name", "DeprecatedName", "Encoding", "FeaturesRequired",
69    "isRV32Only",
70  ];
71
72  let PrimaryKey = [ "Encoding" ];
73  let PrimaryKeyName = "lookupSiFiveRegByEncoding";
74}
75
76def lookupSiFiveRegByName : SearchIndex {
77  let Table = SiFiveRegsList;
78  let Key = [ "Name" ];
79}
80
81def lookupSiFiveRegByDeprecatedName : SearchIndex {
82  let Table = SiFiveRegsList;
83  let Key = [ "DeprecatedName" ];
84}
85
86// The following CSR encodings match those given in Tables 2.2,
87// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
88// Volume II: Privileged Architecture.
89
90//===----------------------------------------------------------------------===//
91// User Floating-Point CSRs
92//===----------------------------------------------------------------------===//
93
94def SysRegFFLAGS : SysReg<"fflags", 0x001>;
95def SysRegFRM    : SysReg<"frm", 0x002>;
96def SysRegFCSR   : SysReg<"fcsr", 0x003>;
97
98//===----------------------------------------------------------------------===//
99// User Counter/Timers
100//===----------------------------------------------------------------------===//
101def CYCLE   : SysReg<"cycle", 0xC00>;
102def TIME    : SysReg<"time", 0xC01>;
103def INSTRET : SysReg<"instret", 0xC02>;
104
105// hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
106foreach i = 3...31 in
107  def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>;
108
109let isRV32Only = 1 in {
110def CYCLEH   : SysReg<"cycleh", 0xC80>;
111def TIMEH    : SysReg<"timeh", 0xC81>;
112def INSTRETH : SysReg<"instreth", 0xC82>;
113
114// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
115foreach i = 3...31 in
116  def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
117}
118
119//===----------------------------------------------------------------------===//
120// Supervisor Trap Setup
121//===----------------------------------------------------------------------===//
122def : SysReg<"sstatus", 0x100>;
123def : SysReg<"sie", 0x104>;
124def : SysReg<"stvec", 0x105>;
125def : SysReg<"scounteren", 0x106>;
126def : SysReg<"stimecmp", 0x14D>;
127let isRV32Only = 1 in
128def : SysReg<"stimecmph", 0x15D>;
129
130//===----------------------------------------------------------------------===//
131// Supervisor Configuration
132//===----------------------------------------------------------------------===//
133
134def : SysReg<"senvcfg", 0x10A>;
135
136//===----------------------------------------------------------------------===//
137// Supervisor Trap Handling
138//===----------------------------------------------------------------------===//
139def : SysReg<"sscratch", 0x140>;
140def : SysReg<"sepc", 0x141>;
141def : SysReg<"scause", 0x142>;
142let DeprecatedName = "sbadaddr" in
143def : SysReg<"stval", 0x143>;
144def : SysReg<"sip", 0x144>;
145
146//===----------------------------------------------------------------------===//
147// Supervisor Protection and Translation
148//===----------------------------------------------------------------------===//
149let DeprecatedName = "sptbr" in
150def : SysReg<"satp", 0x180>;
151
152//===----------------------------------------------------------------------===//
153// Debug/Trace Registers
154//===----------------------------------------------------------------------===//
155
156def : SysReg<"scontext", 0x5A8>;
157
158//===----------------------------------------------------------------------===//
159// Supervisor Count Overflow (defined in Sscofpmf)
160//===----------------------------------------------------------------------===//
161
162def : SysReg<"scountovf", 0xDA0>;
163
164//===----------------------------------------------------------------------===//
165// Hypervisor Trap Setup
166//===----------------------------------------------------------------------===//
167
168def : SysReg<"hstatus", 0x600>;
169def : SysReg<"hedeleg", 0x602>;
170def : SysReg<"hideleg", 0x603>;
171def : SysReg<"hie", 0x604>;
172def : SysReg<"hcounteren", 0x606>;
173def : SysReg<"hgeie", 0x607>;
174
175//===----------------------------------------------------------------------===//
176// Hypervisor Trap Handling
177//===----------------------------------------------------------------------===//
178
179def : SysReg<"htval", 0x643>;
180def : SysReg<"hip", 0x644>;
181def : SysReg<"hvip", 0x645>;
182def : SysReg<"htinst", 0x64A>;
183def : SysReg<"hgeip", 0xE12>;
184
185//===----------------------------------------------------------------------===//
186// Hypervisor Configuration
187//===----------------------------------------------------------------------===//
188
189def : SysReg<"henvcfg", 0x60A>;
190let isRV32Only = 1 in
191def : SysReg<"henvcfgh", 0x61A>;
192
193//===----------------------------------------------------------------------===//
194// Hypervisor Protection and Translation
195//===----------------------------------------------------------------------===//
196
197def : SysReg<"hgatp", 0x680>;
198
199//===----------------------------------------------------------------------===//
200// Debug/Trace Registers
201//===----------------------------------------------------------------------===//
202
203def : SysReg<"hcontext", 0x6A8>;
204
205//===----------------------------------------------------------------------===//
206// Hypervisor Counter/Timer Virtualization Registers
207//===----------------------------------------------------------------------===//
208
209def : SysReg<"htimedelta", 0x605>;
210let isRV32Only = 1 in
211def : SysReg<"htimedeltah", 0x615>;
212
213//===----------------------------------------------------------------------===//
214// Virtual Supervisor Registers
215//===----------------------------------------------------------------------===//
216
217def : SysReg<"vsstatus", 0x200>;
218def : SysReg<"vsie", 0x204>;
219def : SysReg<"vstvec", 0x205>;
220def : SysReg<"vsscratch", 0x240>;
221def : SysReg<"vsepc", 0x241>;
222def : SysReg<"vscause", 0x242>;
223def : SysReg<"vstval", 0x243>;
224def : SysReg<"vsip", 0x244>;
225def : SysReg<"vstimecmp", 0x24D>;
226let isRV32Only = 1 in
227def : SysReg<"vstimecmph", 0x25D>;
228def : SysReg<"vsatp", 0x280>;
229
230//===----------------------------------------------------------------------===//
231// Machine Information Registers
232//===----------------------------------------------------------------------===//
233
234def : SysReg<"mvendorid", 0xF11>;
235def : SysReg<"marchid", 0xF12>;
236def : SysReg<"mimpid", 0xF13>;
237def : SysReg<"mhartid", 0xF14>;
238def : SysReg<"mconfigptr", 0xF15>;
239
240//===----------------------------------------------------------------------===//
241// Machine Trap Setup
242//===----------------------------------------------------------------------===//
243def : SysReg<"mstatus", 0x300>;
244def : SysReg<"misa", 0x301>;
245def : SysReg<"medeleg", 0x302>;
246def : SysReg<"mideleg", 0x303>;
247def : SysReg<"mie", 0x304>;
248def : SysReg<"mtvec", 0x305>;
249def : SysReg<"mcounteren", 0x306>;
250let isRV32Only = 1 in
251def : SysReg<"mstatush", 0x310>;
252
253//===----------------------------------------------------------------------===//
254// Machine Trap Handling
255//===----------------------------------------------------------------------===//
256def : SysReg<"mscratch", 0x340>;
257def : SysReg<"mepc", 0x341>;
258def : SysReg<"mcause", 0x342>;
259let DeprecatedName = "mbadaddr" in
260def : SysReg<"mtval", 0x343>;
261def : SysReg<"mip", 0x344>;
262def : SysReg<"mtinst", 0x34A>;
263def : SysReg<"mtval2", 0x34B>;
264
265//===----------------------------------------------------------------------===//
266// Machine Configuration
267//===----------------------------------------------------------------------===//
268
269def : SysReg<"menvcfg", 0x30A>;
270let isRV32Only = 1 in
271def : SysReg<"menvcfgh", 0x31A>;
272def : SysReg<"mseccfg", 0x747>;
273let isRV32Only = 1 in
274def : SysReg<"mseccfgh", 0x757>;
275
276//===----------------------------------------------------------------------===//
277// Machine Protection and Translation
278//===----------------------------------------------------------------------===//
279
280// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
281foreach i = 0...15 in {
282  let isRV32Only = !and(i, 1) in
283  def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
284}
285
286// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
287foreach i = 0...63 in
288  def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
289
290//===----------------------------------------------------------------------===//
291// Machine Counter and Timers
292//===----------------------------------------------------------------------===//
293def : SysReg<"mcycle", 0xB00>;
294def : SysReg<"minstret", 0xB02>;
295
296// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
297foreach i = 3...31 in
298  def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>;
299
300let isRV32Only = 1 in {
301def: SysReg<"mcycleh", 0xB80>;
302def: SysReg<"minstreth", 0xB82>;
303
304// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
305foreach i = 3...31 in
306  def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
307}
308
309//===----------------------------------------------------------------------===//
310// Machine Counter Setup
311//===----------------------------------------------------------------------===//
312let DeprecatedName = "mucounteren" in // Privileged spec v1.9.1 Name
313def : SysReg<"mcountinhibit", 0x320>;
314
315// mhpmevent3-mhpmevent31 at 0x323-0x33F.
316foreach i = 3...31 in
317  def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
318
319// mhpmevent3h-mhpmevent31h at 0x723-0x73F
320foreach i = 3...31 in {
321  let isRV32Only = 1 in
322  def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
323}
324
325//===----------------------------------------------------------------------===//
326// SiFive Custom Machine Mode Registers
327//===----------------------------------------------------------------------===//
328
329let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in {
330def : SiFiveReg<"mnscratch", 0x350>;
331def : SiFiveReg<"mnepc", 0x351>;
332def : SiFiveReg<"mncause", 0x352>;
333def : SiFiveReg<"mnstatus", 0x353>;
334def : SiFiveReg<"mbpm", 0x7C0>;
335def : SiFiveReg<"mfd", 0x7C1>;
336def : SiFiveReg<"mpd", 0x7C8>;
337}
338
339//===----------------------------------------------------------------------===//
340// Debug/ Trace Registers (shared with Debug Mode)
341//===----------------------------------------------------------------------===//
342def : SysReg<"tselect", 0x7A0>;
343def : SysReg<"tdata1", 0x7A1>;
344def : SysReg<"tdata2", 0x7A2>;
345def : SysReg<"tdata3", 0x7A3>;
346def : SysReg<"mcontext", 0x7A8>;
347
348//===----------------------------------------------------------------------===//
349// Debug Mode Registers
350//===----------------------------------------------------------------------===//
351def : SysReg<"dcsr", 0x7B0>;
352def : SysReg<"dpc", 0x7B1>;
353
354// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
355// drafts of the RISC-V debug spec
356let DeprecatedName = "dscratch" in
357def : SysReg<"dscratch0", 0x7B2>;
358def : SysReg<"dscratch1", 0x7B3>;
359
360//===----------------------------------------------------------------------===//
361// User Vector CSRs
362//===----------------------------------------------------------------------===//
363def : SysReg<"vstart", 0x008>;
364def : SysReg<"vxsat", 0x009>;
365def SysRegVXRM : SysReg<"vxrm", 0x00A>;
366def : SysReg<"vcsr", 0x00F>;
367def SysRegVL : SysReg<"vl", 0xC20>;
368def : SysReg<"vtype", 0xC21>;
369def SysRegVLENB: SysReg<"vlenb", 0xC22>;
370
371//===----------------------------------------------------------------------===//
372// State Enable Extension (Smstateen)
373//===----------------------------------------------------------------------===//
374
375// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
376// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
377// and hstateen0h-hstateen3h at 0x61C-0x61F.
378foreach i = 0...3 in {
379  def : SysReg<"sstateen"#i, !add(0x10C, i)>;
380  def : SysReg<"mstateen"#i, !add(0x30C, i)>;
381  let isRV32Only = 1 in
382  def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
383  def : SysReg<"hstateen"#i, !add(0x60C, i)>;
384  let isRV32Only = 1 in
385  def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
386}
387
388//===-----------------------------------------------
389// Entropy Source CSR
390//===-----------------------------------------------
391
392def SEED : SysReg<"seed", 0x015>;
393
394//===-----------------------------------------------
395// Advanced Interrupt Architecture
396//===-----------------------------------------------
397
398// Machine-level CSRs
399def : SysReg<"miselect", 0x350>;
400def : SysReg<"mireg", 0x351>;
401def : SysReg<"mtopei", 0x35C>;
402def : SysReg<"mtopi", 0xFB0>;
403def : SysReg<"mvien", 0x308>;
404def : SysReg<"mvip", 0x309>;
405let isRV32Only = 1 in {
406def : SysReg<"midelegh", 0x313>;
407def : SysReg<"mieh", 0x314>;
408def : SysReg<"mvienh", 0x318>;
409def : SysReg<"mviph", 0x319>;
410def : SysReg<"miph", 0x354>;
411} // isRV32Only
412
413// Supervisor-level CSRs
414def : SysReg<"siselect", 0x150>;
415def : SysReg<"sireg", 0x151>;
416def : SysReg<"stopei", 0x15C>;
417def : SysReg<"stopi", 0xDB0>;
418let isRV32Only = 1 in {
419def : SysReg<"sieh", 0x114>;
420def : SysReg<"siph", 0x154>;
421} // isRV32Only
422
423// Hypervisor and VS CSRs
424def : SysReg<"hvien", 0x608>;
425def : SysReg<"hvictl", 0x609>;
426def : SysReg<"hviprio1", 0x646>;
427def : SysReg<"hviprio2", 0x647>;
428def : SysReg<"vsiselect", 0x250>;
429def : SysReg<"vsireg", 0x251>;
430def : SysReg<"vstopei", 0x25C>;
431def : SysReg<"vstopi", 0xEB0>;
432let isRV32Only = 1 in {
433def : SysReg<"hidelegh", 0x613>;
434def : SysReg<"hvienh", 0x618>;
435def : SysReg<"hviph", 0x655>;
436def : SysReg<"hviprio1h", 0x656>;
437def : SysReg<"hviprio2h", 0x657>;
438def : SysReg<"vsieh", 0x214>;
439def : SysReg<"vsiph", 0x254>;
440} // isRV32Only
441
442// Jump Vector Table CSR
443//===-----------------------------------------------
444
445def : SysReg<"jvt", 0x017>;
446