1//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the symbolic operands permitted for various kinds of
10// RISC-V system instruction.
11//
12//===----------------------------------------------------------------------===//
13
14include "llvm/TableGen/SearchableTable.td"
15
16//===----------------------------------------------------------------------===//
17// CSR (control and status register read/write) instruction options.
18//===----------------------------------------------------------------------===//
19
20class SysReg<string name, bits<12> op> {
21  string Name = name;
22  bits<12> Encoding = op;
23  // A maximum of one alias is supported right now.
24  string AltName = name;
25  // FIXME: add these additional fields when needed.
26  // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
27  // Privilege Mode: User = 0, System = 1 or Machine = 3.
28  // bits<2> ReadWrite = op{11 - 10};
29  // bits<2> XMode = op{9 - 8};
30  // Check Extra field name and what bits 7-6 correspond to.
31  // bits<2> Extra = op{7 - 6};
32  // Register number without the privilege bits.
33  // bits<6> Number = op{5 - 0};
34  code FeaturesRequired = [{ {} }];
35  bit isRV32Only = 0;
36}
37
38def SysRegsList : GenericTable {
39  let FilterClass = "SysReg";
40  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
41  let Fields = [ "Name", "Encoding", "AltName", "FeaturesRequired", "isRV32Only" ];
42
43  let PrimaryKey = [ "Encoding" ];
44  let PrimaryKeyName = "lookupSysRegByEncoding";
45}
46
47def lookupSysRegByName : SearchIndex {
48  let Table = SysRegsList;
49  let Key = [ "Name" ];
50}
51
52def lookupSysRegByAltName : SearchIndex {
53  let Table = SysRegsList;
54  let Key = [ "AltName" ];
55}
56
57// The following CSR encodings match those given in Tables 2.2,
58// 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
59// Volume II: Privileged Architecture.
60
61//===--------------------------
62// User Trap Setup
63//===--------------------------
64def : SysReg<"ustatus", 0x000>;
65def : SysReg<"uie", 0x004>;
66def : SysReg<"utvec", 0x005>;
67
68//===--------------------------
69// User Trap Handling
70//===--------------------------
71def : SysReg<"uscratch", 0x040>;
72def : SysReg<"uepc", 0x041>;
73def : SysReg<"ucause", 0x042>;
74def : SysReg<"utval", 0x043>;
75def : SysReg<"uip", 0x044>;
76
77//===--------------------------
78// User Floating-Point CSRs
79//===--------------------------
80
81def FFLAGS : SysReg<"fflags", 0x001>;
82def FRM    : SysReg<"frm", 0x002>;
83def FCSR   : SysReg<"fcsr", 0x003>;
84
85//===--------------------------
86// User Counter/Timers
87//===--------------------------
88def CYCLE   : SysReg<"cycle", 0xC00>;
89def TIME    : SysReg<"time", 0xC01>;
90def INSTRET : SysReg<"instret", 0xC02>;
91
92def : SysReg<"hpmcounter3", 0xC03>;
93def : SysReg<"hpmcounter4", 0xC04>;
94def : SysReg<"hpmcounter5", 0xC05>;
95def : SysReg<"hpmcounter6", 0xC06>;
96def : SysReg<"hpmcounter7", 0xC07>;
97def : SysReg<"hpmcounter8", 0xC08>;
98def : SysReg<"hpmcounter9", 0xC09>;
99def : SysReg<"hpmcounter10", 0xC0A>;
100def : SysReg<"hpmcounter11", 0xC0B>;
101def : SysReg<"hpmcounter12", 0xC0C>;
102def : SysReg<"hpmcounter13", 0xC0D>;
103def : SysReg<"hpmcounter14", 0xC0E>;
104def : SysReg<"hpmcounter15", 0xC0F>;
105def : SysReg<"hpmcounter16", 0xC10>;
106def : SysReg<"hpmcounter17", 0xC11>;
107def : SysReg<"hpmcounter18", 0xC12>;
108def : SysReg<"hpmcounter19", 0xC13>;
109def : SysReg<"hpmcounter20", 0xC14>;
110def : SysReg<"hpmcounter21", 0xC15>;
111def : SysReg<"hpmcounter22", 0xC16>;
112def : SysReg<"hpmcounter23", 0xC17>;
113def : SysReg<"hpmcounter24", 0xC18>;
114def : SysReg<"hpmcounter25", 0xC19>;
115def : SysReg<"hpmcounter26", 0xC1A>;
116def : SysReg<"hpmcounter27", 0xC1B>;
117def : SysReg<"hpmcounter28", 0xC1C>;
118def : SysReg<"hpmcounter29", 0xC1D>;
119def : SysReg<"hpmcounter30", 0xC1E>;
120def : SysReg<"hpmcounter31", 0xC1F>;
121
122let isRV32Only = 1 in {
123def CYCLEH   : SysReg<"cycleh", 0xC80>;
124def TIMEH    : SysReg<"timeh", 0xC81>;
125def INSTRETH : SysReg<"instreth", 0xC82>;
126
127def: SysReg<"hpmcounter3h", 0xC83>;
128def: SysReg<"hpmcounter4h", 0xC84>;
129def: SysReg<"hpmcounter5h", 0xC85>;
130def: SysReg<"hpmcounter6h", 0xC86>;
131def: SysReg<"hpmcounter7h", 0xC87>;
132def: SysReg<"hpmcounter8h", 0xC88>;
133def: SysReg<"hpmcounter9h", 0xC89>;
134def: SysReg<"hpmcounter10h", 0xC8A>;
135def: SysReg<"hpmcounter11h", 0xC8B>;
136def: SysReg<"hpmcounter12h", 0xC8C>;
137def: SysReg<"hpmcounter13h", 0xC8D>;
138def: SysReg<"hpmcounter14h", 0xC8E>;
139def: SysReg<"hpmcounter15h", 0xC8F>;
140def: SysReg<"hpmcounter16h", 0xC90>;
141def: SysReg<"hpmcounter17h", 0xC91>;
142def: SysReg<"hpmcounter18h", 0xC92>;
143def: SysReg<"hpmcounter19h", 0xC93>;
144def: SysReg<"hpmcounter20h", 0xC94>;
145def: SysReg<"hpmcounter21h", 0xC95>;
146def: SysReg<"hpmcounter22h", 0xC96>;
147def: SysReg<"hpmcounter23h", 0xC97>;
148def: SysReg<"hpmcounter24h", 0xC98>;
149def: SysReg<"hpmcounter25h", 0xC99>;
150def: SysReg<"hpmcounter26h", 0xC9A>;
151def: SysReg<"hpmcounter27h", 0xC9B>;
152def: SysReg<"hpmcounter28h", 0xC9C>;
153def: SysReg<"hpmcounter29h", 0xC9D>;
154def: SysReg<"hpmcounter30h", 0xC9E>;
155def: SysReg<"hpmcounter31h", 0xC9F>;
156}
157
158//===--------------------------
159// Supervisor Trap Setup
160//===--------------------------
161def : SysReg<"sstatus", 0x100>;
162def : SysReg<"sedeleg", 0x102>;
163def : SysReg<"sideleg", 0x103>;
164def : SysReg<"sie", 0x104>;
165def : SysReg<"stvec", 0x105>;
166def : SysReg<"scounteren", 0x106>;
167
168//===--------------------------
169// Supervisor Trap Handling
170//===--------------------------
171def : SysReg<"sscratch", 0x140>;
172def : SysReg<"sepc", 0x141>;
173def : SysReg<"scause", 0x142>;
174def : SysReg<"stval", 0x143>;
175def : SysReg<"sip", 0x144>;
176
177//===-------------------------------------
178// Supervisor Protection and Translation
179//===-------------------------------------
180def : SysReg<"satp", 0x180>;
181
182//===-----------------------------
183// Machine Information Registers
184//===-----------------------------
185
186def : SysReg<"mvendorid", 0xF11>;
187def : SysReg<"marchid", 0xF12>;
188def : SysReg<"mimpid", 0xF13>;
189def : SysReg<"mhartid", 0xF14>;
190
191//===-----------------------------
192// Machine Trap Setup
193//===-----------------------------
194def : SysReg<"mstatus", 0x300>;
195def : SysReg<"misa", 0x301>;
196def : SysReg<"medeleg", 0x302>;
197def : SysReg<"mideleg", 0x303>;
198def : SysReg<"mie", 0x304>;
199def : SysReg<"mtvec", 0x305>;
200def : SysReg<"mcounteren", 0x306>;
201
202//===-----------------------------
203// Machine Trap Handling
204//===-----------------------------
205def : SysReg<"mscratch", 0x340>;
206def : SysReg<"mepc", 0x341>;
207def : SysReg<"mcause", 0x342>;
208def : SysReg<"mtval", 0x343>;
209def : SysReg<"mip", 0x344>;
210
211//===----------------------------------
212// Machine Protection and Translation
213//===----------------------------------
214def : SysReg<"pmpcfg0", 0x3A0>;
215def : SysReg<"pmpcfg2", 0x3A2>;
216let isRV32Only = 1 in {
217def : SysReg<"pmpcfg1", 0x3A1>;
218def : SysReg<"pmpcfg3", 0x3A3>;
219}
220
221def : SysReg<"pmpaddr0", 0x3B0>;
222def : SysReg<"pmpaddr1", 0x3B1>;
223def : SysReg<"pmpaddr2", 0x3B2>;
224def : SysReg<"pmpaddr3", 0x3B3>;
225def : SysReg<"pmpaddr4", 0x3B4>;
226def : SysReg<"pmpaddr5", 0x3B5>;
227def : SysReg<"pmpaddr6", 0x3B6>;
228def : SysReg<"pmpaddr7", 0x3B7>;
229def : SysReg<"pmpaddr8", 0x3B8>;
230def : SysReg<"pmpaddr9", 0x3B9>;
231def : SysReg<"pmpaddr10", 0x3BA>;
232def : SysReg<"pmpaddr11", 0x3BB>;
233def : SysReg<"pmpaddr12", 0x3BC>;
234def : SysReg<"pmpaddr13", 0x3BD>;
235def : SysReg<"pmpaddr14", 0x3BE>;
236def : SysReg<"pmpaddr15", 0x3BF>;
237
238
239//===--------------------------
240// Machine Counter and Timers
241//===--------------------------
242def : SysReg<"mcycle", 0xB00>;
243def : SysReg<"minstret", 0xB02>;
244
245def : SysReg<"mhpmcounter3", 0xB03>;
246def : SysReg<"mhpmcounter4", 0xB04>;
247def : SysReg<"mhpmcounter5", 0xB05>;
248def : SysReg<"mhpmcounter6", 0xB06>;
249def : SysReg<"mhpmcounter7", 0xB07>;
250def : SysReg<"mhpmcounter8", 0xB08>;
251def : SysReg<"mhpmcounter9", 0xB09>;
252def : SysReg<"mhpmcounter10", 0xB0A>;
253def : SysReg<"mhpmcounter11", 0xB0B>;
254def : SysReg<"mhpmcounter12", 0xB0C>;
255def : SysReg<"mhpmcounter13", 0xB0D>;
256def : SysReg<"mhpmcounter14", 0xB0E>;
257def : SysReg<"mhpmcounter15", 0xB0F>;
258def : SysReg<"mhpmcounter16", 0xB10>;
259def : SysReg<"mhpmcounter17", 0xB11>;
260def : SysReg<"mhpmcounter18", 0xB12>;
261def : SysReg<"mhpmcounter19", 0xB13>;
262def : SysReg<"mhpmcounter20", 0xB14>;
263def : SysReg<"mhpmcounter21", 0xB15>;
264def : SysReg<"mhpmcounter22", 0xB16>;
265def : SysReg<"mhpmcounter23", 0xB17>;
266def : SysReg<"mhpmcounter24", 0xB18>;
267def : SysReg<"mhpmcounter25", 0xB19>;
268def : SysReg<"mhpmcounter26", 0xB1A>;
269def : SysReg<"mhpmcounter27", 0xB1B>;
270def : SysReg<"mhpmcounter28", 0xB1C>;
271def : SysReg<"mhpmcounter29", 0xB1D>;
272def : SysReg<"mhpmcounter30", 0xB1E>;
273def : SysReg<"mhpmcounter31", 0xB1F>;
274
275let isRV32Only = 1 in {
276def: SysReg<"mcycleh", 0xB80>;
277def: SysReg<"minstreth", 0xB82>;
278
279def: SysReg<"mhpmcounter3h", 0xB83>;
280def: SysReg<"mhpmcounter4h", 0xB84>;
281def: SysReg<"mhpmcounter5h", 0xB85>;
282def: SysReg<"mhpmcounter6h", 0xB86>;
283def: SysReg<"mhpmcounter7h", 0xB87>;
284def: SysReg<"mhpmcounter8h", 0xB88>;
285def: SysReg<"mhpmcounter9h", 0xB89>;
286def: SysReg<"mhpmcounter10h", 0xB8A>;
287def: SysReg<"mhpmcounter11h", 0xB8B>;
288def: SysReg<"mhpmcounter12h", 0xB8C>;
289def: SysReg<"mhpmcounter13h", 0xB8D>;
290def: SysReg<"mhpmcounter14h", 0xB8E>;
291def: SysReg<"mhpmcounter15h", 0xB8F>;
292def: SysReg<"mhpmcounter16h", 0xB90>;
293def: SysReg<"mhpmcounter17h", 0xB91>;
294def: SysReg<"mhpmcounter18h", 0xB92>;
295def: SysReg<"mhpmcounter19h", 0xB93>;
296def: SysReg<"mhpmcounter20h", 0xB94>;
297def: SysReg<"mhpmcounter21h", 0xB95>;
298def: SysReg<"mhpmcounter22h", 0xB96>;
299def: SysReg<"mhpmcounter23h", 0xB97>;
300def: SysReg<"mhpmcounter24h", 0xB98>;
301def: SysReg<"mhpmcounter25h", 0xB99>;
302def: SysReg<"mhpmcounter26h", 0xB9A>;
303def: SysReg<"mhpmcounter27h", 0xB9B>;
304def: SysReg<"mhpmcounter28h", 0xB9C>;
305def: SysReg<"mhpmcounter29h", 0xB9D>;
306def: SysReg<"mhpmcounter30h", 0xB9E>;
307def: SysReg<"mhpmcounter31h", 0xB9F>;
308}
309
310//===--------------------------
311// Machine Counter Setup
312//===--------------------------
313let AltName = "mucounteren" in // Privileged spec v1.9.1 Name
314def : SysReg<"mcountinhibit", 0x320>;
315
316def : SysReg<"mhpmevent3", 0x323>;
317def : SysReg<"mhpmevent4", 0x324>;
318def : SysReg<"mhpmevent5", 0x325>;
319def : SysReg<"mhpmevent6", 0x326>;
320def : SysReg<"mhpmevent7", 0x327>;
321def : SysReg<"mhpmevent8", 0x328>;
322def : SysReg<"mhpmevent9", 0x329>;
323def : SysReg<"mhpmevent10", 0x32A>;
324def : SysReg<"mhpmevent11", 0x32B>;
325def : SysReg<"mhpmevent12", 0x32C>;
326def : SysReg<"mhpmevent13", 0x32D>;
327def : SysReg<"mhpmevent14", 0x32E>;
328def : SysReg<"mhpmevent15", 0x32F>;
329def : SysReg<"mhpmevent16", 0x330>;
330def : SysReg<"mhpmevent17", 0x331>;
331def : SysReg<"mhpmevent18", 0x332>;
332def : SysReg<"mhpmevent19", 0x333>;
333def : SysReg<"mhpmevent20", 0x334>;
334def : SysReg<"mhpmevent21", 0x335>;
335def : SysReg<"mhpmevent22", 0x336>;
336def : SysReg<"mhpmevent23", 0x337>;
337def : SysReg<"mhpmevent24", 0x338>;
338def : SysReg<"mhpmevent25", 0x339>;
339def : SysReg<"mhpmevent26", 0x33A>;
340def : SysReg<"mhpmevent27", 0x33B>;
341def : SysReg<"mhpmevent28", 0x33C>;
342def : SysReg<"mhpmevent29", 0x33D>;
343def : SysReg<"mhpmevent30", 0x33E>;
344def : SysReg<"mhpmevent31", 0x33F>;
345
346//===-----------------------------------------------
347// Debug/ Trace Registers (shared with Debug Mode)
348//===-----------------------------------------------
349def : SysReg<"tselect", 0x7A0>;
350def : SysReg<"tdata1", 0x7A1>;
351def : SysReg<"tdata2", 0x7A2>;
352def : SysReg<"tdata3", 0x7A3>;
353
354//===-----------------------------------------------
355// Debug Mode Registers
356//===-----------------------------------------------
357def : SysReg<"dcsr", 0x7B0>;
358def : SysReg<"dpc", 0x7B1>;
359
360// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
361// drafts of the RISC-V debug spec
362let AltName = "dscratch" in
363def : SysReg<"dscratch0", 0x7B2>;
364def : SysReg<"dscratch1", 0x7B3>;
365
366//===-----------------------------------------------
367// User Vector CSRs
368//===-----------------------------------------------
369def : SysReg<"vstart", 0x008>;
370def : SysReg<"vxsat", 0x009>;
371def : SysReg<"vxrm", 0x00A>;
372def : SysReg<"vl", 0xC20>;
373def : SysReg<"vtype", 0xC21>;
374def : SysReg<"vlenb", 0xC22>;
375