1//===-- SPIRVRegisterInfo.td - SPIR-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Declarations that describe the SPIR-V register file. 10// 11//===----------------------------------------------------------------------===// 12 13let Namespace = "SPIRV" in { 14 def p0 : PtrValueType <i32, 0>; 15 // All registers are for 32-bit identifiers, so have a single dummy register 16 17 // Class for registers that are the result of OpTypeXXX instructions 18 def TYPE0 : Register<"TYPE0">; 19 def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>; 20 21 // Class for every other non-type ID 22 def ID0 : Register<"ID0">; 23 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>; 24 def fID0 : Register<"FID0">; 25 def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>; 26 def pID0 : Register<"pID0">; 27 def pID : RegisterClass<"SPIRV", [p0], 32, (add pID0)>; 28 def vID0 : Register<"pID0">; 29 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>; 30 def vfID0 : Register<"pID0">; 31 def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>; 32 33 def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add ID, fID, pID, vID, vfID)>; 34 35 // A few instructions like OpName can take ids from both type and non-type 36 // instructions, so we need a super-class to allow for both to count as valid 37 // arguments for these instructions. 38 def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>; 39} 40