1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/SparcFixupKinds.h"
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "llvm/ADT/StringSwitch.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCELFObjectWriter.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCFixupKindInfo.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCValue.h"
19 #include "llvm/MC/TargetRegistry.h"
20 #include "llvm/Support/EndianStream.h"
21
22 using namespace llvm;
23
adjustFixupValue(unsigned Kind,uint64_t Value)24 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
25 switch (Kind) {
26 default:
27 llvm_unreachable("Unknown fixup kind!");
28 case FK_Data_1:
29 case FK_Data_2:
30 case FK_Data_4:
31 case FK_Data_8:
32 return Value;
33
34 case Sparc::fixup_sparc_wplt30:
35 case Sparc::fixup_sparc_call30:
36 return (Value >> 2) & 0x3fffffff;
37
38 case Sparc::fixup_sparc_br22:
39 return (Value >> 2) & 0x3fffff;
40
41 case Sparc::fixup_sparc_br19:
42 return (Value >> 2) & 0x7ffff;
43
44 case Sparc::fixup_sparc_br16: {
45 // A.3 Branch on Integer Register with Prediction (BPr)
46 // Inst{21-20} = d16hi;
47 // Inst{13-0} = d16lo;
48 unsigned d16hi = (Value >> 16) & 0x3;
49 unsigned d16lo = (Value >> 2) & 0x3fff;
50 return (d16hi << 20) | d16lo;
51 }
52
53 case Sparc::fixup_sparc_hix22:
54 return (~Value >> 10) & 0x3fffff;
55
56 case Sparc::fixup_sparc_pc22:
57 case Sparc::fixup_sparc_got22:
58 case Sparc::fixup_sparc_tls_gd_hi22:
59 case Sparc::fixup_sparc_tls_ldm_hi22:
60 case Sparc::fixup_sparc_tls_ie_hi22:
61 case Sparc::fixup_sparc_hi22:
62 case Sparc::fixup_sparc_lm:
63 return (Value >> 10) & 0x3fffff;
64
65 case Sparc::fixup_sparc_got13:
66 case Sparc::fixup_sparc_13:
67 return Value & 0x1fff;
68
69 case Sparc::fixup_sparc_lox10:
70 return (Value & 0x3ff) | 0x1c00;
71
72 case Sparc::fixup_sparc_pc10:
73 case Sparc::fixup_sparc_got10:
74 case Sparc::fixup_sparc_tls_gd_lo10:
75 case Sparc::fixup_sparc_tls_ldm_lo10:
76 case Sparc::fixup_sparc_tls_ie_lo10:
77 case Sparc::fixup_sparc_lo10:
78 return Value & 0x3ff;
79
80 case Sparc::fixup_sparc_h44:
81 return (Value >> 22) & 0x3fffff;
82
83 case Sparc::fixup_sparc_m44:
84 return (Value >> 12) & 0x3ff;
85
86 case Sparc::fixup_sparc_l44:
87 return Value & 0xfff;
88
89 case Sparc::fixup_sparc_hh:
90 return (Value >> 42) & 0x3fffff;
91
92 case Sparc::fixup_sparc_hm:
93 return (Value >> 32) & 0x3ff;
94
95 case Sparc::fixup_sparc_tls_ldo_hix22:
96 case Sparc::fixup_sparc_tls_le_hix22:
97 case Sparc::fixup_sparc_tls_ldo_lox10:
98 case Sparc::fixup_sparc_tls_le_lox10:
99 assert(Value == 0 && "Sparc TLS relocs expect zero Value");
100 return 0;
101
102 case Sparc::fixup_sparc_tls_gd_add:
103 case Sparc::fixup_sparc_tls_gd_call:
104 case Sparc::fixup_sparc_tls_ldm_add:
105 case Sparc::fixup_sparc_tls_ldm_call:
106 case Sparc::fixup_sparc_tls_ldo_add:
107 case Sparc::fixup_sparc_tls_ie_ld:
108 case Sparc::fixup_sparc_tls_ie_ldx:
109 case Sparc::fixup_sparc_tls_ie_add:
110 case Sparc::fixup_sparc_gotdata_lox10:
111 case Sparc::fixup_sparc_gotdata_hix22:
112 case Sparc::fixup_sparc_gotdata_op:
113 return 0;
114 }
115 }
116
117 /// getFixupKindNumBytes - The number of bytes the fixup may change.
getFixupKindNumBytes(unsigned Kind)118 static unsigned getFixupKindNumBytes(unsigned Kind) {
119 switch (Kind) {
120 default:
121 return 4;
122 case FK_Data_1:
123 return 1;
124 case FK_Data_2:
125 return 2;
126 case FK_Data_8:
127 return 8;
128 }
129 }
130
131 namespace {
132 class SparcAsmBackend : public MCAsmBackend {
133 protected:
134 const Target &TheTarget;
135 bool Is64Bit;
136
137 public:
SparcAsmBackend(const Target & T)138 SparcAsmBackend(const Target &T)
139 : MCAsmBackend(StringRef(T.getName()) == "sparcel"
140 ? llvm::endianness::little
141 : llvm::endianness::big),
142 TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
143
getNumFixupKinds() const144 unsigned getNumFixupKinds() const override {
145 return Sparc::NumTargetFixupKinds;
146 }
147
getFixupKind(StringRef Name) const148 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override {
149 unsigned Type;
150 Type = llvm::StringSwitch<unsigned>(Name)
151 #define ELF_RELOC(X, Y) .Case(#X, Y)
152 #include "llvm/BinaryFormat/ELFRelocs/Sparc.def"
153 #undef ELF_RELOC
154 .Case("BFD_RELOC_NONE", ELF::R_SPARC_NONE)
155 .Case("BFD_RELOC_8", ELF::R_SPARC_8)
156 .Case("BFD_RELOC_16", ELF::R_SPARC_16)
157 .Case("BFD_RELOC_32", ELF::R_SPARC_32)
158 .Case("BFD_RELOC_64", ELF::R_SPARC_64)
159 .Default(-1u);
160 if (Type == -1u)
161 return std::nullopt;
162 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
163 }
164
getFixupKindInfo(MCFixupKind Kind) const165 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
166 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
167 // name offset bits flags
168 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
169 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
170 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
171 { "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
172 { "fixup_sparc_13", 19, 13, 0 },
173 { "fixup_sparc_hi22", 10, 22, 0 },
174 { "fixup_sparc_lo10", 22, 10, 0 },
175 { "fixup_sparc_h44", 10, 22, 0 },
176 { "fixup_sparc_m44", 22, 10, 0 },
177 { "fixup_sparc_l44", 20, 12, 0 },
178 { "fixup_sparc_hh", 10, 22, 0 },
179 { "fixup_sparc_hm", 22, 10, 0 },
180 { "fixup_sparc_lm", 10, 22, 0 },
181 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
182 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
183 { "fixup_sparc_got22", 10, 22, 0 },
184 { "fixup_sparc_got10", 22, 10, 0 },
185 { "fixup_sparc_got13", 19, 13, 0 },
186 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
187 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
188 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
189 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
190 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
191 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
192 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
193 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
194 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
195 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
196 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
197 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
198 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
199 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
200 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
201 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
202 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
203 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
204 { "fixup_sparc_tls_le_lox10", 0, 0, 0 },
205 { "fixup_sparc_hix22", 10, 22, 0 },
206 { "fixup_sparc_lox10", 19, 13, 0 },
207 { "fixup_sparc_gotdata_hix22", 0, 0, 0 },
208 { "fixup_sparc_gotdata_lox10", 0, 0, 0 },
209 { "fixup_sparc_gotdata_op", 0, 0, 0 },
210 };
211
212 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
213 // name offset bits flags
214 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
215 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
216 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
217 { "fixup_sparc_br16", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
218 { "fixup_sparc_13", 0, 13, 0 },
219 { "fixup_sparc_hi22", 0, 22, 0 },
220 { "fixup_sparc_lo10", 0, 10, 0 },
221 { "fixup_sparc_h44", 0, 22, 0 },
222 { "fixup_sparc_m44", 0, 10, 0 },
223 { "fixup_sparc_l44", 0, 12, 0 },
224 { "fixup_sparc_hh", 0, 22, 0 },
225 { "fixup_sparc_hm", 0, 10, 0 },
226 { "fixup_sparc_lm", 0, 22, 0 },
227 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
228 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
229 { "fixup_sparc_got22", 0, 22, 0 },
230 { "fixup_sparc_got10", 0, 10, 0 },
231 { "fixup_sparc_got13", 0, 13, 0 },
232 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
233 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
234 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
235 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
236 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
237 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
238 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
239 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
240 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
241 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
242 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
243 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
244 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
245 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
246 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
247 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
248 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
249 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
250 { "fixup_sparc_tls_le_lox10", 0, 0, 0 },
251 { "fixup_sparc_hix22", 0, 22, 0 },
252 { "fixup_sparc_lox10", 0, 13, 0 },
253 { "fixup_sparc_gotdata_hix22", 0, 0, 0 },
254 { "fixup_sparc_gotdata_lox10", 0, 0, 0 },
255 { "fixup_sparc_gotdata_op", 0, 0, 0 },
256 };
257
258 // Fixup kinds from .reloc directive are like R_SPARC_NONE. They do
259 // not require any extra processing.
260 if (Kind >= FirstLiteralRelocationKind)
261 return MCAsmBackend::getFixupKindInfo(FK_NONE);
262
263 if (Kind < FirstTargetFixupKind)
264 return MCAsmBackend::getFixupKindInfo(Kind);
265
266 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
267 "Invalid kind!");
268 if (Endian == llvm::endianness::little)
269 return InfosLE[Kind - FirstTargetFixupKind];
270
271 return InfosBE[Kind - FirstTargetFixupKind];
272 }
273
shouldForceRelocation(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,const MCSubtargetInfo * STI)274 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
275 const MCValue &Target,
276 const MCSubtargetInfo *STI) override {
277 if (Fixup.getKind() >= FirstLiteralRelocationKind)
278 return true;
279 switch ((Sparc::Fixups)Fixup.getKind()) {
280 default:
281 return false;
282 case Sparc::fixup_sparc_wplt30:
283 if (Target.getSymA()->getSymbol().isTemporary())
284 return false;
285 [[fallthrough]];
286 case Sparc::fixup_sparc_tls_gd_hi22:
287 case Sparc::fixup_sparc_tls_gd_lo10:
288 case Sparc::fixup_sparc_tls_gd_add:
289 case Sparc::fixup_sparc_tls_gd_call:
290 case Sparc::fixup_sparc_tls_ldm_hi22:
291 case Sparc::fixup_sparc_tls_ldm_lo10:
292 case Sparc::fixup_sparc_tls_ldm_add:
293 case Sparc::fixup_sparc_tls_ldm_call:
294 case Sparc::fixup_sparc_tls_ldo_hix22:
295 case Sparc::fixup_sparc_tls_ldo_lox10:
296 case Sparc::fixup_sparc_tls_ldo_add:
297 case Sparc::fixup_sparc_tls_ie_hi22:
298 case Sparc::fixup_sparc_tls_ie_lo10:
299 case Sparc::fixup_sparc_tls_ie_ld:
300 case Sparc::fixup_sparc_tls_ie_ldx:
301 case Sparc::fixup_sparc_tls_ie_add:
302 case Sparc::fixup_sparc_tls_le_hix22:
303 case Sparc::fixup_sparc_tls_le_lox10:
304 return true;
305 }
306 }
307
308 /// fixupNeedsRelaxation - Target specific predicate for whether a given
309 /// fixup requires the associated instruction to be relaxed.
fixupNeedsRelaxation(const MCFixup & Fixup,uint64_t Value,const MCRelaxableFragment * DF,const MCAsmLayout & Layout) const310 bool fixupNeedsRelaxation(const MCFixup &Fixup,
311 uint64_t Value,
312 const MCRelaxableFragment *DF,
313 const MCAsmLayout &Layout) const override {
314 // FIXME.
315 llvm_unreachable("fixupNeedsRelaxation() unimplemented");
316 return false;
317 }
relaxInstruction(MCInst & Inst,const MCSubtargetInfo & STI) const318 void relaxInstruction(MCInst &Inst,
319 const MCSubtargetInfo &STI) const override {
320 // FIXME.
321 llvm_unreachable("relaxInstruction() unimplemented");
322 }
323
writeNopData(raw_ostream & OS,uint64_t Count,const MCSubtargetInfo * STI) const324 bool writeNopData(raw_ostream &OS, uint64_t Count,
325 const MCSubtargetInfo *STI) const override {
326 // Cannot emit NOP with size not multiple of 32 bits.
327 if (Count % 4 != 0)
328 return false;
329
330 uint64_t NumNops = Count / 4;
331 for (uint64_t i = 0; i != NumNops; ++i)
332 support::endian::write<uint32_t>(OS, 0x01000000, Endian);
333
334 return true;
335 }
336 };
337
338 class ELFSparcAsmBackend : public SparcAsmBackend {
339 Triple::OSType OSType;
340 public:
ELFSparcAsmBackend(const Target & T,Triple::OSType OSType)341 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
342 SparcAsmBackend(T), OSType(OSType) { }
343
applyFixup(const MCAssembler & Asm,const MCFixup & Fixup,const MCValue & Target,MutableArrayRef<char> Data,uint64_t Value,bool IsResolved,const MCSubtargetInfo * STI) const344 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
345 const MCValue &Target, MutableArrayRef<char> Data,
346 uint64_t Value, bool IsResolved,
347 const MCSubtargetInfo *STI) const override {
348
349 if (Fixup.getKind() >= FirstLiteralRelocationKind)
350 return;
351 Value = adjustFixupValue(Fixup.getKind(), Value);
352 if (!Value) return; // Doesn't change encoding.
353
354 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
355 unsigned Offset = Fixup.getOffset();
356 // For each byte of the fragment that the fixup touches, mask in the bits
357 // from the fixup value. The Value has been "split up" into the
358 // appropriate bitfields above.
359 for (unsigned i = 0; i != NumBytes; ++i) {
360 unsigned Idx =
361 Endian == llvm::endianness::little ? i : (NumBytes - 1) - i;
362 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
363 }
364 }
365
366 std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const367 createObjectTargetWriter() const override {
368 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
369 return createSparcELFObjectWriter(Is64Bit, OSABI);
370 }
371 };
372
373 } // end anonymous namespace
374
createSparcAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions & Options)375 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
376 const MCSubtargetInfo &STI,
377 const MCRegisterInfo &MRI,
378 const MCTargetOptions &Options) {
379 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
380 }
381