1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcTargetMachine.h"
13 #include "LeonPasses.h"
14 #include "Sparc.h"
15 #include "SparcMachineFunctionInfo.h"
16 #include "SparcTargetObjectFile.h"
17 #include "TargetInfo/SparcTargetInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/MC/TargetRegistry.h"
21 #include <optional>
22 using namespace llvm;
23
LLVMInitializeSparcTarget()24 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
25 // Register the target.
26 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
27 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
28 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
29
30 PassRegistry &PR = *PassRegistry::getPassRegistry();
31 initializeSparcDAGToDAGISelPass(PR);
32 }
33
34 static cl::opt<bool>
35 BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
36 cl::desc("Relax out of range conditional branches"));
37
computeDataLayout(const Triple & T,bool is64Bit)38 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
39 // Sparc is typically big endian, but some are little.
40 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
41 Ret += "-m:e";
42
43 // Some ABIs have 32bit pointers.
44 if (!is64Bit)
45 Ret += "-p:32:32";
46
47 // Alignments for 64 bit integers.
48 Ret += "-i64:64";
49
50 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
51 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
52 if (is64Bit)
53 Ret += "-n32:64";
54 else
55 Ret += "-f128:64-n32";
56
57 if (is64Bit)
58 Ret += "-S128";
59 else
60 Ret += "-S64";
61
62 return Ret;
63 }
64
getEffectiveRelocModel(std::optional<Reloc::Model> RM)65 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
66 return RM.value_or(Reloc::Static);
67 }
68
69 // Code models. Some only make sense for 64-bit code.
70 //
71 // SunCC Reloc CodeModel Constraints
72 // abs32 Static Small text+data+bss linked below 2^32 bytes
73 // abs44 Static Medium text+data+bss linked below 2^44 bytes
74 // abs64 Static Large text smaller than 2^31 bytes
75 // pic13 PIC_ Small GOT < 2^13 bytes
76 // pic32 PIC_ Medium GOT < 2^32 bytes
77 //
78 // All code models require that the text segment is smaller than 2GB.
79 static CodeModel::Model
getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM,Reloc::Model RM,bool Is64Bit,bool JIT)80 getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM,
81 bool Is64Bit, bool JIT) {
82 if (CM) {
83 if (*CM == CodeModel::Tiny)
84 report_fatal_error("Target does not support the tiny CodeModel", false);
85 if (*CM == CodeModel::Kernel)
86 report_fatal_error("Target does not support the kernel CodeModel", false);
87 return *CM;
88 }
89 if (Is64Bit) {
90 if (JIT)
91 return CodeModel::Large;
92 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
93 }
94 return CodeModel::Small;
95 }
96
97 /// Create an ILP32 architecture model
SparcTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT,bool is64bit)98 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
99 StringRef CPU, StringRef FS,
100 const TargetOptions &Options,
101 std::optional<Reloc::Model> RM,
102 std::optional<CodeModel::Model> CM,
103 CodeGenOptLevel OL, bool JIT,
104 bool is64bit)
105 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
106 getEffectiveRelocModel(RM),
107 getEffectiveSparcCodeModel(
108 CM, getEffectiveRelocModel(RM), is64bit, JIT),
109 OL),
110 TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
111 initAsmInfo();
112 }
113
114 SparcTargetMachine::~SparcTargetMachine() = default;
115
116 const SparcSubtarget *
getSubtargetImpl(const Function & F) const117 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
118 Attribute CPUAttr = F.getFnAttribute("target-cpu");
119 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
120 Attribute FSAttr = F.getFnAttribute("target-features");
121
122 std::string CPU =
123 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
124 std::string TuneCPU =
125 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
126 std::string FS =
127 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
128
129 // FIXME: This is related to the code below to reset the target options,
130 // we need to know whether or not the soft float flag is set on the
131 // function, so we can enable it as a subtarget feature.
132 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
133
134 if (softFloat)
135 FS += FS.empty() ? "+soft-float" : ",+soft-float";
136
137 auto &I = SubtargetMap[CPU + FS];
138 if (!I) {
139 // This needs to be done before we create a new subtarget since any
140 // creation will depend on the TM and the code generation flags on the
141 // function that reside in TargetOptions.
142 resetTargetOptions(F);
143 I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this,
144 this->is64Bit);
145 }
146 return I.get();
147 }
148
createMachineFunctionInfo(BumpPtrAllocator & Allocator,const Function & F,const TargetSubtargetInfo * STI) const149 MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
150 BumpPtrAllocator &Allocator, const Function &F,
151 const TargetSubtargetInfo *STI) const {
152 return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
153 F, STI);
154 }
155
156 namespace {
157 /// Sparc Code Generator Pass Configuration Options.
158 class SparcPassConfig : public TargetPassConfig {
159 public:
SparcPassConfig(SparcTargetMachine & TM,PassManagerBase & PM)160 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
161 : TargetPassConfig(TM, PM) {}
162
getSparcTargetMachine() const163 SparcTargetMachine &getSparcTargetMachine() const {
164 return getTM<SparcTargetMachine>();
165 }
166
167 void addIRPasses() override;
168 bool addInstSelector() override;
169 void addPreEmitPass() override;
170 };
171 } // namespace
172
createPassConfig(PassManagerBase & PM)173 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
174 return new SparcPassConfig(*this, PM);
175 }
176
addIRPasses()177 void SparcPassConfig::addIRPasses() {
178 addPass(createAtomicExpandPass());
179
180 TargetPassConfig::addIRPasses();
181 }
182
addInstSelector()183 bool SparcPassConfig::addInstSelector() {
184 addPass(createSparcISelDag(getSparcTargetMachine()));
185 return false;
186 }
187
addPreEmitPass()188 void SparcPassConfig::addPreEmitPass(){
189 if (BranchRelaxation)
190 addPass(&BranchRelaxationPassID);
191
192 addPass(createSparcDelaySlotFillerPass());
193 addPass(new InsertNOPLoad());
194 addPass(new DetectRoundChange());
195 addPass(new FixAllFDIVSQRT());
196 }
197
anchor()198 void SparcV8TargetMachine::anchor() { }
199
SparcV8TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT)200 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
201 StringRef CPU, StringRef FS,
202 const TargetOptions &Options,
203 std::optional<Reloc::Model> RM,
204 std::optional<CodeModel::Model> CM,
205 CodeGenOptLevel OL, bool JIT)
206 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
207
anchor()208 void SparcV9TargetMachine::anchor() { }
209
SparcV9TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT)210 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
211 StringRef CPU, StringRef FS,
212 const TargetOptions &Options,
213 std::optional<Reloc::Model> RM,
214 std::optional<CodeModel::Model> CM,
215 CodeGenOptLevel OL, bool JIT)
216 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
217
anchor()218 void SparcelTargetMachine::anchor() {}
219
SparcelTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT)220 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
221 StringRef CPU, StringRef FS,
222 const TargetOptions &Options,
223 std::optional<Reloc::Model> RM,
224 std::optional<CodeModel::Model> CM,
225 CodeGenOptLevel OL, bool JIT)
226 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
227