1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "SparcTargetMachine.h" 13 #include "LeonPasses.h" 14 #include "Sparc.h" 15 #include "SparcMachineFunctionInfo.h" 16 #include "SparcTargetObjectFile.h" 17 #include "TargetInfo/SparcTargetInfo.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/CodeGen/TargetPassConfig.h" 20 #include "llvm/MC/TargetRegistry.h" 21 #include <optional> 22 using namespace llvm; 23 24 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { 25 // Register the target. 26 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget()); 27 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target()); 28 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); 29 30 PassRegistry &PR = *PassRegistry::getPassRegistry(); 31 initializeSparcDAGToDAGISelPass(PR); 32 } 33 34 static cl::opt<bool> 35 BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true), 36 cl::desc("Relax out of range conditional branches")); 37 38 static std::string computeDataLayout(const Triple &T, bool is64Bit) { 39 // Sparc is typically big endian, but some are little. 40 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; 41 Ret += "-m:e"; 42 43 // Some ABIs have 32bit pointers. 44 if (!is64Bit) 45 Ret += "-p:32:32"; 46 47 // Alignments for 64 bit integers. 48 Ret += "-i64:64"; 49 50 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. 51 // On SparcV9 registers can hold 64 or 32 bits, on others only 32. 52 if (is64Bit) 53 Ret += "-n32:64"; 54 else 55 Ret += "-f128:64-n32"; 56 57 if (is64Bit) 58 Ret += "-S128"; 59 else 60 Ret += "-S64"; 61 62 return Ret; 63 } 64 65 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { 66 return RM.value_or(Reloc::Static); 67 } 68 69 // Code models. Some only make sense for 64-bit code. 70 // 71 // SunCC Reloc CodeModel Constraints 72 // abs32 Static Small text+data+bss linked below 2^32 bytes 73 // abs44 Static Medium text+data+bss linked below 2^44 bytes 74 // abs64 Static Large text smaller than 2^31 bytes 75 // pic13 PIC_ Small GOT < 2^13 bytes 76 // pic32 PIC_ Medium GOT < 2^32 bytes 77 // 78 // All code models require that the text segment is smaller than 2GB. 79 static CodeModel::Model 80 getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM, 81 bool Is64Bit, bool JIT) { 82 if (CM) { 83 if (*CM == CodeModel::Tiny) 84 report_fatal_error("Target does not support the tiny CodeModel", false); 85 if (*CM == CodeModel::Kernel) 86 report_fatal_error("Target does not support the kernel CodeModel", false); 87 return *CM; 88 } 89 if (Is64Bit) { 90 if (JIT) 91 return CodeModel::Large; 92 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 93 } 94 return CodeModel::Small; 95 } 96 97 /// Create an ILP32 architecture model 98 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, 99 StringRef CPU, StringRef FS, 100 const TargetOptions &Options, 101 std::optional<Reloc::Model> RM, 102 std::optional<CodeModel::Model> CM, 103 CodeGenOptLevel OL, bool JIT, 104 bool is64bit) 105 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, 106 getEffectiveRelocModel(RM), 107 getEffectiveSparcCodeModel( 108 CM, getEffectiveRelocModel(RM), is64bit, JIT), 109 OL), 110 TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) { 111 initAsmInfo(); 112 } 113 114 SparcTargetMachine::~SparcTargetMachine() = default; 115 116 const SparcSubtarget * 117 SparcTargetMachine::getSubtargetImpl(const Function &F) const { 118 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 119 Attribute FSAttr = F.getFnAttribute("target-features"); 120 121 std::string CPU = 122 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 123 std::string FS = 124 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 125 126 // FIXME: This is related to the code below to reset the target options, 127 // we need to know whether or not the soft float flag is set on the 128 // function, so we can enable it as a subtarget feature. 129 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 130 131 if (softFloat) 132 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 133 134 auto &I = SubtargetMap[CPU + FS]; 135 if (!I) { 136 // This needs to be done before we create a new subtarget since any 137 // creation will depend on the TM and the code generation flags on the 138 // function that reside in TargetOptions. 139 resetTargetOptions(F); 140 I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this, 141 this->is64Bit); 142 } 143 return I.get(); 144 } 145 146 MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo( 147 BumpPtrAllocator &Allocator, const Function &F, 148 const TargetSubtargetInfo *STI) const { 149 return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator, 150 F, STI); 151 } 152 153 namespace { 154 /// Sparc Code Generator Pass Configuration Options. 155 class SparcPassConfig : public TargetPassConfig { 156 public: 157 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM) 158 : TargetPassConfig(TM, PM) {} 159 160 SparcTargetMachine &getSparcTargetMachine() const { 161 return getTM<SparcTargetMachine>(); 162 } 163 164 void addIRPasses() override; 165 bool addInstSelector() override; 166 void addPreEmitPass() override; 167 }; 168 } // namespace 169 170 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 171 return new SparcPassConfig(*this, PM); 172 } 173 174 void SparcPassConfig::addIRPasses() { 175 addPass(createAtomicExpandPass()); 176 177 TargetPassConfig::addIRPasses(); 178 } 179 180 bool SparcPassConfig::addInstSelector() { 181 addPass(createSparcISelDag(getSparcTargetMachine())); 182 return false; 183 } 184 185 void SparcPassConfig::addPreEmitPass(){ 186 if (BranchRelaxation) 187 addPass(&BranchRelaxationPassID); 188 189 addPass(createSparcDelaySlotFillerPass()); 190 addPass(new InsertNOPLoad()); 191 addPass(new DetectRoundChange()); 192 addPass(new FixAllFDIVSQRT()); 193 } 194 195 void SparcV8TargetMachine::anchor() { } 196 197 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, 198 StringRef CPU, StringRef FS, 199 const TargetOptions &Options, 200 std::optional<Reloc::Model> RM, 201 std::optional<CodeModel::Model> CM, 202 CodeGenOptLevel OL, bool JIT) 203 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 204 205 void SparcV9TargetMachine::anchor() { } 206 207 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, 208 StringRef CPU, StringRef FS, 209 const TargetOptions &Options, 210 std::optional<Reloc::Model> RM, 211 std::optional<CodeModel::Model> CM, 212 CodeGenOptLevel OL, bool JIT) 213 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 214 215 void SparcelTargetMachine::anchor() {} 216 217 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, 218 StringRef CPU, StringRef FS, 219 const TargetOptions &Options, 220 std::optional<Reloc::Model> RM, 221 std::optional<CodeModel::Model> CM, 222 CodeGenOptLevel OL, bool JIT) 223 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 224