1//===-------------- VVPInstrInfo.td - VVP_* SDNode patterns ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the VE Vector Predicated SDNodes (VVP SDNodes).  VVP
10// SDNodes are an intermediate isel layer between the vector SDNodes emitted by
11// LLVM and the actual VE vector instructions. For example:
12//
13//  ADD(x,y)   -->   VVP_ADD(x,y,mask,evl)   -->   VADDSWSXrvml(x,y,mask,evl)
14//     ^                      ^                            ^
15//  The standard     The VVP layer SDNode.        The VE vector instruction.
16//  SDNode.
17//
18// TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream.
19//===----------------------------------------------------------------------===//
20
21// vvp_load(ptr, stride, mask, avl)
22def SDTLoadVVP : SDTypeProfile<1, 4, [
23  SDTCisVec<0>,
24  SDTCisPtrTy<1>,
25  SDTCisInt<2>,
26  SDTCisVec<3>,
27  IsVLVT<4>
28]>;
29
30// vvp_store(data, ptr, stride, mask, avl)
31def SDTStoreVVP: SDTypeProfile<0, 5, [
32  SDTCisVec<0>,
33  SDTCisPtrTy<1>,
34  SDTCisInt<2>,
35  SDTCisVec<3>,
36  IsVLVT<4>
37]>;
38
39// vvp_scatter(chain, data, addr, mask, avl)
40def SDTScatterVVP: SDTypeProfile<0, 4, [
41  SDTCisVec<0>,
42  SDTCisVec<1>,
43  SDTCisVec<2>,
44  SDTCisSameNumEltsAs<0, 2>,
45  IsVLVT<3>
46]>;
47
48// vvp_gather(chain, addr, mask, avl)
49def SDTGatherVVP: SDTypeProfile<1, 3, [
50  SDTCisVec<0>,
51  SDTCisVec<1>,
52  SDTCisSameNumEltsAs<0, 2>,
53  IsVLVT<3>
54]>;
55
56// BinaryOp(x,y,mask,vl)
57def SDTIntBinOpVVP : SDTypeProfile<1, 4, [     // vp_add, vp_and, etc.
58  SDTCisSameAs<0, 1>,
59  SDTCisSameAs<0, 2>,
60  SDTCisInt<0>,
61  SDTCisSameNumEltsAs<0, 3>,
62  IsVLVT<4>
63]>;
64
65// UnaryFPOp(x,mask,vl)
66def SDTFPUnaryOpVVP : SDTypeProfile<1, 3, [
67  SDTCisSameAs<0, 1>,
68  SDTCisFP<0>,
69  SDTCisInt<2>,
70  SDTCisSameNumEltsAs<0, 2>,
71  IsVLVT<3>
72]>;
73
74// BinaryFPOp(x,y,mask,vl)
75def SDTFPBinOpVVP : SDTypeProfile<1, 4, [      // vvp_fadd, etc.
76  SDTCisSameAs<0, 1>,
77  SDTCisSameAs<0, 2>,
78  SDTCisFP<0>,
79  SDTCisInt<3>,
80  SDTCisSameNumEltsAs<0, 3>,
81  IsVLVT<4>
82]>;
83
84// TernaryFPOp(x,y,z,mask,vl)
85def SDTFPTernaryOpVVP : SDTypeProfile<1, 5, [
86  SDTCisSameAs<0, 1>,
87  SDTCisSameAs<0, 2>,
88  SDTCisSameAs<0, 3>,
89  SDTCisFP<0>,
90  SDTCisInt<4>,
91  SDTCisSameNumEltsAs<0, 4>,
92  IsVLVT<5>
93]>;
94
95// Select(OnTrue, OnFalse, SelMask, vl)
96def SDTSelectVVP : SDTypeProfile<1, 4, [       // vp_select, vp_merge
97  SDTCisVec<0>,
98  SDTCisSameNumEltsAs<0, 3>,
99  SDTCisSameAs<0, 1>,
100  SDTCisSameAs<1, 2>,
101  IsVLVT<4>
102]>;
103
104// SetCC (lhs, rhs, cc, mask, vl)
105def SDTSetCCVVP : SDTypeProfile<1, 5, [        // vp_setcc
106  SDTCisVec<0>,
107  SDTCisVec<1>,
108  SDTCisSameNumEltsAs<0, 1>,
109  SDTCisSameAs<1, 2>,
110  SDTCisVT<3, OtherVT>,
111  SDTCisInt<4>,
112  SDTCisSameNumEltsAs<0, 4>,
113  IsVLVT<5>
114]>;
115
116// vvp_reduce(vector, mask, vl)
117def SDTReduceVVP : SDTypeProfile<1, 3, [
118  SDTCisVec<1>,
119  SDTCisInt<2>,
120  SDTCisVec<2>,
121  SDTCisSameNumEltsAs<1,2>,
122  IsVLVT<3>
123]>;
124
125
126// Binary operator commutative pattern.
127class vvp_commutative<SDNode RootOp> :
128  PatFrags<
129  (ops node:$lhs, node:$rhs, node:$mask, node:$vlen),
130  [(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen),
131   (RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>;
132
133class vvp_fma_commutative<SDNode RootOp> :
134  PatFrags<
135  (ops node:$X, node:$Y, node:$Z, node:$mask, node:$vlen),
136  [(RootOp node:$X, node:$Y, node:$Z, node:$mask, node:$vlen),
137   (RootOp node:$X, node:$Z, node:$Y, node:$mask, node:$vlen)]>;
138
139// VVP node definitions.
140def vvp_add    : SDNode<"VEISD::VVP_ADD",  SDTIntBinOpVVP>;
141def c_vvp_add  : vvp_commutative<vvp_add>;
142
143def vvp_sub    : SDNode<"VEISD::VVP_SUB",  SDTIntBinOpVVP>;
144
145def vvp_mul    : SDNode<"VEISD::VVP_MUL",  SDTIntBinOpVVP>;
146def c_vvp_mul  : vvp_commutative<vvp_mul>;
147
148def vvp_sdiv   : SDNode<"VEISD::VVP_SDIV", SDTIntBinOpVVP>;
149def vvp_udiv   : SDNode<"VEISD::VVP_UDIV", SDTIntBinOpVVP>;
150
151def vvp_and    : SDNode<"VEISD::VVP_AND",  SDTIntBinOpVVP>;
152def c_vvp_and  : vvp_commutative<vvp_and>;
153
154def vvp_or     : SDNode<"VEISD::VVP_OR",  SDTIntBinOpVVP>;
155def c_vvp_or   : vvp_commutative<vvp_or>;
156
157def vvp_xor    : SDNode<"VEISD::VVP_XOR",  SDTIntBinOpVVP>;
158def c_vvp_xor  : vvp_commutative<vvp_xor>;
159
160def vvp_srl    : SDNode<"VEISD::VVP_SRL",  SDTIntBinOpVVP>;
161def vvp_sra    : SDNode<"VEISD::VVP_SRA",  SDTIntBinOpVVP>;
162def vvp_shl    : SDNode<"VEISD::VVP_SHL",  SDTIntBinOpVVP>;
163
164def vvp_fneg    : SDNode<"VEISD::VVP_FNEG",  SDTFPUnaryOpVVP>;
165
166def vvp_fadd    : SDNode<"VEISD::VVP_FADD",  SDTFPBinOpVVP>;
167def c_vvp_fadd  : vvp_commutative<vvp_fadd>;
168def vvp_fsub    : SDNode<"VEISD::VVP_FSUB",  SDTFPBinOpVVP>;
169def vvp_fmul    : SDNode<"VEISD::VVP_FMUL",  SDTFPBinOpVVP>;
170def c_vvp_fmul  : vvp_commutative<vvp_fmul>;
171def vvp_fdiv    : SDNode<"VEISD::VVP_FDIV",  SDTFPBinOpVVP>;
172
173def vvp_ffma    : SDNode<"VEISD::VVP_FFMA",  SDTFPTernaryOpVVP>;
174def c_vvp_ffma  : vvp_fma_commutative<vvp_ffma>;
175
176def vvp_scatter : SDNode<"VEISD::VVP_SCATTER",  SDTScatterVVP,
177                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
178def vvp_gather  : SDNode<"VEISD::VVP_GATHER",  SDTGatherVVP,
179                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
180
181def vvp_load    : SDNode<"VEISD::VVP_LOAD",  SDTLoadVVP,
182                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand ]>;
183def vvp_store   : SDNode<"VEISD::VVP_STORE", SDTStoreVVP,
184                         [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
185
186// Reductions
187
188// int reductions
189def vvp_reduce_add          : SDNode<"VEISD::VVP_REDUCE_ADD", SDTReduceVVP>;
190def vvp_reduce_and          : SDNode<"VEISD::VVP_REDUCE_AND", SDTReduceVVP>;
191def vvp_reduce_or           : SDNode<"VEISD::VVP_REDUCE_OR",  SDTReduceVVP>;
192def vvp_reduce_xor          : SDNode<"VEISD::VVP_REDUCE_XOR", SDTReduceVVP>;
193def vvp_reduce_smax         : SDNode<"VEISD::VVP_REDUCE_SMAX", SDTReduceVVP>;
194
195
196def vvp_select : SDNode<"VEISD::VVP_SELECT", SDTSelectVVP>;
197
198// setcc (lhs, rhs, cc, mask, vl)
199def vvp_setcc  : SDNode<"VEISD::VVP_SETCC", SDTSetCCVVP>;
200