1//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 conditional move and set on condition
10// instructions.
11//
12//===----------------------------------------------------------------------===//
13
14
15// CMOV instructions.
16let isCodeGenOnly = 1, ForceDisassemble = 1 in {
17let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
18    isCommutable = 1, SchedRW = [WriteCMOV] in {
19  def CMOV16rr
20    : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
21        "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
22        [(set GR16:$dst,
23              (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
24              TB, OpSize16;
25  def CMOV32rr
26    : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
27        "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
28        [(set GR32:$dst,
29              (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
30              TB, OpSize32;
31  def CMOV64rr
32    :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
33        "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
34        [(set GR64:$dst,
35              (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
36}
37
38let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
39    SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
40  def CMOV16rm
41    : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
42        "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
43        [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
44                                  timm:$cond, EFLAGS))]>, TB, OpSize16;
45  def CMOV32rm
46    : I<0x40, MRMSrcMemCC, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2, ccode:$cond),
47        "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
48        [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
49                                  timm:$cond, EFLAGS))]>, TB, OpSize32;
50  def CMOV64rm
51    :RI<0x40, MRMSrcMemCC, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2, ccode:$cond),
52        "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
53        [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
54                                  timm:$cond, EFLAGS))]>, TB;
55} // Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst"
56} // isCodeGenOnly = 1, ForceDisassemble = 1
57
58def inv_cond_XFORM : SDNodeXForm<imm, [{
59  X86::CondCode CC = static_cast<X86::CondCode>(N->getZExtValue());
60  return CurDAG->getTargetConstant(X86::GetOppositeBranchCondition(CC),
61                                   SDLoc(N), MVT::i8);
62}]>;
63
64// Conditional moves with folded loads with operands swapped and conditions
65// inverted.
66let Predicates = [HasCMOV] in {
67  def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
68            (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
69  def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
70            (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
71  def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
72            (CMOV64rm GR64:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
73}
74
75// SetCC instructions.
76let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
77  def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
78                "set${cond}\t$dst",
79                [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
80                TB, Sched<[WriteSETCC]>;
81  def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
82                "set${cond}\t$dst",
83                [(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
84                TB, Sched<[WriteSETCCStore]>;
85} // Uses = [EFLAGS]
86
87// SALC is an undocumented instruction. Information for this instruction can be found
88// here http://www.rcollins.org/secrets/opcodes/SALC.html
89// Set AL if carry.
90let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
91  def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
92}
93