1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 #include "opt_capsicum.h" 35 #include "opt_ktrace.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/capsicum.h> 40 #include <sys/kernel.h> 41 #include <sys/ktrace.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/mutex.h> 45 #include <sys/pcpu.h> 46 #include <sys/priv.h> 47 #include <sys/proc.h> 48 #include <sys/smp.h> 49 #include <sys/sysproto.h> 50 #include <sys/uio.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 #include <vm/vm_kern.h> /* for kernel_map */ 55 #include <vm/vm_map.h> 56 #include <vm/vm_extern.h> 57 58 #include <machine/frame.h> 59 #include <machine/md_var.h> 60 #include <machine/pcb.h> 61 #include <machine/specialreg.h> 62 #include <machine/sysarch.h> 63 #include <machine/tss.h> 64 #include <machine/vmparam.h> 65 66 #include <security/audit/audit.h> 67 68 static void user_ldt_deref(struct proc_ldt *pldt); 69 static void user_ldt_derefl(struct proc_ldt *pldt); 70 71 #define MAX_LD 8192 72 73 int max_ldt_segment = 512; 74 SYSCTL_INT(_machdep, OID_AUTO, max_ldt_segment, CTLFLAG_RDTUN, 75 &max_ldt_segment, 0, 76 "Maximum number of allowed LDT segments in the single address space"); 77 78 static void 79 max_ldt_segment_init(void *arg __unused) 80 { 81 82 if (max_ldt_segment <= 0) 83 max_ldt_segment = 1; 84 if (max_ldt_segment > MAX_LD) 85 max_ldt_segment = MAX_LD; 86 } 87 SYSINIT(maxldt, SI_SUB_VM_CONF, SI_ORDER_ANY, max_ldt_segment_init, NULL); 88 89 #ifndef _SYS_SYSPROTO_H_ 90 struct sysarch_args { 91 int op; 92 char *parms; 93 }; 94 #endif 95 96 int 97 sysarch_ldt(struct thread *td, struct sysarch_args *uap, int uap_space) 98 { 99 struct i386_ldt_args *largs, la; 100 struct user_segment_descriptor *lp; 101 int error = 0; 102 103 /* 104 * XXXKIB check that the BSM generation code knows to encode 105 * the op argument. 106 */ 107 AUDIT_ARG_CMD(uap->op); 108 if (uap_space == UIO_USERSPACE) { 109 error = copyin(uap->parms, &la, sizeof(struct i386_ldt_args)); 110 if (error != 0) 111 return (error); 112 largs = &la; 113 } else 114 largs = (struct i386_ldt_args *)uap->parms; 115 116 switch (uap->op) { 117 case I386_GET_LDT: 118 error = amd64_get_ldt(td, largs); 119 break; 120 case I386_SET_LDT: 121 if (largs->descs != NULL && largs->num > max_ldt_segment) 122 return (EINVAL); 123 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 124 if (largs->descs != NULL) { 125 lp = malloc(largs->num * sizeof(struct 126 user_segment_descriptor), M_TEMP, M_WAITOK); 127 error = copyin(largs->descs, lp, largs->num * 128 sizeof(struct user_segment_descriptor)); 129 if (error == 0) 130 error = amd64_set_ldt(td, largs, lp); 131 free(lp, M_TEMP); 132 } else { 133 error = amd64_set_ldt(td, largs, NULL); 134 } 135 break; 136 } 137 return (error); 138 } 139 140 void 141 update_gdt_gsbase(struct thread *td, uint32_t base) 142 { 143 struct user_segment_descriptor *sd; 144 145 if (td != curthread) 146 return; 147 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 148 critical_enter(); 149 sd = PCPU_GET(gs32p); 150 sd->sd_lobase = base & 0xffffff; 151 sd->sd_hibase = (base >> 24) & 0xff; 152 critical_exit(); 153 } 154 155 void 156 update_gdt_fsbase(struct thread *td, uint32_t base) 157 { 158 struct user_segment_descriptor *sd; 159 160 if (td != curthread) 161 return; 162 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 163 critical_enter(); 164 sd = PCPU_GET(fs32p); 165 sd->sd_lobase = base & 0xffffff; 166 sd->sd_hibase = (base >> 24) & 0xff; 167 critical_exit(); 168 } 169 170 int 171 sysarch(struct thread *td, struct sysarch_args *uap) 172 { 173 struct pcb *pcb; 174 struct vm_map *map; 175 uint32_t i386base; 176 uint64_t a64base; 177 struct i386_ioperm_args iargs; 178 struct i386_get_xfpustate i386xfpu; 179 struct i386_set_pkru i386pkru; 180 struct amd64_get_xfpustate a64xfpu; 181 struct amd64_set_pkru a64pkru; 182 int error; 183 184 #ifdef CAPABILITY_MODE 185 /* 186 * When adding new operations, add a new case statement here to 187 * explicitly indicate whether or not the operation is safe to 188 * perform in capability mode. 189 */ 190 if (IN_CAPABILITY_MODE(td)) { 191 switch (uap->op) { 192 case I386_GET_LDT: 193 case I386_SET_LDT: 194 case I386_GET_IOPERM: 195 case I386_GET_FSBASE: 196 case I386_SET_FSBASE: 197 case I386_GET_GSBASE: 198 case I386_SET_GSBASE: 199 case I386_GET_XFPUSTATE: 200 case I386_SET_PKRU: 201 case I386_CLEAR_PKRU: 202 case AMD64_GET_FSBASE: 203 case AMD64_SET_FSBASE: 204 case AMD64_GET_GSBASE: 205 case AMD64_SET_GSBASE: 206 case AMD64_GET_XFPUSTATE: 207 case AMD64_SET_PKRU: 208 case AMD64_CLEAR_PKRU: 209 break; 210 211 case I386_SET_IOPERM: 212 default: 213 #ifdef KTRACE 214 if (KTRPOINT(td, KTR_CAPFAIL)) 215 ktrcapfail(CAPFAIL_SYSCALL, NULL, NULL); 216 #endif 217 return (ECAPMODE); 218 } 219 } 220 #endif 221 222 if (uap->op == I386_GET_LDT || uap->op == I386_SET_LDT) 223 return (sysarch_ldt(td, uap, UIO_USERSPACE)); 224 225 error = 0; 226 pcb = td->td_pcb; 227 228 /* 229 * XXXKIB check that the BSM generation code knows to encode 230 * the op argument. 231 */ 232 AUDIT_ARG_CMD(uap->op); 233 switch (uap->op) { 234 case I386_GET_IOPERM: 235 case I386_SET_IOPERM: 236 if ((error = copyin(uap->parms, &iargs, 237 sizeof(struct i386_ioperm_args))) != 0) 238 return (error); 239 break; 240 case I386_GET_XFPUSTATE: 241 if ((error = copyin(uap->parms, &i386xfpu, 242 sizeof(struct i386_get_xfpustate))) != 0) 243 return (error); 244 a64xfpu.addr = (void *)(uintptr_t)i386xfpu.addr; 245 a64xfpu.len = i386xfpu.len; 246 break; 247 case I386_SET_PKRU: 248 case I386_CLEAR_PKRU: 249 if ((error = copyin(uap->parms, &i386pkru, 250 sizeof(struct i386_set_pkru))) != 0) 251 return (error); 252 a64pkru.addr = (void *)(uintptr_t)i386pkru.addr; 253 a64pkru.len = i386pkru.len; 254 a64pkru.keyidx = i386pkru.keyidx; 255 a64pkru.flags = i386pkru.flags; 256 break; 257 case AMD64_GET_XFPUSTATE: 258 if ((error = copyin(uap->parms, &a64xfpu, 259 sizeof(struct amd64_get_xfpustate))) != 0) 260 return (error); 261 break; 262 case AMD64_SET_PKRU: 263 case AMD64_CLEAR_PKRU: 264 if ((error = copyin(uap->parms, &a64pkru, 265 sizeof(struct amd64_set_pkru))) != 0) 266 return (error); 267 break; 268 default: 269 break; 270 } 271 272 switch (uap->op) { 273 case I386_GET_IOPERM: 274 error = amd64_get_ioperm(td, &iargs); 275 if (error == 0) 276 error = copyout(&iargs, uap->parms, 277 sizeof(struct i386_ioperm_args)); 278 break; 279 case I386_SET_IOPERM: 280 error = amd64_set_ioperm(td, &iargs); 281 break; 282 case I386_GET_FSBASE: 283 update_pcb_bases(pcb); 284 i386base = pcb->pcb_fsbase; 285 error = copyout(&i386base, uap->parms, sizeof(i386base)); 286 break; 287 case I386_SET_FSBASE: 288 error = copyin(uap->parms, &i386base, sizeof(i386base)); 289 if (!error) { 290 set_pcb_flags(pcb, PCB_FULL_IRET); 291 pcb->pcb_fsbase = i386base; 292 td->td_frame->tf_fs = _ufssel; 293 update_gdt_fsbase(td, i386base); 294 } 295 break; 296 case I386_GET_GSBASE: 297 update_pcb_bases(pcb); 298 i386base = pcb->pcb_gsbase; 299 error = copyout(&i386base, uap->parms, sizeof(i386base)); 300 break; 301 case I386_SET_GSBASE: 302 error = copyin(uap->parms, &i386base, sizeof(i386base)); 303 if (!error) { 304 set_pcb_flags(pcb, PCB_FULL_IRET); 305 pcb->pcb_gsbase = i386base; 306 td->td_frame->tf_gs = _ugssel; 307 update_gdt_gsbase(td, i386base); 308 } 309 break; 310 case AMD64_GET_FSBASE: 311 update_pcb_bases(pcb); 312 error = copyout(&pcb->pcb_fsbase, uap->parms, 313 sizeof(pcb->pcb_fsbase)); 314 break; 315 316 case AMD64_SET_FSBASE: 317 error = copyin(uap->parms, &a64base, sizeof(a64base)); 318 if (!error) { 319 if (a64base < VM_MAXUSER_ADDRESS) { 320 set_pcb_flags(pcb, PCB_FULL_IRET); 321 pcb->pcb_fsbase = a64base; 322 td->td_frame->tf_fs = _ufssel; 323 } else 324 error = EINVAL; 325 } 326 break; 327 328 case AMD64_GET_GSBASE: 329 update_pcb_bases(pcb); 330 error = copyout(&pcb->pcb_gsbase, uap->parms, 331 sizeof(pcb->pcb_gsbase)); 332 break; 333 334 case AMD64_SET_GSBASE: 335 error = copyin(uap->parms, &a64base, sizeof(a64base)); 336 if (!error) { 337 if (a64base < VM_MAXUSER_ADDRESS) { 338 set_pcb_flags(pcb, PCB_FULL_IRET); 339 pcb->pcb_gsbase = a64base; 340 td->td_frame->tf_gs = _ugssel; 341 } else 342 error = EINVAL; 343 } 344 break; 345 346 case I386_GET_XFPUSTATE: 347 case AMD64_GET_XFPUSTATE: 348 if (a64xfpu.len > cpu_max_ext_state_size - 349 sizeof(struct savefpu)) 350 return (EINVAL); 351 fpugetregs(td); 352 error = copyout((char *)(get_pcb_user_save_td(td) + 1), 353 a64xfpu.addr, a64xfpu.len); 354 break; 355 356 case I386_SET_PKRU: 357 case AMD64_SET_PKRU: 358 /* 359 * Read-lock the map to synchronize with parallel 360 * pmap_vmspace_copy() on fork. 361 */ 362 map = &td->td_proc->p_vmspace->vm_map; 363 vm_map_lock_read(map); 364 error = pmap_pkru_set(PCPU_GET(curpmap), 365 (vm_offset_t)a64pkru.addr, (vm_offset_t)a64pkru.addr + 366 a64pkru.len, a64pkru.keyidx, a64pkru.flags); 367 vm_map_unlock_read(map); 368 break; 369 370 case I386_CLEAR_PKRU: 371 case AMD64_CLEAR_PKRU: 372 if (a64pkru.flags != 0 || a64pkru.keyidx != 0) { 373 error = EINVAL; 374 break; 375 } 376 map = &td->td_proc->p_vmspace->vm_map; 377 vm_map_lock_read(map); 378 error = pmap_pkru_clear(PCPU_GET(curpmap), 379 (vm_offset_t)a64pkru.addr, 380 (vm_offset_t)a64pkru.addr + a64pkru.len); 381 vm_map_unlock_read(map); 382 break; 383 384 default: 385 error = EINVAL; 386 break; 387 } 388 return (error); 389 } 390 391 int 392 amd64_set_ioperm(struct thread *td, struct i386_ioperm_args *uap) 393 { 394 char *iomap; 395 struct amd64tss *tssp; 396 struct system_segment_descriptor *tss_sd; 397 struct pcb *pcb; 398 u_int i; 399 int error; 400 401 if ((error = priv_check(td, PRIV_IO)) != 0) 402 return (error); 403 if ((error = securelevel_gt(td->td_ucred, 0)) != 0) 404 return (error); 405 if (uap->start > uap->start + uap->length || 406 uap->start + uap->length > IOPAGES * PAGE_SIZE * NBBY) 407 return (EINVAL); 408 409 /* 410 * XXX 411 * While this is restricted to root, we should probably figure out 412 * whether any other driver is using this i/o address, as so not to 413 * cause confusion. This probably requires a global 'usage registry'. 414 */ 415 pcb = td->td_pcb; 416 if (pcb->pcb_tssp == NULL) { 417 tssp = kmem_malloc(ctob(IOPAGES + 1), M_WAITOK); 418 pmap_pti_add_kva((vm_offset_t)tssp, (vm_offset_t)tssp + 419 ctob(IOPAGES + 1), false); 420 iomap = (char *)&tssp[1]; 421 memset(iomap, 0xff, IOPERM_BITMAP_SIZE); 422 critical_enter(); 423 /* Takes care of tss_rsp0. */ 424 memcpy(tssp, PCPU_PTR(common_tss), sizeof(struct amd64tss)); 425 tssp->tss_iobase = sizeof(*tssp); 426 pcb->pcb_tssp = tssp; 427 tss_sd = PCPU_GET(tss); 428 tss_sd->sd_lobase = (u_long)tssp & 0xffffff; 429 tss_sd->sd_hibase = ((u_long)tssp >> 24) & 0xfffffffffful; 430 tss_sd->sd_type = SDT_SYSTSS; 431 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 432 PCPU_SET(tssp, tssp); 433 critical_exit(); 434 } else 435 iomap = (char *)&pcb->pcb_tssp[1]; 436 for (i = uap->start; i < uap->start + uap->length; i++) { 437 if (uap->enable) 438 iomap[i >> 3] &= ~(1 << (i & 7)); 439 else 440 iomap[i >> 3] |= (1 << (i & 7)); 441 } 442 return (error); 443 } 444 445 int 446 amd64_get_ioperm(struct thread *td, struct i386_ioperm_args *uap) 447 { 448 int i, state; 449 char *iomap; 450 451 if (uap->start >= IOPAGES * PAGE_SIZE * NBBY) 452 return (EINVAL); 453 if (td->td_pcb->pcb_tssp == NULL) { 454 uap->length = 0; 455 goto done; 456 } 457 458 iomap = (char *)&td->td_pcb->pcb_tssp[1]; 459 460 i = uap->start; 461 state = (iomap[i >> 3] >> (i & 7)) & 1; 462 uap->enable = !state; 463 uap->length = 1; 464 465 for (i = uap->start + 1; i < IOPAGES * PAGE_SIZE * NBBY; i++) { 466 if (state != ((iomap[i >> 3] >> (i & 7)) & 1)) 467 break; 468 uap->length++; 469 } 470 471 done: 472 return (0); 473 } 474 475 /* 476 * Update the GDT entry pointing to the LDT to point to the LDT of the 477 * current process. 478 */ 479 static void 480 set_user_ldt(struct mdproc *mdp) 481 { 482 483 *PCPU_GET(ldt) = mdp->md_ldt_sd; 484 lldt(GSEL(GUSERLDT_SEL, SEL_KPL)); 485 } 486 487 static void 488 set_user_ldt_rv(void *arg) 489 { 490 struct proc *orig, *target; 491 struct proc_ldt *ldt; 492 493 orig = arg; 494 target = curthread->td_proc; 495 496 ldt = (void *)atomic_load_acq_ptr((uintptr_t *)&orig->p_md.md_ldt); 497 if (target->p_md.md_ldt != ldt) 498 return; 499 500 set_user_ldt(&target->p_md); 501 } 502 503 struct proc_ldt * 504 user_ldt_alloc(struct proc *p, int force) 505 { 506 struct proc_ldt *pldt, *new_ldt; 507 struct mdproc *mdp; 508 struct soft_segment_descriptor sldt; 509 vm_offset_t sva; 510 vm_size_t sz; 511 512 mtx_assert(&dt_lock, MA_OWNED); 513 mdp = &p->p_md; 514 if (!force && mdp->md_ldt != NULL) 515 return (mdp->md_ldt); 516 mtx_unlock(&dt_lock); 517 new_ldt = malloc(sizeof(struct proc_ldt), M_SUBPROC, M_WAITOK); 518 sz = max_ldt_segment * sizeof(struct user_segment_descriptor); 519 new_ldt->ldt_base = kmem_malloc(sz, M_WAITOK | M_ZERO); 520 sva = (uintptr_t)new_ldt->ldt_base; 521 pmap_pti_add_kva(sva, sva + sz, false); 522 new_ldt->ldt_refcnt = 1; 523 sldt.ssd_base = sva; 524 sldt.ssd_limit = sz - 1; 525 sldt.ssd_type = SDT_SYSLDT; 526 sldt.ssd_dpl = SEL_KPL; 527 sldt.ssd_p = 1; 528 sldt.ssd_long = 0; 529 sldt.ssd_def32 = 0; 530 sldt.ssd_gran = 0; 531 mtx_lock(&dt_lock); 532 pldt = mdp->md_ldt; 533 if (pldt != NULL && !force) { 534 pmap_pti_remove_kva(sva, sva + sz); 535 kmem_free(new_ldt->ldt_base, sz); 536 free(new_ldt, M_SUBPROC); 537 return (pldt); 538 } 539 540 if (pldt != NULL) { 541 bcopy(pldt->ldt_base, new_ldt->ldt_base, max_ldt_segment * 542 sizeof(struct user_segment_descriptor)); 543 user_ldt_derefl(pldt); 544 } 545 critical_enter(); 546 ssdtosyssd(&sldt, &p->p_md.md_ldt_sd); 547 atomic_thread_fence_rel(); 548 mdp->md_ldt = new_ldt; 549 critical_exit(); 550 smp_rendezvous(NULL, set_user_ldt_rv, NULL, p); 551 552 return (mdp->md_ldt); 553 } 554 555 void 556 user_ldt_free(struct thread *td) 557 { 558 struct proc *p = td->td_proc; 559 struct mdproc *mdp = &p->p_md; 560 struct proc_ldt *pldt; 561 562 mtx_lock(&dt_lock); 563 if ((pldt = mdp->md_ldt) == NULL) { 564 mtx_unlock(&dt_lock); 565 return; 566 } 567 568 critical_enter(); 569 mdp->md_ldt = NULL; 570 atomic_thread_fence_rel(); 571 bzero(&mdp->md_ldt_sd, sizeof(mdp->md_ldt_sd)); 572 if (td == curthread) 573 lldt(GSEL(GNULL_SEL, SEL_KPL)); 574 critical_exit(); 575 user_ldt_deref(pldt); 576 } 577 578 static void 579 user_ldt_derefl(struct proc_ldt *pldt) 580 { 581 vm_offset_t sva; 582 vm_size_t sz; 583 584 if (--pldt->ldt_refcnt == 0) { 585 sva = (vm_offset_t)pldt->ldt_base; 586 sz = max_ldt_segment * sizeof(struct user_segment_descriptor); 587 pmap_pti_remove_kva(sva, sva + sz); 588 kmem_free(pldt->ldt_base, sz); 589 free(pldt, M_SUBPROC); 590 } 591 } 592 593 static void 594 user_ldt_deref(struct proc_ldt *pldt) 595 { 596 597 mtx_assert(&dt_lock, MA_OWNED); 598 user_ldt_derefl(pldt); 599 mtx_unlock(&dt_lock); 600 } 601 602 /* 603 * Note for the authors of compat layers (linux, etc): copyout() in 604 * the function below is not a problem since it presents data in 605 * arch-specific format (i.e. i386-specific in this case), not in 606 * the OS-specific one. 607 */ 608 int 609 amd64_get_ldt(struct thread *td, struct i386_ldt_args *uap) 610 { 611 struct proc_ldt *pldt; 612 struct user_segment_descriptor *lp; 613 uint64_t *data; 614 u_int i, num; 615 int error; 616 617 #ifdef DEBUG 618 printf("amd64_get_ldt: start=%u num=%u descs=%p\n", 619 uap->start, uap->num, (void *)uap->descs); 620 #endif 621 622 pldt = td->td_proc->p_md.md_ldt; 623 if (pldt == NULL || uap->start >= max_ldt_segment || uap->num == 0) { 624 td->td_retval[0] = 0; 625 return (0); 626 } 627 num = min(uap->num, max_ldt_segment - uap->start); 628 lp = &((struct user_segment_descriptor *)(pldt->ldt_base))[uap->start]; 629 data = malloc(num * sizeof(struct user_segment_descriptor), M_TEMP, 630 M_WAITOK); 631 mtx_lock(&dt_lock); 632 for (i = 0; i < num; i++) 633 data[i] = ((volatile uint64_t *)lp)[i]; 634 mtx_unlock(&dt_lock); 635 error = copyout(data, uap->descs, num * 636 sizeof(struct user_segment_descriptor)); 637 free(data, M_TEMP); 638 if (error == 0) 639 td->td_retval[0] = num; 640 return (error); 641 } 642 643 int 644 amd64_set_ldt(struct thread *td, struct i386_ldt_args *uap, 645 struct user_segment_descriptor *descs) 646 { 647 struct mdproc *mdp; 648 struct proc_ldt *pldt; 649 struct user_segment_descriptor *dp; 650 struct proc *p; 651 u_int largest_ld, i; 652 int error; 653 654 #ifdef DEBUG 655 printf("amd64_set_ldt: start=%u num=%u descs=%p\n", 656 uap->start, uap->num, (void *)uap->descs); 657 #endif 658 mdp = &td->td_proc->p_md; 659 error = 0; 660 661 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 662 p = td->td_proc; 663 if (descs == NULL) { 664 /* Free descriptors */ 665 if (uap->start == 0 && uap->num == 0) 666 uap->num = max_ldt_segment; 667 if (uap->num == 0) 668 return (EINVAL); 669 if ((pldt = mdp->md_ldt) == NULL || 670 uap->start >= max_ldt_segment) 671 return (0); 672 largest_ld = uap->start + uap->num; 673 if (largest_ld > max_ldt_segment) 674 largest_ld = max_ldt_segment; 675 if (largest_ld < uap->start) 676 return (EINVAL); 677 mtx_lock(&dt_lock); 678 for (i = uap->start; i < largest_ld; i++) 679 ((volatile uint64_t *)(pldt->ldt_base))[i] = 0; 680 mtx_unlock(&dt_lock); 681 return (0); 682 } 683 684 if (!(uap->start == LDT_AUTO_ALLOC && uap->num == 1)) { 685 /* verify range of descriptors to modify */ 686 largest_ld = uap->start + uap->num; 687 if (uap->start >= max_ldt_segment || 688 largest_ld > max_ldt_segment || 689 largest_ld < uap->start) 690 return (EINVAL); 691 } 692 693 /* Check descriptors for access violations */ 694 for (i = 0; i < uap->num; i++) { 695 dp = &descs[i]; 696 697 switch (dp->sd_type) { 698 case SDT_SYSNULL: /* system null */ 699 dp->sd_p = 0; 700 break; 701 case SDT_SYS286TSS: 702 case SDT_SYSLDT: 703 case SDT_SYS286BSY: 704 case SDT_SYS286CGT: 705 case SDT_SYSTASKGT: 706 case SDT_SYS286IGT: 707 case SDT_SYS286TGT: 708 case SDT_SYSNULL2: 709 case SDT_SYSTSS: 710 case SDT_SYSNULL3: 711 case SDT_SYSBSY: 712 case SDT_SYSCGT: 713 case SDT_SYSNULL4: 714 case SDT_SYSIGT: 715 case SDT_SYSTGT: 716 return (EACCES); 717 718 /* memory segment types */ 719 case SDT_MEMEC: /* memory execute only conforming */ 720 case SDT_MEMEAC: /* memory execute only accessed conforming */ 721 case SDT_MEMERC: /* memory execute read conforming */ 722 case SDT_MEMERAC: /* memory execute read accessed conforming */ 723 /* Must be "present" if executable and conforming. */ 724 if (dp->sd_p == 0) 725 return (EACCES); 726 break; 727 case SDT_MEMRO: /* memory read only */ 728 case SDT_MEMROA: /* memory read only accessed */ 729 case SDT_MEMRW: /* memory read write */ 730 case SDT_MEMRWA: /* memory read write accessed */ 731 case SDT_MEMROD: /* memory read only expand dwn limit */ 732 case SDT_MEMRODA: /* memory read only expand dwn lim accessed */ 733 case SDT_MEMRWD: /* memory read write expand dwn limit */ 734 case SDT_MEMRWDA: /* memory read write expand dwn lim acessed */ 735 case SDT_MEME: /* memory execute only */ 736 case SDT_MEMEA: /* memory execute only accessed */ 737 case SDT_MEMER: /* memory execute read */ 738 case SDT_MEMERA: /* memory execute read accessed */ 739 break; 740 default: 741 return(EINVAL); 742 } 743 744 /* Only user (ring-3) descriptors may be present. */ 745 if ((dp->sd_p != 0) && (dp->sd_dpl != SEL_UPL)) 746 return (EACCES); 747 } 748 749 if (uap->start == LDT_AUTO_ALLOC && uap->num == 1) { 750 /* Allocate a free slot */ 751 mtx_lock(&dt_lock); 752 pldt = user_ldt_alloc(p, 0); 753 if (pldt == NULL) { 754 mtx_unlock(&dt_lock); 755 return (ENOMEM); 756 } 757 758 /* 759 * start scanning a bit up to leave room for NVidia and 760 * Wine, which still user the "Blat" method of allocation. 761 */ 762 i = 16; 763 dp = &((struct user_segment_descriptor *)(pldt->ldt_base))[i]; 764 for (; i < max_ldt_segment; ++i, ++dp) { 765 if (dp->sd_type == SDT_SYSNULL) 766 break; 767 } 768 if (i >= max_ldt_segment) { 769 mtx_unlock(&dt_lock); 770 return (ENOSPC); 771 } 772 uap->start = i; 773 error = amd64_set_ldt_data(td, i, 1, descs); 774 mtx_unlock(&dt_lock); 775 } else { 776 largest_ld = uap->start + uap->num; 777 if (largest_ld > max_ldt_segment) 778 return (EINVAL); 779 mtx_lock(&dt_lock); 780 if (user_ldt_alloc(p, 0) != NULL) { 781 error = amd64_set_ldt_data(td, uap->start, uap->num, 782 descs); 783 } 784 mtx_unlock(&dt_lock); 785 } 786 if (error == 0) 787 td->td_retval[0] = uap->start; 788 return (error); 789 } 790 791 int 792 amd64_set_ldt_data(struct thread *td, int start, int num, 793 struct user_segment_descriptor *descs) 794 { 795 struct mdproc *mdp; 796 struct proc_ldt *pldt; 797 volatile uint64_t *dst, *src; 798 int i; 799 800 mtx_assert(&dt_lock, MA_OWNED); 801 802 mdp = &td->td_proc->p_md; 803 pldt = mdp->md_ldt; 804 dst = (volatile uint64_t *)(pldt->ldt_base); 805 src = (volatile uint64_t *)descs; 806 for (i = 0; i < num; i++) 807 dst[start + i] = src[i]; 808 return (0); 809 } 810