1 /*- 2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #ifndef _AMD64_SGX_SGXVAR_H_ 33 #define _AMD64_SGX_SGXVAR_H_ 34 35 #define SGX_CPUID 0x12 36 #define SGX_PAGE_SIZE 4096 37 #define SGX_VA_PAGE_SLOTS 512 38 #define SGX_VA_PAGES_OFFS 512 39 #define SGX_SECS_VM_OBJECT_INDEX -1 40 #define SGX_SIGSTRUCT_SIZE 1808 41 #define SGX_EINITTOKEN_SIZE 304 42 #define SGX_IOCTL_MAX_DATA_LEN 26 43 #define SGX_ENCL_SIZE_MAX_DEF 0x1000000000ULL 44 #define SGX_EFAULT 99 45 46 #ifndef LOCORE 47 static MALLOC_DEFINE(M_SGX, "sgx", "SGX driver"); 48 49 struct sgx_vm_handle { 50 struct sgx_softc *sc; 51 vm_object_t mem; 52 uint64_t base; 53 vm_size_t size; 54 struct sgx_enclave *enclave; 55 }; 56 57 /* EPC (Enclave Page Cache) page. */ 58 struct epc_page { 59 uint64_t base; 60 uint64_t phys; 61 int index; 62 }; 63 64 struct sgx_enclave { 65 uint64_t base; 66 uint64_t size; 67 struct sgx_vm_handle *vmh; 68 TAILQ_ENTRY(sgx_enclave) next; 69 vm_object_t object; 70 struct epc_page *secs_epc_page; 71 }; 72 73 struct sgx_softc { 74 struct cdev *sgx_cdev; 75 struct mtx mtx_encls; 76 struct mtx mtx; 77 uint64_t epc_base; 78 uint64_t epc_size; 79 struct epc_page *epc_pages; 80 struct vmem *vmem_epc; 81 uint32_t npages; 82 TAILQ_HEAD(, sgx_enclave) enclaves; 83 uint64_t enclave_size_max; 84 uint8_t state; 85 #define SGX_STATE_RUNNING (1 << 0) 86 }; 87 #endif /* !LOCORE */ 88 89 #endif /* !_AMD64_SGX_SGXVAR_H_ */ 90