1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Clocks and power control driver for Freescale i.MX6 family of SoCs. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include <machine/bus.h> 45 46 #include <arm/freescale/imx/imx6_anatopreg.h> 47 #include <arm/freescale/imx/imx6_anatopvar.h> 48 #include <arm/freescale/imx/imx6_ccmreg.h> 49 #include <arm/freescale/imx/imx_machdep.h> 50 #include <arm/freescale/imx/imx_ccmvar.h> 51 52 #ifndef CCGR_CLK_MODE_ALWAYS 53 #define CCGR_CLK_MODE_OFF 0 54 #define CCGR_CLK_MODE_RUNMODE 1 55 #define CCGR_CLK_MODE_ALWAYS 3 56 #endif 57 58 struct ccm_softc { 59 device_t dev; 60 struct resource *mem_res; 61 }; 62 63 static struct ccm_softc *ccm_sc; 64 65 static inline uint32_t 66 RD4(struct ccm_softc *sc, bus_size_t off) 67 { 68 69 return (bus_read_4(sc->mem_res, off)); 70 } 71 72 static inline void 73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) 74 { 75 76 bus_write_4(sc->mem_res, off, val); 77 } 78 79 /* 80 * Until we have a fully functional ccm driver which implements the fdt_clock 81 * interface, use the age-old workaround of unconditionally enabling the clocks 82 * for devices we might need to use. The SoC defaults to most clocks enabled, 83 * but the rom boot code and u-boot disable a few of them. We turn on only 84 * what's needed to run the chip plus devices we have drivers for, and turn off 85 * devices we don't yet have drivers for. (Note that USB is not turned on here 86 * because that is one we do when the driver asks for it.) 87 */ 88 static void 89 ccm_init_gates(struct ccm_softc *sc) 90 { 91 uint32_t reg; 92 93 /* ahpbdma, aipstz 1 & 2 buses */ 94 reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; 95 WR4(sc, CCM_CCGR0, reg); 96 97 /* enet, epit, gpt */ 98 reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT; 99 WR4(sc, CCM_CCGR1, reg); 100 101 /* ipmux & ipsync (bridges), iomux, i2c */ 102 reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | 103 CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 | 104 CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 | 105 CCGR2_IPSYNC_VDOA; 106 WR4(sc, CCM_CCGR2, reg); 107 108 /* DDR memory controller */ 109 reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | 110 CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13; 111 WR4(sc, CCM_CCGR3, reg); 112 113 /* pl301 bus crossbar */ 114 reg = CCGR4_PL301_MX6QFAST1_S133 | 115 CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN; 116 WR4(sc, CCM_CCGR4, reg); 117 118 /* uarts, ssi, sdma */ 119 reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 | 120 CCGR5_UART | CCGR5_UART_SERIAL; 121 WR4(sc, CCM_CCGR5, reg); 122 123 /* usdhc 1-4, usboh3 */ 124 reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 | 125 CCGR6_USDHC3 | CCGR6_USDHC4; 126 WR4(sc, CCM_CCGR6, reg); 127 } 128 129 static int 130 ccm_detach(device_t dev) 131 { 132 struct ccm_softc *sc; 133 134 sc = device_get_softc(dev); 135 136 if (sc->mem_res != NULL) 137 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 138 139 return (0); 140 } 141 142 static int 143 ccm_attach(device_t dev) 144 { 145 struct ccm_softc *sc; 146 int err, rid; 147 uint32_t reg; 148 149 sc = device_get_softc(dev); 150 err = 0; 151 152 /* Allocate bus_space resources. */ 153 rid = 0; 154 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 155 RF_ACTIVE); 156 if (sc->mem_res == NULL) { 157 device_printf(dev, "Cannot allocate memory resources\n"); 158 err = ENXIO; 159 goto out; 160 } 161 162 ccm_sc = sc; 163 164 /* 165 * Configure the Low Power Mode setting to leave the ARM core power on 166 * when a WFI instruction is executed. This lets the MPCore timers and 167 * GIC continue to run, which is helpful when the only thing that can 168 * wake you up is an MPCore Private Timer interrupt delivered via GIC. 169 * 170 * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be 171 * required when the LPM bits are set to LPM_RUN. But experimentally 172 * I've experienced a fairly rare lockup when not setting it. I was 173 * unable to prove conclusively that the lockup was related to power 174 * management or that this definitively fixes it. Revisit this. 175 */ 176 reg = RD4(sc, CCM_CGPR); 177 reg |= CCM_CGPR_INT_MEM_CLK_LPM; 178 WR4(sc, CCM_CGPR, reg); 179 reg = RD4(sc, CCM_CLPCR); 180 reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; 181 WR4(sc, CCM_CLPCR, reg); 182 183 ccm_init_gates(sc); 184 185 err = 0; 186 187 out: 188 189 if (err != 0) 190 ccm_detach(dev); 191 192 return (err); 193 } 194 195 static int 196 ccm_probe(device_t dev) 197 { 198 199 if (!ofw_bus_status_okay(dev)) 200 return (ENXIO); 201 202 if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) 203 return (ENXIO); 204 205 device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); 206 207 return (BUS_PROBE_DEFAULT); 208 } 209 210 void 211 imx_ccm_ssi_configure(device_t _ssidev) 212 { 213 struct ccm_softc *sc; 214 uint32_t reg; 215 216 sc = ccm_sc; 217 218 /* 219 * Select PLL4 (Audio PLL) clock multiplexer as source. 220 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). 221 */ 222 223 reg = RD4(sc, CCM_CSCMR1); 224 reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S); 225 reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S); 226 reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S); 227 reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S); 228 reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S); 229 reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S); 230 WR4(sc, CCM_CSCMR1, reg); 231 232 /* 233 * Ensure we have set hardware-default values 234 * for pre and post dividers. 235 */ 236 237 /* SSI1 and SSI3 */ 238 reg = RD4(sc, CCM_CS1CDR); 239 /* Divide by 2 */ 240 reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT); 241 reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT); 242 reg |= (0x1 << SSI1_CLK_PODF_SHIFT); 243 reg |= (0x1 << SSI3_CLK_PODF_SHIFT); 244 /* Divide by 4 */ 245 reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT); 246 reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT); 247 reg |= (0x3 << SSI1_CLK_PRED_SHIFT); 248 reg |= (0x3 << SSI3_CLK_PRED_SHIFT); 249 WR4(sc, CCM_CS1CDR, reg); 250 251 /* SSI2 */ 252 reg = RD4(sc, CCM_CS2CDR); 253 /* Divide by 2 */ 254 reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT); 255 reg |= (0x1 << SSI2_CLK_PODF_SHIFT); 256 /* Divide by 4 */ 257 reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT); 258 reg |= (0x3 << SSI2_CLK_PRED_SHIFT); 259 WR4(sc, CCM_CS2CDR, reg); 260 } 261 262 void 263 imx_ccm_usb_enable(device_t _usbdev) 264 { 265 266 /* 267 * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for 268 * shifting and masking here, just set the low-order two bits to ALWAYS. 269 */ 270 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); 271 } 272 273 void 274 imx_ccm_usbphy_enable(device_t _phydev) 275 { 276 /* 277 * XXX Which unit? 278 * Right now it's not clear how to figure from fdt data which phy unit 279 * we're supposed to operate on. Until this is worked out, just enable 280 * both PHYs. 281 */ 282 #if 0 283 int phy_num, regoff; 284 285 phy_num = 0; /* XXX */ 286 287 switch (phy_num) { 288 case 0: 289 regoff = 0; 290 break; 291 case 1: 292 regoff = 0x10; 293 break; 294 default: 295 device_printf(ccm_sc->dev, "Bad PHY number %u,\n", 296 phy_num); 297 return; 298 } 299 300 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, 301 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 302 IMX6_ANALOG_CCM_PLL_USB_POWER | 303 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 304 #else 305 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, 306 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 307 IMX6_ANALOG_CCM_PLL_USB_POWER | 308 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 309 310 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, 311 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 312 IMX6_ANALOG_CCM_PLL_USB_POWER | 313 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 314 #endif 315 } 316 317 uint32_t 318 imx_ccm_ipg_hz(void) 319 { 320 321 return (66000000); 322 } 323 324 uint32_t 325 imx_ccm_perclk_hz(void) 326 { 327 328 return (66000000); 329 } 330 331 uint32_t 332 imx_ccm_sdhci_hz(void) 333 { 334 335 return (200000000); 336 } 337 338 uint32_t 339 imx_ccm_uart_hz(void) 340 { 341 342 return (80000000); 343 } 344 345 uint32_t 346 imx_ccm_ahb_hz(void) 347 { 348 return (132000000); 349 } 350 351 void 352 imx_ccm_ipu_enable(int ipu) 353 { 354 struct ccm_softc *sc; 355 uint32_t reg; 356 357 sc = ccm_sc; 358 reg = RD4(sc, CCM_CCGR3); 359 if (ipu == 1) 360 reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0; 361 else 362 reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0; 363 WR4(sc, CCM_CCGR3, reg); 364 } 365 366 void 367 imx_ccm_hdmi_enable(void) 368 { 369 struct ccm_softc *sc; 370 uint32_t reg; 371 372 sc = ccm_sc; 373 reg = RD4(sc, CCM_CCGR2); 374 reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR; 375 WR4(sc, CCM_CCGR2, reg); 376 377 /* Set HDMI clock to 280MHz */ 378 reg = RD4(sc, CCM_CHSCCDR); 379 reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | 380 CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 381 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT); 382 reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); 383 WR4(sc, CCM_CHSCCDR, reg); 384 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT); 385 WR4(sc, CCM_CHSCCDR, reg); 386 } 387 388 uint32_t 389 imx_ccm_get_cacrr(void) 390 { 391 392 return (RD4(ccm_sc, CCM_CACCR)); 393 } 394 395 void 396 imx_ccm_set_cacrr(uint32_t divisor) 397 { 398 399 WR4(ccm_sc, CCM_CACCR, divisor); 400 } 401 402 static device_method_t ccm_methods[] = { 403 /* Device interface */ 404 DEVMETHOD(device_probe, ccm_probe), 405 DEVMETHOD(device_attach, ccm_attach), 406 DEVMETHOD(device_detach, ccm_detach), 407 408 DEVMETHOD_END 409 }; 410 411 static driver_t ccm_driver = { 412 "ccm", 413 ccm_methods, 414 sizeof(struct ccm_softc) 415 }; 416 417 static devclass_t ccm_devclass; 418 419 EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, 420 BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 421 422