1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright (c) 1997 Mark Brinicombe.
7 * Copyright (c) 1997 Causality Limited
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Causality Limited.
21 * 4. The name of Causality Limited may not be used to endorse or promote
22 * products derived from this software without specific prior written
23 * permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * cpufunc.h
40 *
41 * Prototypes for cpu, mmu and tlb related functions.
42 */
43
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
46
47 #ifdef _KERNEL
48
49 #include <sys/types.h>
50 #include <machine/armreg.h>
51
52 static __inline void
breakpoint(void)53 breakpoint(void)
54 {
55 __asm("udf 0xffff");
56 }
57
58 struct cpu_functions {
59 /* CPU functions */
60 void (*cf_l2cache_wbinv_all) (void);
61 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
62 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
63 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
64 void (*cf_l2cache_drain_writebuf) (void);
65
66 /* Other functions */
67
68 void (*cf_sleep) (int mode);
69
70 void (*cf_setup) (void);
71 };
72
73 extern struct cpu_functions cpufuncs;
74 extern u_int cputype;
75
76 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
77 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
78 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
79 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
80 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
81
82 #define cpu_sleep(m) cpufuncs.cf_sleep(m)
83
84 #define cpu_setup() cpufuncs.cf_setup()
85
86 int set_cpufuncs (void);
87 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
88
89 void cpufunc_nullop (void);
90 u_int cpufunc_control (u_int clear, u_int bic);
91
92
93 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
94 void armv7_cpu_sleep (int);
95 #endif
96 #if defined(CPU_MV_PJ4B)
97 void pj4b_config (void);
98 #endif
99
100 #if defined(CPU_ARM1176)
101 void arm11x6_sleep (int); /* no ref. for errata */
102 #endif
103
104
105 /*
106 * Macros for manipulating CPU interrupts
107 */
108 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
109
110 static __inline uint32_t
__set_cpsr(uint32_t bic,uint32_t eor)111 __set_cpsr(uint32_t bic, uint32_t eor)
112 {
113 uint32_t tmp, ret;
114
115 __asm __volatile(
116 "mrs %0, cpsr\n" /* Get the CPSR */
117 "bic %1, %0, %2\n" /* Clear bits */
118 "eor %1, %1, %3\n" /* XOR bits */
119 "msr cpsr_xc, %1\n" /* Set the CPSR */
120 : "=&r" (ret), "=&r" (tmp)
121 : "r" (bic), "r" (eor) : "memory");
122
123 return ret;
124 }
125
126 static __inline uint32_t
disable_interrupts(uint32_t mask)127 disable_interrupts(uint32_t mask)
128 {
129
130 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
131 }
132
133 static __inline uint32_t
enable_interrupts(uint32_t mask)134 enable_interrupts(uint32_t mask)
135 {
136
137 return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
138 }
139
140 static __inline uint32_t
restore_interrupts(uint32_t old_cpsr)141 restore_interrupts(uint32_t old_cpsr)
142 {
143
144 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
145 }
146
147 static __inline register_t
intr_disable(void)148 intr_disable(void)
149 {
150
151 return (disable_interrupts(PSR_I | PSR_F));
152 }
153
154 static __inline void
intr_restore(register_t s)155 intr_restore(register_t s)
156 {
157
158 restore_interrupts(s);
159 }
160 #undef __ARM_INTR_BITS
161
162 /*
163 * Functions to manipulate cpu r13
164 * (in arm/arm32/setstack.S)
165 */
166
167 void set_stackptr (u_int mode, u_int address);
168 u_int get_stackptr (u_int mode);
169
170 /*
171 * CPU functions from locore.S
172 */
173
174 void cpu_reset (void) __attribute__((__noreturn__));
175
176 /*
177 * Cache info variables.
178 */
179
180 /* PRIMARY CACHE VARIABLES */
181 extern unsigned int arm_dcache_align;
182 extern unsigned int arm_dcache_align_mask;
183
184 #else /* !_KERNEL */
185
186 static __inline void
breakpoint(void)187 breakpoint(void)
188 {
189
190 /*
191 * This matches the instruction used by GDB for software
192 * breakpoints.
193 */
194 __asm("udf 0xfdee");
195 }
196
197 #endif /* _KERNEL */
198 #endif /* _MACHINE_CPUFUNC_H_ */
199
200 /* End of cpufunc.h */
201