1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/cpuconf.h> 51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53 static __inline void 54 breakpoint(void) 55 { 56 __asm(".word 0xe7ffffff"); 57 } 58 59 struct cpu_functions { 60 61 /* CPU functions */ 62 63 u_int (*cf_id) (void); 64 void (*cf_cpwait) (void); 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_domains) (u_int domains); 70 void (*cf_setttb) (u_int ttb); 71 u_int (*cf_faultstatus) (void); 72 u_int (*cf_faultaddress) (void); 73 74 /* TLB functions */ 75 76 void (*cf_tlb_flushID) (void); 77 void (*cf_tlb_flushID_SE) (u_int va); 78 void (*cf_tlb_flushI) (void); 79 void (*cf_tlb_flushI_SE) (u_int va); 80 void (*cf_tlb_flushD) (void); 81 void (*cf_tlb_flushD_SE) (u_int va); 82 83 /* 84 * Cache operations: 85 * 86 * We define the following primitives: 87 * 88 * icache_sync_all Synchronize I-cache 89 * icache_sync_range Synchronize I-cache range 90 * 91 * dcache_wbinv_all Write-back and Invalidate D-cache 92 * dcache_wbinv_range Write-back and Invalidate D-cache range 93 * dcache_inv_range Invalidate D-cache range 94 * dcache_wb_range Write-back D-cache range 95 * 96 * idcache_wbinv_all Write-back and Invalidate D-cache, 97 * Invalidate I-cache 98 * idcache_wbinv_range Write-back and Invalidate D-cache, 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * 107 * I-cache Synch (all or range): 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: 115 * If you can't WB-Inv a range, you must WB-Inv the 116 * entire D-cache. 117 * 118 * D-cache Invalidate: 119 * If you can't Inv the D-cache, you must Write-Back 120 * and Invalidate. Code that uses this operation 121 * MUST NOT assume that the D-cache will not be written 122 * back to memory. 123 * 124 * D-cache Write-Back: 125 * If you can't Write-back without doing an Inv, 126 * that's fine. Then treat this as a WB-Inv. 127 * Skipping the invalidate is merely an optimization. 128 * 129 * All operations: 130 * Valid virtual addresses must be passed to each 131 * cache operation. 132 */ 133 void (*cf_icache_sync_all) (void); 134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140 141 void (*cf_idcache_wbinv_all) (void); 142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143 void (*cf_l2cache_wbinv_all) (void); 144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 147 148 /* Other functions */ 149 150 void (*cf_flush_prefetchbuf) (void); 151 void (*cf_drain_writebuf) (void); 152 void (*cf_flush_brnchtgt_C) (void); 153 void (*cf_flush_brnchtgt_E) (u_int va); 154 155 void (*cf_sleep) (int mode); 156 157 /* Soft functions */ 158 159 int (*cf_dataabt_fixup) (void *arg); 160 int (*cf_prefetchabt_fixup) (void *arg); 161 162 void (*cf_context_switch) (void); 163 164 void (*cf_setup) (char *string); 165 }; 166 167 extern struct cpu_functions cpufuncs; 168 extern u_int cputype; 169 170 #define cpu_id() cpufuncs.cf_id() 171 #define cpu_cpwait() cpufuncs.cf_cpwait() 172 173 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 174 #define cpu_domains(d) cpufuncs.cf_domains(d) 175 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 176 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 177 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 178 179 #ifndef SMP 180 181 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 182 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 183 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 184 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 185 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 186 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 187 188 #else 189 void tlb_broadcast(int); 190 191 #ifdef CPU_CORTEXA 192 #define TLB_BROADCAST /* No need to explicitely send an IPI */ 193 #else 194 #define TLB_BROADCAST tlb_broadcast(7) 195 #endif 196 197 #define cpu_tlb_flushID() do { \ 198 cpufuncs.cf_tlb_flushID(); \ 199 TLB_BROADCAST; \ 200 } while(0) 201 202 #define cpu_tlb_flushID_SE(e) do { \ 203 cpufuncs.cf_tlb_flushID_SE(e); \ 204 TLB_BROADCAST; \ 205 } while(0) 206 207 208 #define cpu_tlb_flushI() do { \ 209 cpufuncs.cf_tlb_flushI(); \ 210 TLB_BROADCAST; \ 211 } while(0) 212 213 214 #define cpu_tlb_flushI_SE(e) do { \ 215 cpufuncs.cf_tlb_flushI_SE(e); \ 216 TLB_BROADCAST; \ 217 } while(0) 218 219 220 #define cpu_tlb_flushD() do { \ 221 cpufuncs.cf_tlb_flushD(); \ 222 TLB_BROADCAST; \ 223 } while(0) 224 225 226 #define cpu_tlb_flushD_SE(e) do { \ 227 cpufuncs.cf_tlb_flushD_SE(e); \ 228 TLB_BROADCAST; \ 229 } while(0) 230 231 #endif 232 233 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 234 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 235 236 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 237 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 238 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 239 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 240 241 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 242 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 243 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 244 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 245 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 246 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 247 248 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 249 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 250 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 251 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 252 253 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 254 255 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 256 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 257 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 258 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 259 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 260 261 #define cpu_setup(a) cpufuncs.cf_setup(a) 262 263 int set_cpufuncs (void); 264 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 265 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 266 267 void cpufunc_nullop (void); 268 int cpufunc_null_fixup (void *); 269 int early_abort_fixup (void *); 270 int late_abort_fixup (void *); 271 u_int cpufunc_id (void); 272 u_int cpufunc_cpuid (void); 273 u_int cpufunc_control (u_int clear, u_int bic); 274 void cpufunc_domains (u_int domains); 275 u_int cpufunc_faultstatus (void); 276 u_int cpufunc_faultaddress (void); 277 u_int cpu_pfr (int); 278 279 #ifdef CPU_ARM3 280 u_int arm3_control (u_int clear, u_int bic); 281 void arm3_cache_flush (void); 282 #endif /* CPU_ARM3 */ 283 284 #if defined(CPU_ARM6) || defined(CPU_ARM7) 285 void arm67_setttb (u_int ttb); 286 void arm67_tlb_flush (void); 287 void arm67_tlb_purge (u_int va); 288 void arm67_cache_flush (void); 289 void arm67_context_switch (void); 290 #endif /* CPU_ARM6 || CPU_ARM7 */ 291 292 #ifdef CPU_ARM6 293 void arm6_setup (char *string); 294 #endif /* CPU_ARM6 */ 295 296 #ifdef CPU_ARM7 297 void arm7_setup (char *string); 298 #endif /* CPU_ARM7 */ 299 300 #ifdef CPU_ARM7TDMI 301 int arm7_dataabt_fixup (void *arg); 302 void arm7tdmi_setup (char *string); 303 void arm7tdmi_setttb (u_int ttb); 304 void arm7tdmi_tlb_flushID (void); 305 void arm7tdmi_tlb_flushID_SE (u_int va); 306 void arm7tdmi_cache_flushID (void); 307 void arm7tdmi_context_switch (void); 308 #endif /* CPU_ARM7TDMI */ 309 310 #ifdef CPU_ARM8 311 void arm8_setttb (u_int ttb); 312 void arm8_tlb_flushID (void); 313 void arm8_tlb_flushID_SE (u_int va); 314 void arm8_cache_flushID (void); 315 void arm8_cache_flushID_E (u_int entry); 316 void arm8_cache_cleanID (void); 317 void arm8_cache_cleanID_E (u_int entry); 318 void arm8_cache_purgeID (void); 319 void arm8_cache_purgeID_E (u_int entry); 320 321 void arm8_cache_syncI (void); 322 void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 323 void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 324 void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 325 void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 326 void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 327 328 void arm8_context_switch (void); 329 330 void arm8_setup (char *string); 331 332 u_int arm8_clock_config (u_int, u_int); 333 #endif 334 335 336 #if defined(CPU_FA526) || defined(CPU_FA626TE) 337 void fa526_setup (char *arg); 338 void fa526_setttb (u_int ttb); 339 void fa526_context_switch (void); 340 void fa526_cpu_sleep (int); 341 void fa526_tlb_flushI_SE (u_int); 342 void fa526_tlb_flushID_SE (u_int); 343 void fa526_flush_prefetchbuf (void); 344 void fa526_flush_brnchtgt_E (u_int); 345 346 void fa526_icache_sync_all (void); 347 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 348 void fa526_dcache_wbinv_all (void); 349 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 350 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 351 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 352 void fa526_idcache_wbinv_all(void); 353 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 354 #endif 355 356 357 #ifdef CPU_SA110 358 void sa110_setup (char *string); 359 void sa110_context_switch (void); 360 #endif /* CPU_SA110 */ 361 362 #if defined(CPU_SA1100) || defined(CPU_SA1110) 363 void sa11x0_drain_readbuf (void); 364 365 void sa11x0_context_switch (void); 366 void sa11x0_cpu_sleep (int mode); 367 368 void sa11x0_setup (char *string); 369 #endif 370 371 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 372 void sa1_setttb (u_int ttb); 373 374 void sa1_tlb_flushID_SE (u_int va); 375 376 void sa1_cache_flushID (void); 377 void sa1_cache_flushI (void); 378 void sa1_cache_flushD (void); 379 void sa1_cache_flushD_SE (u_int entry); 380 381 void sa1_cache_cleanID (void); 382 void sa1_cache_cleanD (void); 383 void sa1_cache_cleanD_E (u_int entry); 384 385 void sa1_cache_purgeID (void); 386 void sa1_cache_purgeID_E (u_int entry); 387 void sa1_cache_purgeD (void); 388 void sa1_cache_purgeD_E (u_int entry); 389 390 void sa1_cache_syncI (void); 391 void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 392 void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 393 void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 394 void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 395 void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 396 397 #endif 398 399 #ifdef CPU_ARM9 400 void arm9_setttb (u_int); 401 402 void arm9_tlb_flushID_SE (u_int va); 403 404 void arm9_icache_sync_all (void); 405 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 406 407 void arm9_dcache_wbinv_all (void); 408 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 409 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 410 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 411 412 void arm9_idcache_wbinv_all (void); 413 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 414 415 void arm9_context_switch (void); 416 417 void arm9_setup (char *string); 418 419 extern unsigned arm9_dcache_sets_max; 420 extern unsigned arm9_dcache_sets_inc; 421 extern unsigned arm9_dcache_index_max; 422 extern unsigned arm9_dcache_index_inc; 423 #endif 424 425 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 426 void arm10_setttb (u_int); 427 428 void arm10_tlb_flushID_SE (u_int); 429 void arm10_tlb_flushI_SE (u_int); 430 431 void arm10_icache_sync_all (void); 432 void arm10_icache_sync_range (vm_offset_t, vm_size_t); 433 434 void arm10_dcache_wbinv_all (void); 435 void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 436 void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 437 void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 438 439 void arm10_idcache_wbinv_all (void); 440 void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 441 442 void arm10_context_switch (void); 443 444 void arm10_setup (char *string); 445 446 extern unsigned arm10_dcache_sets_max; 447 extern unsigned arm10_dcache_sets_inc; 448 extern unsigned arm10_dcache_index_max; 449 extern unsigned arm10_dcache_index_inc; 450 451 u_int sheeva_control_ext (u_int, u_int); 452 void sheeva_cpu_sleep (int); 453 void sheeva_setttb (u_int); 454 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 455 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 456 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 457 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 458 459 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 460 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 461 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 462 void sheeva_l2cache_wbinv_all (void); 463 #endif 464 465 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ 466 defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) 467 void arm11_setttb (u_int); 468 void arm11_sleep (int); 469 470 void arm11_tlb_flushID_SE (u_int); 471 void arm11_tlb_flushI_SE (u_int); 472 473 void arm11_context_switch (void); 474 475 void arm11_setup (char *string); 476 void arm11_tlb_flushID (void); 477 void arm11_tlb_flushI (void); 478 void arm11_tlb_flushD (void); 479 void arm11_tlb_flushD_SE (u_int va); 480 481 void arm11_drain_writebuf (void); 482 483 void pj4b_setttb (u_int); 484 485 void pj4b_icache_sync_range (vm_offset_t, vm_size_t); 486 487 void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t); 488 void pj4b_dcache_inv_range (vm_offset_t, vm_size_t); 489 void pj4b_dcache_wb_range (vm_offset_t, vm_size_t); 490 491 void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t); 492 493 void pj4b_drain_readbuf (void); 494 void pj4b_flush_brnchtgt_all (void); 495 void pj4b_flush_brnchtgt_va (u_int); 496 void pj4b_sleep (int); 497 498 void armv6_icache_sync_all (void); 499 void armv6_icache_sync_range (vm_offset_t, vm_size_t); 500 501 void armv6_dcache_wbinv_all (void); 502 void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 503 void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 504 void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 505 506 void armv6_idcache_wbinv_all (void); 507 void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 508 509 void armv7_setttb (u_int); 510 void armv7_tlb_flushID (void); 511 void armv7_tlb_flushID_SE (u_int); 512 void armv7_icache_sync_range (vm_offset_t, vm_size_t); 513 void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 514 void armv7_dcache_wbinv_all (void); 515 void armv7_idcache_wbinv_all (void); 516 void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 517 void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 518 void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 519 void armv7_cpu_sleep (int); 520 void armv7_setup (char *string); 521 void armv7_context_switch (void); 522 void armv7_drain_writebuf (void); 523 void armv7_sev (void); 524 u_int armv7_auxctrl (u_int, u_int); 525 void pj4bv7_setup (char *string); 526 void pj4bv6_setup (char *string); 527 void pj4b_config (void); 528 529 int get_core_id (void); 530 531 void armadaxp_idcache_wbinv_all (void); 532 533 void cortexa_setup (char *); 534 #endif 535 536 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) 537 void arm11x6_setttb (u_int); 538 void arm11x6_idcache_wbinv_all (void); 539 void arm11x6_dcache_wbinv_all (void); 540 void arm11x6_icache_sync_all (void); 541 void arm11x6_flush_prefetchbuf (void); 542 void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 543 void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 544 void arm11x6_setup (char *string); 545 void arm11x6_sleep (int); /* no ref. for errata */ 546 #endif 547 #if defined(CPU_ARM1136) 548 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 549 #endif 550 551 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 552 void armv5_ec_setttb(u_int); 553 554 void armv5_ec_icache_sync_all(void); 555 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 556 557 void armv5_ec_dcache_wbinv_all(void); 558 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 559 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 560 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 561 562 void armv5_ec_idcache_wbinv_all(void); 563 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 564 #endif 565 566 #if defined (CPU_ARM10) 567 void armv5_setttb(u_int); 568 569 void armv5_icache_sync_all(void); 570 void armv5_icache_sync_range(vm_offset_t, vm_size_t); 571 572 void armv5_dcache_wbinv_all(void); 573 void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 574 void armv5_dcache_inv_range(vm_offset_t, vm_size_t); 575 void armv5_dcache_wb_range(vm_offset_t, vm_size_t); 576 577 void armv5_idcache_wbinv_all(void); 578 void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 579 580 extern unsigned armv5_dcache_sets_max; 581 extern unsigned armv5_dcache_sets_inc; 582 extern unsigned armv5_dcache_index_max; 583 extern unsigned armv5_dcache_index_inc; 584 #endif 585 586 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 587 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 588 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 589 defined(CPU_FA526) || defined(CPU_FA626TE) || \ 590 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 591 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 592 593 void armv4_tlb_flushID (void); 594 void armv4_tlb_flushI (void); 595 void armv4_tlb_flushD (void); 596 void armv4_tlb_flushD_SE (u_int va); 597 598 void armv4_drain_writebuf (void); 599 #endif 600 601 #if defined(CPU_IXP12X0) 602 void ixp12x0_drain_readbuf (void); 603 void ixp12x0_context_switch (void); 604 void ixp12x0_setup (char *string); 605 #endif 606 607 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 608 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 609 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 610 void xscale_cpwait (void); 611 612 void xscale_cpu_sleep (int mode); 613 614 u_int xscale_control (u_int clear, u_int bic); 615 616 void xscale_setttb (u_int ttb); 617 618 void xscale_tlb_flushID_SE (u_int va); 619 620 void xscale_cache_flushID (void); 621 void xscale_cache_flushI (void); 622 void xscale_cache_flushD (void); 623 void xscale_cache_flushD_SE (u_int entry); 624 625 void xscale_cache_cleanID (void); 626 void xscale_cache_cleanD (void); 627 void xscale_cache_cleanD_E (u_int entry); 628 629 void xscale_cache_clean_minidata (void); 630 631 void xscale_cache_purgeID (void); 632 void xscale_cache_purgeID_E (u_int entry); 633 void xscale_cache_purgeD (void); 634 void xscale_cache_purgeD_E (u_int entry); 635 636 void xscale_cache_syncI (void); 637 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 638 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 639 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 640 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 641 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 642 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 643 644 void xscale_context_switch (void); 645 646 void xscale_setup (char *string); 647 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 648 CPU_XSCALE_80219 */ 649 650 #ifdef CPU_XSCALE_81342 651 652 void xscalec3_l2cache_purge (void); 653 void xscalec3_cache_purgeID (void); 654 void xscalec3_cache_purgeD (void); 655 void xscalec3_cache_cleanID (void); 656 void xscalec3_cache_cleanD (void); 657 void xscalec3_cache_syncI (void); 658 659 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 660 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 661 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 662 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 663 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 664 665 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 666 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 667 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 668 669 670 void xscalec3_setttb (u_int ttb); 671 void xscalec3_context_switch (void); 672 673 #endif /* CPU_XSCALE_81342 */ 674 675 #define tlb_flush cpu_tlb_flushID 676 #define setttb cpu_setttb 677 #define drain_writebuf cpu_drain_writebuf 678 679 /* 680 * Macros for manipulating CPU interrupts 681 */ 682 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 683 684 static __inline u_int32_t 685 __set_cpsr_c(u_int bic, u_int eor) 686 { 687 u_int32_t tmp, ret; 688 689 __asm __volatile( 690 "mrs %0, cpsr\n" /* Get the CPSR */ 691 "bic %1, %0, %2\n" /* Clear bits */ 692 "eor %1, %1, %3\n" /* XOR bits */ 693 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 694 : "=&r" (ret), "=&r" (tmp) 695 : "r" (bic), "r" (eor) : "memory"); 696 697 return ret; 698 } 699 700 #define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ 701 #define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ 702 703 #define disable_interrupts(mask) \ 704 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ 705 (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 706 707 #define enable_interrupts(mask) \ 708 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) 709 710 #define restore_interrupts(old_cpsr) \ 711 (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ 712 (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 713 714 static __inline register_t 715 intr_disable(void) 716 { 717 register_t s; 718 719 s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); 720 return (s); 721 } 722 723 static __inline void 724 intr_restore(register_t s) 725 { 726 727 restore_interrupts(s); 728 } 729 730 /* Functions to manipulate the CPSR. */ 731 u_int SetCPSR(u_int bic, u_int eor); 732 u_int GetCPSR(void); 733 734 /* 735 * Functions to manipulate cpu r13 736 * (in arm/arm32/setstack.S) 737 */ 738 739 void set_stackptr (u_int mode, u_int address); 740 u_int get_stackptr (u_int mode); 741 742 /* 743 * Miscellany 744 */ 745 746 int get_pc_str_offset (void); 747 748 /* 749 * CPU functions from locore.S 750 */ 751 752 void cpu_reset (void) __attribute__((__noreturn__)); 753 754 /* 755 * Cache info variables. 756 */ 757 758 /* PRIMARY CACHE VARIABLES */ 759 extern int arm_picache_size; 760 extern int arm_picache_line_size; 761 extern int arm_picache_ways; 762 763 extern int arm_pdcache_size; /* and unified */ 764 extern int arm_pdcache_line_size; 765 extern int arm_pdcache_ways; 766 767 extern int arm_pcache_type; 768 extern int arm_pcache_unified; 769 770 extern int arm_dcache_align; 771 extern int arm_dcache_align_mask; 772 773 extern u_int arm_cache_level; 774 extern u_int arm_cache_loc; 775 extern u_int arm_cache_type[14]; 776 777 #endif /* _KERNEL */ 778 #endif /* _MACHINE_CPUFUNC_H_ */ 779 780 /* End of cpufunc.h */ 781