1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/extres/clk/clk_fixed.h> 48 #include <dev/extres/clk/clk_gate.h> 49 #include <dev/extres/syscon/syscon.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <arm/mv/mv_cp110_clock.h> 55 56 #include "clkdev_if.h" 57 #include "syscon_if.h" 58 59 /* Clocks */ 60 static struct clk_fixed_def cp110_clk_pll_0 = { 61 .clkdef.id = CP110_PLL_0, 62 .freq = 1000000000, 63 }; 64 65 static const char *clk_parents_0[] = {"cp110-pll0-0"}; 66 static const char *clk_parents_1[] = {"cp110-pll0-1"}; 67 68 static struct clk_fixed_def cp110_clk_ppv2_core = { 69 .clkdef.id = CP110_PPV2_CORE, 70 .clkdef.parent_cnt = 1, 71 .mult = 1, 72 .div = 3, 73 }; 74 75 static struct clk_fixed_def cp110_clk_x2core = { 76 .clkdef.id = CP110_X2CORE, 77 .clkdef.parent_cnt = 1, 78 .mult = 1, 79 .div = 2, 80 }; 81 82 static const char *core_parents_0[] = {"cp110-x2core-0"}; 83 static const char *core_parents_1[] = {"cp110-x2core-1"}; 84 85 static struct clk_fixed_def cp110_clk_core = { 86 .clkdef.id = CP110_CORE, 87 .clkdef.parent_cnt = 1, 88 .mult = 1, 89 .div = 2, 90 }; 91 92 static struct clk_fixed_def cp110_clk_sdio = { 93 .clkdef.id = CP110_SDIO, 94 .clkdef.parent_cnt = 1, 95 .mult = 2, 96 .div = 5, 97 }; 98 99 /* Gates */ 100 101 static struct cp110_gate cp110_gates[] = { 102 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0) 103 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1) 104 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */ 105 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3) 106 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4) 107 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5) 108 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6) 109 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7) 110 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8) 111 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9) 112 CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11) 113 CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12) 114 CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13) 115 CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14) 116 CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15) 117 CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16) 118 CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17) 119 CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18) 120 CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21) 121 CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22) 122 CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23) 123 CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24) 124 CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25) 125 CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26) 126 }; 127 128 struct mv_cp110_clock_softc { 129 device_t dev; 130 struct syscon *syscon; 131 struct mtx mtx; 132 }; 133 134 135 static struct ofw_compat_data compat_data[] = { 136 {"marvell,cp110-clock", 1}, 137 {NULL, 0} 138 }; 139 140 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) 141 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) 142 143 static char * 144 mv_cp110_clock_name(device_t dev, const char *name) 145 { 146 char *clkname = NULL; 147 int unit; 148 149 unit = device_get_unit(dev); 150 if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0) 151 panic("Cannot generate unique clock name for %s\n", name); 152 return (clkname); 153 } 154 155 static int 156 mv_cp110_clock_probe(device_t dev) 157 { 158 159 if (!ofw_bus_status_okay(dev)) 160 return (ENXIO); 161 162 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 163 return (ENXIO); 164 165 device_set_desc(dev, "Marvell CP110 Clock Controller"); 166 return (BUS_PROBE_DEFAULT); 167 } 168 169 static int 170 cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells, 171 phandle_t *cells, struct clknode **clk) 172 { 173 int id = 0; 174 175 if (ncells != 2) 176 return (ENXIO); 177 178 id = cells[1]; 179 if (cells[0] == 1) 180 id += CP110_MAX_CLOCK; 181 182 *clk = clknode_find_by_id(clkdom, id); 183 184 return (0); 185 } 186 187 static int 188 mv_cp110_clock_attach(device_t dev) 189 { 190 struct mv_cp110_clock_softc *sc; 191 struct clkdom *clkdom; 192 struct clk_gate_def def; 193 char *pll0_name; 194 int unit, i; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 199 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || 200 sc->syscon == NULL) { 201 device_printf(dev, "cannot get syscon for device\n"); 202 return (ENXIO); 203 } 204 205 unit = device_get_unit(dev); 206 if (unit > 1) { 207 device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit); 208 return (ENXIO); 209 } 210 211 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 212 213 clkdom = clkdom_create(dev); 214 clkdom_set_ofw_mapper(clkdom, cp110_ofw_map); 215 216 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0"); 217 cp110_clk_pll_0.clkdef.name = pll0_name; 218 clknode_fixed_register(clkdom, &cp110_clk_pll_0); 219 220 cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2"); 221 cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 222 clknode_fixed_register(clkdom, &cp110_clk_ppv2_core); 223 224 cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core"); 225 cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 226 clknode_fixed_register(clkdom, &cp110_clk_x2core); 227 228 cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core"); 229 cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1; 230 clknode_fixed_register(clkdom, &cp110_clk_core); 231 232 /* NAND missing */ 233 234 cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio"); 235 cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 236 clknode_fixed_register(clkdom, &cp110_clk_sdio); 237 238 for (i = 0; i < nitems(cp110_gates); i++) { 239 if (cp110_gates[i].name == NULL) 240 continue; 241 242 memset(&def, 0, sizeof(def)); 243 def.clkdef.id = CP110_MAX_CLOCK + i; 244 def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name); 245 def.clkdef.parent_cnt = 1; 246 def.offset = CP110_CLOCK_GATING_OFFSET; 247 def.shift = cp110_gates[i].shift; 248 def.mask = 1; 249 def.on_value = 1; 250 def.off_value = 0; 251 252 switch (i) { 253 case CP110_GATE_MG: 254 case CP110_GATE_GOP_DP: 255 case CP110_GATE_PPV2: 256 def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name; 257 break; 258 case CP110_GATE_SDIO: 259 def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name; 260 break; 261 case CP110_GATE_MAIN: 262 case CP110_GATE_PCIE_XOR: 263 case CP110_GATE_PCIE_X4: 264 case CP110_GATE_EIP150: 265 case CP110_GATE_EIP197: 266 def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name; 267 break; 268 default: 269 def.clkdef.parent_names = &cp110_clk_core.clkdef.name; 270 break; 271 } 272 273 clknode_gate_register(clkdom, &def); 274 } 275 276 clkdom_finit(clkdom); 277 278 if (bootverbose) 279 clkdom_dump(clkdom); 280 281 return (0); 282 } 283 284 static int 285 mv_cp110_clock_detach(device_t dev) 286 { 287 288 return (EBUSY); 289 } 290 291 static int 292 mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val) 293 { 294 struct mv_cp110_clock_softc *sc; 295 296 sc = device_get_softc(dev); 297 WR4(sc, addr, val); 298 return (0); 299 } 300 301 static int 302 mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 303 { 304 struct mv_cp110_clock_softc *sc; 305 306 sc = device_get_softc(dev); 307 308 *val = RD4(sc, addr); 309 return (0); 310 } 311 312 static int 313 mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) 314 { 315 struct mv_cp110_clock_softc *sc; 316 uint32_t reg; 317 318 sc = device_get_softc(dev); 319 320 reg = RD4(sc, addr); 321 reg &= ~clr; 322 reg |= set; 323 WR4(sc, addr, reg); 324 325 return (0); 326 } 327 328 static void 329 mv_cp110_clock_device_lock(device_t dev) 330 { 331 struct mv_cp110_clock_softc *sc; 332 333 sc = device_get_softc(dev); 334 mtx_lock(&sc->mtx); 335 } 336 337 static void 338 mv_cp110_clock_device_unlock(device_t dev) 339 { 340 struct mv_cp110_clock_softc *sc; 341 342 sc = device_get_softc(dev); 343 mtx_unlock(&sc->mtx); 344 } 345 346 static device_method_t mv_cp110_clock_methods[] = { 347 /* Device interface */ 348 DEVMETHOD(device_probe, mv_cp110_clock_probe), 349 DEVMETHOD(device_attach, mv_cp110_clock_attach), 350 DEVMETHOD(device_detach, mv_cp110_clock_detach), 351 352 /* clkdev interface */ 353 DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4), 354 DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4), 355 DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4), 356 DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock), 357 DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock), 358 359 DEVMETHOD_END 360 }; 361 362 static devclass_t mv_cp110_clock_devclass; 363 364 static driver_t mv_cp110_clock_driver = { 365 "mv_cp110_clock", 366 mv_cp110_clock_methods, 367 sizeof(struct mv_cp110_clock_softc), 368 }; 369 370 EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver, 371 mv_cp110_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 372