1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/kobj.h>
33 #include <sys/module.h>
34 #include <sys/malloc.h>
35 #include <sys/rman.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41
42 #include <dev/clk/clk_div.h>
43 #include <dev/clk/clk_fixed.h>
44 #include <dev/clk/clk_gate.h>
45 #include <dev/clk/clk_mux.h>
46 #include <dev/hwreset/hwreset.h>
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50
51 #include <dt-bindings/clock/tegra210-car.h>
52
53 #include "clkdev_if.h"
54 #include "hwreset_if.h"
55 #include "tegra210_car.h"
56
57 static struct ofw_compat_data compat_data[] = {
58 {"nvidia,tegra210-car", 1},
59 {NULL, 0},
60 };
61
62 #define PLIST(x) static const char *x[]
63
64 /* Pure multiplexer. */
65 #define MUX(_id, cname, plists, o, s, w) \
66 { \
67 .clkdef.id = _id, \
68 .clkdef.name = cname, \
69 .clkdef.parent_names = plists, \
70 .clkdef.parent_cnt = nitems(plists), \
71 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
72 .offset = o, \
73 .shift = s, \
74 .width = w, \
75 }
76
77 /* Fractional divider (7.1). */
78 #define DIV7_1(_id, cname, plist, o, s) \
79 { \
80 .clkdef.id = _id, \
81 .clkdef.name = cname, \
82 .clkdef.parent_names = (const char *[]){plist}, \
83 .clkdef.parent_cnt = 1, \
84 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
85 .offset = o, \
86 .i_shift = (s) + 1, \
87 .i_width = 7, \
88 .f_shift = s, \
89 .f_width = 1, \
90 }
91
92 /* Integer divider. */
93 #define DIV(_id, cname, plist, o, s, w, f) \
94 { \
95 .clkdef.id = _id, \
96 .clkdef.name = cname, \
97 .clkdef.parent_names = (const char *[]){plist}, \
98 .clkdef.parent_cnt = 1, \
99 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
100 .offset = o, \
101 .i_shift = s, \
102 .i_width = w, \
103 .div_flags = f, \
104 }
105
106 /* Gate in PLL block. */
107 #define GATE_PLL(_id, cname, plist, o, s) \
108 { \
109 .clkdef.id = _id, \
110 .clkdef.name = cname, \
111 .clkdef.parent_names = (const char *[]){plist}, \
112 .clkdef.parent_cnt = 1, \
113 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
114 .offset = o, \
115 .shift = s, \
116 .mask = 3, \
117 .on_value = 3, \
118 .off_value = 0, \
119 }
120
121 /* Standard gate. */
122 #define GATE(_id, cname, plist, o, s) \
123 { \
124 .clkdef.id = _id, \
125 .clkdef.name = cname, \
126 .clkdef.parent_names = (const char *[]){plist}, \
127 .clkdef.parent_cnt = 1, \
128 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
129 .offset = o, \
130 .shift = s, \
131 .mask = 1, \
132 .on_value = 1, \
133 .off_value = 0, \
134 }
135
136 /* Inverted gate. */
137 #define GATE_INV(_id, cname, plist, o, s) \
138 { \
139 .clkdef.id = _id, \
140 .clkdef.name = cname, \
141 .clkdef.parent_names = (const char *[]){plist}, \
142 .clkdef.parent_cnt = 1, \
143 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
144 .offset = o, \
145 .shift = s, \
146 .mask = 1, \
147 .on_value = 0, \
148 .off_value = 1, \
149 }
150
151 /* Fixed rate clock. */
152 #define FRATE(_id, cname, _freq) \
153 { \
154 .clkdef.id = _id, \
155 .clkdef.name = cname, \
156 .clkdef.parent_names = NULL, \
157 .clkdef.parent_cnt = 0, \
158 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
159 .freq = _freq, \
160 }
161
162 /* Fixed rate multipier/divider. */
163 #define FACT(_id, cname, pname, _mult, _div) \
164 { \
165 .clkdef.id = _id, \
166 .clkdef.name = cname, \
167 .clkdef.parent_names = (const char *[]){pname}, \
168 .clkdef.parent_cnt = 1, \
169 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
170 .mult = _mult, \
171 .div = _div, \
172 }
173
174 static uint32_t osc_freqs[16] = {
175 [0] = 13000000,
176 [1] = 16800000,
177 [4] = 19200000,
178 [5] = 38400000,
179 [8] = 12000000,
180 [9] = 48000000,
181 };
182
183
184 /* Parent lists. */
185 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60", "pc_xusb_ss" };
186 PLIST(mux_xusb_ssp) = {"xusb_ss", "osc_div_clk"};
187
188
189 /* Clocks adjusted online. */
190 static struct clk_fixed_def fixed_osc =
191 FRATE(TEGRA210_CLK_CLK_M, "osc", 38400000);
192 static struct clk_fixed_def fixed_clk_m =
193 FACT(0, "clk_m", "osc", 1, 1);
194 static struct clk_fixed_def fixed_osc_div =
195 FACT(0, "osc_div_clk", "osc", 1, 1);
196
197 static struct clk_fixed_def tegra210_fixed_clks[] = {
198 /* Core clocks. */
199 FRATE(0, "bogus", 1),
200 FRATE(0, "clk_s", 32768),
201
202 /* Audio clocks. */
203 FRATE(0, "vimclk_sync", 1),
204 FRATE(0, "i2s1_sync", 1),
205 FRATE(0, "i2s2_sync", 1),
206 FRATE(0, "i2s3_sync", 1),
207 FRATE(0, "i2s4_sync", 1),
208 FRATE(0, "i2s5_sync", 1),
209 FRATE(0, "spdif_in_sync", 1),
210
211 /* XUSB */
212 FACT(TEGRA210_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2),
213
214 /* SOR */
215 FACT(0, "sor_safe_div", "pllP_out0", 1, 17),
216 FACT(0, "dpaux_div", "sor_safe", 1, 17),
217 FACT(0, "dpaux1_div", "sor_safe", 1, 17),
218
219 /* Not Yet Implemented */
220 FRATE(0, "audio", 10000000),
221 FRATE(0, "audio0", 10000000),
222 FRATE(0, "audio1", 10000000),
223 FRATE(0, "audio2", 10000000),
224 FRATE(0, "audio3", 10000000),
225 FRATE(0, "audio4", 10000000),
226 FRATE(0, "ext_vimclk", 10000000),
227 FRATE(0, "audiod1", 10000000),
228 FRATE(0, "audiod2", 10000000),
229 FRATE(0, "audiod3", 10000000),
230 FRATE(0, "dfllCPU_out", 10000000),
231
232 };
233
234
235 static struct clk_mux_def tegra210_mux_clks[] = {
236 /* USB. */
237 MUX(TEGRA210_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 2),
238 MUX(0, "xusb_ssp", mux_xusb_ssp, CLK_SOURCE_XUSB_SS, 24, 1),
239
240 };
241
242
243 static struct clk_gate_def tegra210_gate_clks[] = {
244 /* Base peripheral clocks. */
245 GATE_INV(TEGRA210_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
246 GATE_INV(TEGRA210_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
247 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
248 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
249 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21),
250 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29),
251 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
252 };
253
254 static struct clk_div_def tegra210_div_clks[] = {
255 /* Base peripheral clocks. */
256 DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
257 DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),
258 };
259
260 /* Initial setup table. */
261 static struct tegra210_init_item clk_init_table[] = {
262 /* clock, partent, frequency, enable */
263 {"uarta", "pllP_out0", 408000000, 0},
264 {"uartb", "pllP_out0", 408000000, 0},
265 {"uartc", "pllP_out0", 408000000, 0},
266 {"uartd", "pllP_out0", 408000000, 0},
267 {"pllA", NULL, 564480000, 1},
268 {"pllA_out0", NULL, 11289600, 1},
269 {"extperiph1", "pllA_out0", 0, 1},
270 {"i2s1", "pllA_out0", 11289600, 0},
271 {"i2s2", "pllA_out0", 11289600, 0},
272 {"i2s3", "pllA_out0", 11289600, 0},
273 {"i2s4", "pllA_out0", 11289600, 0},
274 {"i2s5", "pllA_out0", 11289600, 0},
275 {"host1x", "pllP_out0", 136000000, 1},
276 {"sclk", "pllP_out2", 102000000, 1},
277 {"dvfs_soc", "pllP_out0", 51000000, 1},
278 {"dvfs_ref", "pllP_out0", 51000000, 1},
279 {"spi4", "pllP_out0", 12000000, 1},
280 {"pllREFE", NULL, 672000000, 0},
281
282 {"xusb", NULL, 0, 1},
283 {"xusb_ss", "pllU_480", 120000000, 0},
284 {"pc_xusb_fs", "pllU_48", 48000000, 0},
285 {"xusb_hs", "pc_xusb_ss", 120000000, 0},
286 {"xusb_ssp", "xusb_ss", 120000000, 0},
287 {"pc_xusb_falcon", "pllP_xusb", 204000000, 0},
288 {"pc_xusb_core_host", "pllP_xusb", 102000000, 0},
289 {"pc_xusb_core_dev", "pllP_xusb", 102000000, 0},
290
291 {"sata", "pllP_out0", 104000000, 0},
292 {"sata_oob", "pllP_out0", 204000000, 0},
293 {"emc", NULL, 0, 1},
294 {"mselect", NULL, 0, 1},
295 {"csite", NULL, 0, 1},
296
297 {"dbgapb", NULL, 0, 1 },
298 {"tsensor", "clk_m", 400000, 0},
299 {"i2c1", "pllP_out0", 0, 0},
300 {"i2c2", "pllP_out0", 0, 0},
301 {"i2c3", "pllP_out0", 0, 0},
302 {"i2c4", "pllP_out0", 0, 0},
303 {"i2c5", "pllP_out0", 0, 0},
304 {"i2c6", "pllP_out0", 0, 0},
305
306 {"pllDP_out0", NULL, 270000000, 0},
307 {"soc_therm", "pllP_out0", 51000000, 0},
308 {"cclk_g", NULL, 0, 1},
309 {"pllU_out1", NULL, 48000000, 1},
310 {"pllU_out2", NULL, 60000000, 1},
311 {"pllC4", NULL, 1000000000, 1},
312 {"pllC4_out0", NULL, 1000000000, 1},
313 };
314
315 static void
init_divs(struct tegra210_car_softc * sc,struct clk_div_def * clks,int nclks)316 init_divs(struct tegra210_car_softc *sc, struct clk_div_def *clks, int nclks)
317 {
318 int i, rv;
319
320 for (i = 0; i < nclks; i++) {
321 rv = clknode_div_register(sc->clkdom, clks + i);
322 if (rv != 0)
323 panic("clk_div_register failed");
324 }
325 }
326
327 static void
init_gates(struct tegra210_car_softc * sc,struct clk_gate_def * clks,int nclks)328 init_gates(struct tegra210_car_softc *sc, struct clk_gate_def *clks, int nclks)
329 {
330 int i, rv;
331
332
333 for (i = 0; i < nclks; i++) {
334 rv = clknode_gate_register(sc->clkdom, clks + i);
335 if (rv != 0)
336 panic("clk_gate_register failed");
337 }
338 }
339
340 static void
init_muxes(struct tegra210_car_softc * sc,struct clk_mux_def * clks,int nclks)341 init_muxes(struct tegra210_car_softc *sc, struct clk_mux_def *clks, int nclks)
342 {
343 int i, rv;
344
345
346 for (i = 0; i < nclks; i++) {
347 rv = clknode_mux_register(sc->clkdom, clks + i);
348 if (rv != 0)
349 panic("clk_mux_register failed");
350 }
351 }
352
353 static void
init_fixeds(struct tegra210_car_softc * sc,struct clk_fixed_def * clks,int nclks)354 init_fixeds(struct tegra210_car_softc *sc, struct clk_fixed_def *clks,
355 int nclks)
356 {
357 int i, rv;
358 uint32_t val;
359 int osc_idx;
360
361 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val);
362 osc_idx = OSC_CTRL_OSC_FREQ_GET(val);
363 fixed_osc.freq = osc_freqs[osc_idx];
364 if (fixed_osc.freq == 0)
365 panic("Undefined input frequency");
366 rv = clknode_fixed_register(sc->clkdom, &fixed_osc);
367 if (rv != 0)
368 panic("clk_fixed_register failed");
369
370 fixed_osc_div.div = 1 << OSC_CTRL_PLL_REF_DIV_GET(val);
371 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div);
372 if (rv != 0)
373 panic("clk_fixed_register failed");
374
375 CLKDEV_READ_4(sc->dev, SPARE_REG0, &val);
376 fixed_clk_m.div = SPARE_REG0_MDIV_GET(val) + 1;
377 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m);
378 if (rv != 0)
379 panic("clk_fixed_register failed");
380
381 for (i = 0; i < nclks; i++) {
382 rv = clknode_fixed_register(sc->clkdom, clks + i);
383 if (rv != 0)
384 panic("clk_fixed_register failed");
385 }
386 }
387
388 static void
postinit_clock(struct tegra210_car_softc * sc)389 postinit_clock(struct tegra210_car_softc *sc)
390 {
391 int i;
392 struct tegra210_init_item *tbl;
393 struct clknode *clknode;
394 int rv;
395
396 for (i = 0; i < nitems(clk_init_table); i++) {
397 tbl = &clk_init_table[i];
398
399 clknode = clknode_find_by_name(tbl->name);
400 if (clknode == NULL) {
401 device_printf(sc->dev, "Cannot find clock %s\n",
402 tbl->name);
403 continue;
404 }
405 if (tbl->parent != NULL) {
406 rv = clknode_set_parent_by_name(clknode, tbl->parent);
407 if (rv != 0) {
408 device_printf(sc->dev,
409 "Cannot set parent for %s (to %s): %d\n",
410 tbl->name, tbl->parent, rv);
411 continue;
412 }
413 }
414 if (tbl->frequency != 0) {
415 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999);
416 if (rv != 0) {
417 device_printf(sc->dev,
418 "Cannot set frequency for %s: %d\n",
419 tbl->name, rv);
420 continue;
421 }
422 }
423 if (tbl->enable!= 0) {
424 rv = clknode_enable(clknode);
425 if (rv != 0) {
426 device_printf(sc->dev,
427 "Cannot enable %s: %d\n", tbl->name, rv);
428 continue;
429 }
430 }
431 }
432 }
433
434 static void
register_clocks(device_t dev)435 register_clocks(device_t dev)
436 {
437 struct tegra210_car_softc *sc;
438
439 sc = device_get_softc(dev);
440 sc->clkdom = clkdom_create(dev);
441 if (sc->clkdom == NULL)
442 panic("clkdom == NULL");
443
444 init_fixeds(sc, tegra210_fixed_clks, nitems(tegra210_fixed_clks));
445 tegra210_init_plls(sc);
446 init_muxes(sc, tegra210_mux_clks, nitems(tegra210_mux_clks));
447 init_divs(sc, tegra210_div_clks, nitems(tegra210_div_clks));
448 init_gates(sc, tegra210_gate_clks, nitems(tegra210_gate_clks));
449 tegra210_periph_clock(sc);
450 tegra210_super_mux_clock(sc);
451 clkdom_finit(sc->clkdom);
452 clkdom_xlock(sc->clkdom);
453 postinit_clock(sc);
454 clkdom_unlock(sc->clkdom);
455 if (bootverbose)
456 clkdom_dump(sc->clkdom);
457 }
458
459 static int
tegra210_car_clkdev_read_4(device_t dev,bus_addr_t addr,uint32_t * val)460 tegra210_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
461 {
462 struct tegra210_car_softc *sc;
463
464 sc = device_get_softc(dev);
465 *val = bus_read_4(sc->mem_res, addr);
466 return (0);
467 }
468
469 static int
tegra210_car_clkdev_write_4(device_t dev,bus_addr_t addr,uint32_t val)470 tegra210_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
471 {
472 struct tegra210_car_softc *sc;
473
474 sc = device_get_softc(dev);
475 bus_write_4(sc->mem_res, addr, val);
476 return (0);
477 }
478
479 static int
tegra210_car_clkdev_modify_4(device_t dev,bus_addr_t addr,uint32_t clear_mask,uint32_t set_mask)480 tegra210_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask,
481 uint32_t set_mask)
482 {
483 struct tegra210_car_softc *sc;
484 uint32_t reg;
485
486 sc = device_get_softc(dev);
487 reg = bus_read_4(sc->mem_res, addr);
488 reg &= ~clear_mask;
489 reg |= set_mask;
490 bus_write_4(sc->mem_res, addr, reg);
491 return (0);
492 }
493
494 static void
tegra210_car_clkdev_device_lock(device_t dev)495 tegra210_car_clkdev_device_lock(device_t dev)
496 {
497 struct tegra210_car_softc *sc;
498
499 sc = device_get_softc(dev);
500 mtx_lock(&sc->mtx);
501 }
502
503 static void
tegra210_car_clkdev_device_unlock(device_t dev)504 tegra210_car_clkdev_device_unlock(device_t dev)
505 {
506 struct tegra210_car_softc *sc;
507
508 sc = device_get_softc(dev);
509 mtx_unlock(&sc->mtx);
510 }
511
512 static int
tegra210_car_detach(device_t dev)513 tegra210_car_detach(device_t dev)
514 {
515
516 device_printf(dev, "Error: Clock driver cannot be detached\n");
517 return (EBUSY);
518 }
519
520 static int
tegra210_car_probe(device_t dev)521 tegra210_car_probe(device_t dev)
522 {
523
524 if (!ofw_bus_status_okay(dev))
525 return (ENXIO);
526
527 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
528 device_set_desc(dev, "Tegra Clock Driver");
529 return (BUS_PROBE_DEFAULT);
530 }
531
532 return (ENXIO);
533 }
534
535 static int
tegra210_car_attach(device_t dev)536 tegra210_car_attach(device_t dev)
537 {
538 struct tegra210_car_softc *sc = device_get_softc(dev);
539 int rid, rv;
540
541 sc->dev = dev;
542
543 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
544 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
545
546 /* Resource setup. */
547 rid = 0;
548 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
549 RF_ACTIVE);
550 if (!sc->mem_res) {
551 device_printf(dev, "cannot allocate memory resource\n");
552 rv = ENXIO;
553 goto fail;
554 }
555
556 register_clocks(dev);
557 hwreset_register_ofw_provider(dev);
558 return (0);
559
560 fail:
561 if (sc->mem_res)
562 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
563
564 return (rv);
565 }
566
567 static int
tegra210_car_hwreset_assert(device_t dev,intptr_t id,bool value)568 tegra210_car_hwreset_assert(device_t dev, intptr_t id, bool value)
569 {
570 struct tegra210_car_softc *sc = device_get_softc(dev);
571
572 return (tegra210_hwreset_by_idx(sc, id, value));
573 }
574
575 static device_method_t tegra210_car_methods[] = {
576 /* Device interface */
577 DEVMETHOD(device_probe, tegra210_car_probe),
578 DEVMETHOD(device_attach, tegra210_car_attach),
579 DEVMETHOD(device_detach, tegra210_car_detach),
580
581 /* Clkdev interface*/
582 DEVMETHOD(clkdev_read_4, tegra210_car_clkdev_read_4),
583 DEVMETHOD(clkdev_write_4, tegra210_car_clkdev_write_4),
584 DEVMETHOD(clkdev_modify_4, tegra210_car_clkdev_modify_4),
585 DEVMETHOD(clkdev_device_lock, tegra210_car_clkdev_device_lock),
586 DEVMETHOD(clkdev_device_unlock, tegra210_car_clkdev_device_unlock),
587
588 /* Reset interface */
589 DEVMETHOD(hwreset_assert, tegra210_car_hwreset_assert),
590
591 DEVMETHOD_END
592 };
593
594 static DEFINE_CLASS_0(car, tegra210_car_driver, tegra210_car_methods,
595 sizeof(struct tegra210_car_softc));
596 EARLY_DRIVER_MODULE(tegra210_car, simplebus, tegra210_car_driver, NULL, NULL,
597 BUS_PASS_TIMER);
598