1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
4//
5// Based on imx6qdl-sabresd.dtsi which is:
6// Copyright 2012 Freescale Semiconductor, Inc.
7// Copyright 2011 Linaro Ltd.
8
9#include <dt-bindings/clock/imx6qdl-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12
13/ {
14	chosen {
15		stdout-path = &uart4;
16	};
17
18	memory@10000000 {
19		device_type = "memory";
20		reg = <0x10000000 0x80000000>;
21	};
22
23	reg_usb_otg_vbus: regulator-usb-otg-vbus {
24		compatible = "regulator-fixed";
25		regulator-name = "usb_otg_vbus";
26		regulator-min-microvolt = <5000000>;
27		regulator-max-microvolt = <5000000>;
28	};
29
30	reg_usb_h1_vbus: regulator-usb-h1-vbus {
31		compatible = "regulator-fixed";
32		regulator-name = "usb_h1_vbus";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35	};
36
37	leds {
38		compatible = "gpio-leds";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_gpio_leds>;
41
42		led-0 {
43			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
44			default-state = "on";
45			linux,default-trigger = "heartbeat";
46		};
47	};
48};
49
50&ipu1_csi0_from_ipu1_csi0_mux {
51	bus-width = <8>;
52	data-shift = <12>; /* Lines 19:12 used */
53	hsync-active = <1>;
54	vsync-active = <1>;
55};
56
57&ipu1_csi0_mux_from_parallel_sensor {
58	remote-endpoint = <&ov2659_to_ipu1_csi0_mux>;
59};
60
61&ipu1_csi0 {
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_ipu1_csi0>;
64	status = "okay";
65};
66
67&ecspi1 {
68	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
69	pinctrl-names = "default";
70	pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>;
71	status = "okay";
72
73	m25p80: flash@0 {
74		#address-cells = <1>;
75		#size-cells = <1>;
76		compatible = "st,m25p80", "jedec,spi-nor";
77		spi-max-frequency = <20000000>;
78		reg = <0>;
79	};
80};
81
82&fec {
83	pinctrl-names = "default";
84	pinctrl-0 = <&pinctrl_enet>;
85	phy-mode = "rgmii-id";
86	phy-handle = <&phy>;
87	fsl,magic-packet;
88	status = "okay";
89
90	mdio {
91		#address-cells = <1>;
92		#size-cells = <0>;
93
94		phy: ethernet-phy@1 {
95			reg = <1>;
96			qca,clk-out-frequency = <125000000>;
97			reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
98			reset-assert-us = <10000>;
99		};
100	};
101};
102
103&hdmi {
104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_hdmi_cec>;
106	ddc-i2c-bus = <&i2c3>;
107	status = "okay";
108};
109
110&i2c2 {
111	clock-frequency = <100000>;
112	pinctrl-names = "default";
113	pinctrl-0 = <&pinctrl_i2c2>;
114	status = "okay";
115
116	pfuze100: pmic@8 {
117		compatible = "fsl,pfuze100";
118		reg = <0x08>;
119
120		regulators {
121			sw1a_reg: sw1ab {
122				regulator-min-microvolt = <300000>;
123				regulator-max-microvolt = <1875000>;
124				regulator-boot-on;
125				regulator-always-on;
126				regulator-ramp-delay = <6250>;
127			};
128
129			sw1c_reg: sw1c {
130				regulator-min-microvolt = <300000>;
131				regulator-max-microvolt = <1875000>;
132				regulator-boot-on;
133				regulator-always-on;
134				regulator-ramp-delay = <6250>;
135			};
136
137			sw2_reg: sw2 {
138				regulator-min-microvolt = <800000>;
139				regulator-max-microvolt = <3300000>;
140				regulator-boot-on;
141				regulator-always-on;
142				regulator-ramp-delay = <6250>;
143			};
144
145			sw3a_reg: sw3a {
146				regulator-min-microvolt = <400000>;
147				regulator-max-microvolt = <1975000>;
148				regulator-boot-on;
149				regulator-always-on;
150			};
151
152			sw3b_reg: sw3b {
153				regulator-min-microvolt = <400000>;
154				regulator-max-microvolt = <1975000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			sw4_reg: sw4 {
160				regulator-min-microvolt = <800000>;
161				regulator-max-microvolt = <3300000>;
162				regulator-always-on;
163			};
164
165			swbst_reg: swbst {
166				regulator-min-microvolt = <5000000>;
167				regulator-max-microvolt = <5150000>;
168			};
169
170			snvs_reg: vsnvs {
171				regulator-min-microvolt = <1000000>;
172				regulator-max-microvolt = <3000000>;
173				regulator-boot-on;
174				regulator-always-on;
175			};
176
177			vref_reg: vrefddr {
178				regulator-boot-on;
179				regulator-always-on;
180			};
181
182			vgen1_reg: vgen1 {
183				regulator-min-microvolt = <800000>;
184				regulator-max-microvolt = <1550000>;
185			};
186
187			vgen2_reg: vgen2 {
188				regulator-min-microvolt = <800000>;
189				regulator-max-microvolt = <1550000>;
190			};
191
192			vgen3_reg: vgen3 {
193				regulator-min-microvolt = <1800000>;
194				regulator-max-microvolt = <3300000>;
195			};
196
197			vgen4_reg: vgen4 {
198				regulator-min-microvolt = <1800000>;
199				regulator-max-microvolt = <3300000>;
200				regulator-always-on;
201			};
202
203			vgen5_reg: vgen5 {
204				regulator-min-microvolt = <1800000>;
205				regulator-max-microvolt = <3300000>;
206				regulator-always-on;
207			};
208
209			vgen6_reg: vgen6 {
210				regulator-min-microvolt = <1800000>;
211				regulator-max-microvolt = <3300000>;
212				regulator-always-on;
213			};
214		};
215	};
216};
217
218&i2c3 {
219	clock-frequency = <100000>;
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_i2c3>;
222	status = "okay";
223
224	ov2659: camera@30 {
225		compatible = "ovti,ov2659";
226		pinctrl-names = "default";
227		pinctrl-0 = <&pinctrl_ov2659>;
228		clocks = <&clks IMX6QDL_CLK_CKO>;
229		clock-names = "xvclk";
230		reg = <0x30>;
231		powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
232		reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
233		status = "okay";
234
235		port {
236			ov2659_to_ipu1_csi0_mux: endpoint {
237				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
238				link-frequencies = /bits/ 64 <70000000>;
239				bus-width = <8>;
240				hsync-active = <1>;
241				vsync-active = <1>;
242			};
243		};
244	};
245};
246
247&iomuxc {
248	pinctrl_ecspi1: ecspi1grp {
249		fsl,pins = <
250			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
251			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
252			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
253		>;
254	};
255
256	pinctrl_ecspi1_gpio: ecspi1grpgpiogrp {
257		fsl,pins = <
258			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
259			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x1b0b0
260		>;
261	};
262
263	pinctrl_enet: enetgrp {
264		fsl,pins = <
265			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
266			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
267			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
268			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
269			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
270			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
271			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
272			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
273			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
274			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
275			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
276			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
277			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
278			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
279			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
280			MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
281		>;
282	};
283
284	pinctrl_hdmi_cec: hdmicecgrp {
285		fsl,pins = <
286			MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
287		>;
288	};
289
290	pinctrl_i2c2: i2c2grp {
291		fsl,pins = <
292			MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
293			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
294		>;
295	};
296
297	pinctrl_i2c3: i2c3grp {
298		fsl,pins = <
299			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
300			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
301		>;
302	};
303
304	pinctrl_ipu1_csi0: ipu1csi0grp {
305		fsl,pins = <
306			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
307			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
308			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
309			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
310			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
311			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
312			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
313			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
314			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
315			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
316			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
317		>;
318	};
319
320	pinctrl_ov2659: ov2659grp {
321		fsl,pins = <
322			MX6QDL_PAD_GPIO_16__GPIO7_IO11		0x1b0b0
323			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0
324			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
325		>;
326	};
327
328	pinctrl_uart4: uart4grp {
329		fsl,pins = <
330			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
331			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
332		>;
333	};
334
335	pinctrl_usbotg: usbotggrp {
336		fsl,pins = <
337			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
338		>;
339	};
340
341	pinctrl_usdhc1: usdhc1grp {
342		fsl,pins = <
343			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
344			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
345			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
346			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
347			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
348			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
349		>;
350	};
351
352	pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
353		fsl,pins = <
354			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
355		>;
356	};
357
358	pinctrl_usdhc2: usdhc2grp {
359		fsl,pins = <
360			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
361			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
362			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
363			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
364			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
365			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
366		>;
367	};
368
369	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
370		fsl,pins = <
371			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
372			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
373		>;
374	};
375
376	pinctrl_usdhc3: usdhc3grp {
377		fsl,pins = <
378			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
379			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
380			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
381			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
382			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
383			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
384			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
385			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
386			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
387			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
388		>;
389	};
390
391	pinctrl_wdog: wdoggrp {
392		fsl,pins = <
393			MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
394		>;
395	};
396
397	pinctrl_gpio_leds: gpioledsgrp {
398		fsl,pins = <
399			MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
400		>;
401	};
402};
403
404&uart4 {
405	pinctrl-names = "default";
406	pinctrl-0 = <&pinctrl_uart4>;
407	status = "okay";
408};
409
410&usbh1 {
411	vbus-supply = <&reg_usb_h1_vbus>;
412	status = "okay";
413};
414
415&usbotg {
416	vbus-supply = <&reg_usb_otg_vbus>;
417	pinctrl-names = "default";
418	pinctrl-0 = <&pinctrl_usbotg>;
419	disable-over-current;
420	status = "okay";
421};
422
423&usdhc1 {
424	pinctrl-names = "default";
425	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
426	bus-width = <4>;
427	cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
428	status = "okay";
429};
430
431&usdhc2 {
432	pinctrl-names = "default";
433	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
434	bus-width = <4>;
435	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
436	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
437	status = "disabled";
438};
439
440&usdhc3 {
441	pinctrl-names = "default";
442	pinctrl-0 = <&pinctrl_usdhc3>;
443	bus-width = <8>;
444	non-removable;
445	no-1-8-v;
446	status = "okay";
447};
448
449&wdog1 {
450	status = "disabled";
451};
452
453&wdog2 {
454	pinctrl-names = "default";
455	pinctrl-0 = <&pinctrl_wdog>;
456	fsl,ext-reset-output;
457	status = "okay";
458};
459