1/*
2 * ARM Ltd. Juno Platform
3 *
4 * Copyright (c) 2013-2014 ARM Ltd.
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/arm/coresight-cti-dt.h>
13#include "juno-base.dtsi"
14
15/ {
16	model = "ARM Juno development board (r0)";
17	compatible = "arm,juno", "arm,vexpress";
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		serial0 = &soc_uart0;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	psci {
31		compatible = "arm,psci-0.2";
32		method = "smc";
33	};
34
35	cpus {
36		#address-cells = <2>;
37		#size-cells = <0>;
38
39		cpu-map {
40			cluster0 {
41				core0 {
42					cpu = <&A57_0>;
43				};
44				core1 {
45					cpu = <&A57_1>;
46				};
47			};
48
49			cluster1 {
50				core0 {
51					cpu = <&A53_0>;
52				};
53				core1 {
54					cpu = <&A53_1>;
55				};
56				core2 {
57					cpu = <&A53_2>;
58				};
59				core3 {
60					cpu = <&A53_3>;
61				};
62			};
63		};
64
65		idle-states {
66			entry-method = "psci";
67
68			CPU_SLEEP_0: cpu-sleep-0 {
69				compatible = "arm,idle-state";
70				arm,psci-suspend-param = <0x0010000>;
71				local-timer-stop;
72				entry-latency-us = <300>;
73				exit-latency-us = <1200>;
74				min-residency-us = <2000>;
75			};
76
77			CLUSTER_SLEEP_0: cluster-sleep-0 {
78				compatible = "arm,idle-state";
79				arm,psci-suspend-param = <0x1010000>;
80				local-timer-stop;
81				entry-latency-us = <400>;
82				exit-latency-us = <1200>;
83				min-residency-us = <2500>;
84			};
85		};
86
87		A57_0: cpu@0 {
88			compatible = "arm,cortex-a57";
89			reg = <0x0 0x0>;
90			device_type = "cpu";
91			enable-method = "psci";
92			i-cache-size = <0xc000>;
93			i-cache-line-size = <64>;
94			i-cache-sets = <256>;
95			d-cache-size = <0x8000>;
96			d-cache-line-size = <64>;
97			d-cache-sets = <256>;
98			next-level-cache = <&A57_L2>;
99			clocks = <&scpi_dvfs 0>;
100			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
101			capacity-dmips-mhz = <1024>;
102			dynamic-power-coefficient = <530>;
103		};
104
105		A57_1: cpu@1 {
106			compatible = "arm,cortex-a57";
107			reg = <0x0 0x1>;
108			device_type = "cpu";
109			enable-method = "psci";
110			i-cache-size = <0xc000>;
111			i-cache-line-size = <64>;
112			i-cache-sets = <256>;
113			d-cache-size = <0x8000>;
114			d-cache-line-size = <64>;
115			d-cache-sets = <256>;
116			next-level-cache = <&A57_L2>;
117			clocks = <&scpi_dvfs 0>;
118			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119			capacity-dmips-mhz = <1024>;
120			dynamic-power-coefficient = <530>;
121		};
122
123		A53_0: cpu@100 {
124			compatible = "arm,cortex-a53";
125			reg = <0x0 0x100>;
126			device_type = "cpu";
127			enable-method = "psci";
128			i-cache-size = <0x8000>;
129			i-cache-line-size = <64>;
130			i-cache-sets = <256>;
131			d-cache-size = <0x8000>;
132			d-cache-line-size = <64>;
133			d-cache-sets = <128>;
134			next-level-cache = <&A53_L2>;
135			clocks = <&scpi_dvfs 1>;
136			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
137			capacity-dmips-mhz = <578>;
138			dynamic-power-coefficient = <140>;
139		};
140
141		A53_1: cpu@101 {
142			compatible = "arm,cortex-a53";
143			reg = <0x0 0x101>;
144			device_type = "cpu";
145			enable-method = "psci";
146			i-cache-size = <0x8000>;
147			i-cache-line-size = <64>;
148			i-cache-sets = <256>;
149			d-cache-size = <0x8000>;
150			d-cache-line-size = <64>;
151			d-cache-sets = <128>;
152			next-level-cache = <&A53_L2>;
153			clocks = <&scpi_dvfs 1>;
154			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
155			capacity-dmips-mhz = <578>;
156			dynamic-power-coefficient = <140>;
157		};
158
159		A53_2: cpu@102 {
160			compatible = "arm,cortex-a53";
161			reg = <0x0 0x102>;
162			device_type = "cpu";
163			enable-method = "psci";
164			i-cache-size = <0x8000>;
165			i-cache-line-size = <64>;
166			i-cache-sets = <256>;
167			d-cache-size = <0x8000>;
168			d-cache-line-size = <64>;
169			d-cache-sets = <128>;
170			next-level-cache = <&A53_L2>;
171			clocks = <&scpi_dvfs 1>;
172			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173			capacity-dmips-mhz = <578>;
174			dynamic-power-coefficient = <140>;
175		};
176
177		A53_3: cpu@103 {
178			compatible = "arm,cortex-a53";
179			reg = <0x0 0x103>;
180			device_type = "cpu";
181			enable-method = "psci";
182			i-cache-size = <0x8000>;
183			i-cache-line-size = <64>;
184			i-cache-sets = <256>;
185			d-cache-size = <0x8000>;
186			d-cache-line-size = <64>;
187			d-cache-sets = <128>;
188			next-level-cache = <&A53_L2>;
189			clocks = <&scpi_dvfs 1>;
190			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
191			capacity-dmips-mhz = <578>;
192			dynamic-power-coefficient = <140>;
193		};
194
195		A57_L2: l2-cache0 {
196			compatible = "cache";
197			cache-unified;
198			cache-size = <0x200000>;
199			cache-line-size = <64>;
200			cache-sets = <2048>;
201			cache-level = <2>;
202		};
203
204		A53_L2: l2-cache1 {
205			compatible = "cache";
206			cache-unified;
207			cache-size = <0x100000>;
208			cache-line-size = <64>;
209			cache-sets = <1024>;
210			cache-level = <2>;
211		};
212	};
213
214	pmu-a57 {
215		compatible = "arm,cortex-a57-pmu";
216		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
217			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
218		interrupt-affinity = <&A57_0>,
219				     <&A57_1>;
220	};
221
222	pmu-a53 {
223		compatible = "arm,cortex-a53-pmu";
224		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
225			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
226			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
227			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
228		interrupt-affinity = <&A53_0>,
229				     <&A53_1>,
230				     <&A53_2>,
231				     <&A53_3>;
232	};
233};
234
235&etm0 {
236	cpu = <&A57_0>;
237};
238
239&etm1 {
240	cpu = <&A57_1>;
241};
242
243&etm2 {
244	cpu = <&A53_0>;
245};
246
247&etm3 {
248	cpu = <&A53_1>;
249};
250
251&etm4 {
252	cpu = <&A53_2>;
253};
254
255&etm5 {
256	cpu = <&A53_3>;
257};
258
259&etf0_out_port {
260	remote-endpoint = <&replicator_in_port0>;
261};
262
263&replicator_in_port0 {
264	remote-endpoint = <&etf0_out_port>;
265};
266
267&stm_out_port {
268	remote-endpoint = <&main_funnel_in_port2>;
269};
270
271&main_funnel_in_ports {
272	port@2 {
273		reg = <2>;
274		main_funnel_in_port2: endpoint {
275			remote-endpoint = <&stm_out_port>;
276		};
277	};
278};
279
280&cpu_debug0 {
281	cpu = <&A57_0>;
282};
283
284&cpu_debug1 {
285	cpu = <&A57_1>;
286};
287
288&cpu_debug2 {
289	cpu = <&A53_0>;
290};
291
292&cpu_debug3 {
293	cpu = <&A53_1>;
294};
295
296&cpu_debug4 {
297	cpu = <&A53_2>;
298};
299
300&cpu_debug5 {
301	cpu = <&A53_3>;
302};
303
304&cti0 {
305	cpu = <&A57_0>;
306};
307
308&cti1 {
309	cpu = <&A57_1>;
310};
311
312&cti2 {
313	cpu = <&A53_0>;
314};
315
316&cti3 {
317	cpu = <&A53_1>;
318};
319
320&cti4 {
321	cpu = <&A53_2>;
322};
323
324&cti5 {
325	cpu = <&A53_3>;
326};
327