1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8/dts-v1/;
9
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/net/ti-dp83867.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <dt-bindings/usb/pd.h>
15#include "imx93-tqma9352.dtsi"
16
17/{
18	model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
19	compatible = "tq,imx93-tqma9352-mba93xxla",
20		     "tq,imx93-tqma9352", "fsl,imx93";
21	chassis-type = "embedded";
22
23	chosen {
24		stdout-path = &lpuart1;
25	};
26
27	aliases {
28		eeprom0 = &eeprom0;
29		rtc0 = &pcf85063;
30		rtc1 = &bbnsm_rtc;
31	};
32
33	backlight_lvds: backlight {
34		compatible = "pwm-backlight";
35		pwms = <&tpm5 0 5000000 0>;
36		brightness-levels = <0 4 8 16 32 64 128 255>;
37		default-brightness-level = <7>;
38		power-supply = <&reg_12v0>;
39		enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
40		status = "disabled";
41	};
42
43	clk_dp: clk-dp {
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46		clock-frequency = <26000000>;
47	};
48
49	gpio-keys {
50		compatible = "gpio-keys";
51		autorepeat;
52
53		switch-a {
54			label = "switcha";
55			linux,code = <BTN_0>;
56			gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
57			wakeup-source;
58		};
59
60		switch-b {
61			label = "switchb";
62			linux,code = <BTN_1>;
63			gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
64			wakeup-source;
65		};
66	};
67
68	gpio-leds {
69		compatible = "gpio-leds";
70
71		led-1 {
72			color = <LED_COLOR_ID_GREEN>;
73			function = LED_FUNCTION_STATUS;
74			gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
75			linux,default-trigger = "default-on";
76		};
77
78		led-2 {
79			color = <LED_COLOR_ID_AMBER>;
80			function = LED_FUNCTION_HEARTBEAT;
81			gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
82			linux,default-trigger = "heartbeat";
83		};
84	};
85
86	iio-hwmon {
87		compatible = "iio-hwmon";
88		io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
89	};
90
91	reg_3v3: regulator-3v3 {
92		compatible = "regulator-fixed";
93		regulator-name = "V_3V3_MB";
94		regulator-min-microvolt = <3300000>;
95		regulator-max-microvolt = <3300000>;
96	};
97
98	reg_3v8: regulator-3v8 {
99		compatible = "regulator-fixed";
100		regulator-name = "V_3V8";
101		regulator-min-microvolt = <3800000>;
102		regulator-max-microvolt = <3800000>;
103		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
104		enable-active-high;
105		/* TODO: this is supply for IOT module */
106		regulator-always-on;
107	};
108
109	reg_5v0: regulator-5v0 {
110		compatible = "regulator-fixed";
111		regulator-name = "V_5V0_MB";
112		regulator-min-microvolt = <5000000>;
113		regulator-max-microvolt = <5000000>;
114	};
115
116	reg_12v0: regulator-12v0 {
117		compatible = "regulator-fixed";
118		regulator-name = "V_12V";
119		regulator-min-microvolt = <12000000>;
120		regulator-max-microvolt = <12000000>;
121		gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
122		enable-active-high;
123	};
124};
125
126&adc1 {
127	status = "okay";
128};
129
130&eqos {
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_eqos>;
133	phy-mode = "rgmii-id";
134	phy-handle = <&ethphy_eqos>;
135	status = "okay";
136
137	mdio {
138		compatible = "snps,dwmac-mdio";
139		#address-cells = <1>;
140		#size-cells = <0>;
141
142		ethphy_eqos: ethernet-phy@0 {
143			compatible = "ethernet-phy-ieee802.3-c22";
144			reg = <0>;
145			pinctrl-names = "default";
146			pinctrl-0 = <&pinctrl_eqos_phy>;
147			interrupt-parent = <&gpio3>;
148			interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
149			reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
150			reset-assert-us = <500000>;
151			reset-deassert-us = <50000>;
152			enet-phy-lane-no-swap;
153			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
154			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
155			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
156			ti,dp83867-rxctrl-strap-quirk;
157			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
158		};
159	};
160};
161
162&fec {
163	pinctrl-names = "default";
164	pinctrl-0 = <&pinctrl_fec>;
165	phy-mode = "rgmii-id";
166	phy-handle = <&ethphy_fec>;
167	fsl,magic-packet;
168	status = "okay";
169
170	mdio {
171		#address-cells = <1>;
172		#size-cells = <0>;
173		clock-frequency = <5000000>;
174
175		ethphy_fec: ethernet-phy@0 {
176			compatible = "ethernet-phy-ieee802.3-c22";
177			reg = <0>;
178			pinctrl-names = "default";
179			pinctrl-0 = <&pinctrl_fec_phy>;
180			interrupt-parent = <&gpio3>;
181			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
182			reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
183			reset-assert-us = <500000>;
184			reset-deassert-us = <50000>;
185			enet-phy-lane-no-swap;
186			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
187			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
188			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
189			ti,dp83867-rxctrl-strap-quirk;
190			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
191		};
192	};
193};
194
195&flexcan1 {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_flexcan1>;
198	xceiver-supply = <&reg_3v3>;
199	status = "okay";
200};
201
202&flexcan2 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_flexcan2>;
205	xceiver-supply = <&reg_3v3>;
206	status = "okay";
207};
208
209&gpio1 {
210	expander-irq-hog {
211		gpio-hog;
212		gpios = <12 GPIO_ACTIVE_LOW>;
213		input;
214		line-name = "PEX_INT#";
215	};
216
217	rtc-irq-hog {
218		gpio-hog;
219		gpios = <14 GPIO_ACTIVE_LOW>;
220		input;
221		line-name = "RTC_EVENT#";
222	};
223};
224
225&gpio3 {
226	ethphy-eqos-irq-hog {
227		gpio-hog;
228		gpios = <26 GPIO_ACTIVE_LOW>;
229		input;
230		line-name = "ENET0_IRQ#";
231	};
232
233	ethphy-fec-irq-hog {
234		gpio-hog;
235		gpios = <27 GPIO_ACTIVE_LOW>;
236		input;
237		line-name = "ENET1_IRQ#";
238	};
239};
240
241&lpi2c3 {
242	#address-cells = <1>;
243	#size-cells = <0>;
244	clock-frequency = <400000>;
245	pinctrl-names = "default", "sleep";
246	pinctrl-0 = <&pinctrl_lpi2c3>;
247	pinctrl-1 = <&pinctrl_lpi2c3>;
248	status = "okay";
249
250	temperature-sensor@1c {
251		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
252		reg = <0x1c>;
253	};
254
255	eeprom2: eeprom@54 {
256		compatible = "nxp,se97b", "atmel,24c02";
257		reg = <0x54>;
258		pagesize = <16>;
259		vcc-supply = <&reg_3v3>;
260	};
261
262	expander0: gpio@70 {
263		compatible = "nxp,pca9538";
264		reg = <0x70>;
265		pinctrl-names = "default";
266		pinctrl-0 = <&pinctrl_pexp_irq>;
267		gpio-controller;
268		#gpio-cells = <2>;
269		interrupt-controller;
270		#interrupt-cells = <2>;
271		interrupt-parent = <&gpio1>;
272		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
273		vcc-supply = <&reg_3v3>;
274		gpio-line-names = "3V8_EN", "",
275				  "", "IOT_PWRKEY",
276				  "IOT_RESET", "IOT_W_DISABLE",
277				  "BUTTON_A#", "BUTTON_B#";
278
279		/*
280		 * Controls the IOT W_DISABLE pin which is low active
281		 * as disable signal but inverted as seen from the CPU.
282		 * The output-low states, the signal is
283		 * inactive, e.g. not disabled
284		 */
285		iot_wdisable_hog: iot-wdisable-hog {
286			gpio-hog;
287			gpios = <5 GPIO_ACTIVE_HIGH>;
288			output-low;
289			line-name = "IOT_W_DISABLE";
290		};
291	};
292
293	expander1: gpio@71 {
294		compatible = "nxp,pca9538";
295		reg = <0x71>;
296		gpio-controller;
297		#gpio-cells = <2>;
298		vcc-supply = <&reg_3v3>;
299		gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
300				  "USB_RESET#", "",
301				  "WLAN_PD#", "WLAN_W_DISABLE#",
302				  "WLAN_PERST#", "12V_EN";
303
304		/*
305		 * Controls the WiFi card PD pin which is low active
306		 * as power down signal. The output-low states, the signal
307		 * is inactive, e.g. not power down
308		 */
309		wlan-pd-hog {
310			gpio-hog;
311			gpios = <4 GPIO_ACTIVE_LOW>;
312			output-low;
313			line-name = "WLAN_PD#";
314		};
315
316		/*
317		 * Controls the WiFi card disable pin which is low active
318		 * as disable signal. The output-low states, the signal
319		 * is inactive, e.g. not disabled
320		 */
321		wlan-wdisable-hog {
322			gpio-hog;
323			gpios = <5 GPIO_ACTIVE_LOW>;
324			output-low;
325			line-name = "WLAN_W_DISABLE#";
326		};
327
328		/*
329		 * Controls the WiFi card reset pin which is low active
330		 * as reset signal. The output-low states, the signal
331		 * is inactive, e.g. not in reset
332		 */
333		wlan-perst-hog {
334			gpio-hog;
335			gpios = <6 GPIO_ACTIVE_LOW>;
336			output-low;
337			line-name = "WLAN_PERST#";
338		};
339	};
340
341	expander2: gpio@72 {
342		compatible = "nxp,pca9538";
343		reg = <0x72>;
344		gpio-controller;
345		#gpio-cells = <2>;
346		vcc-supply = <&reg_3v3>;
347		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
348				  "LCD_BL_EN", "DP_EN",
349				  "MIPI_CSI_EN", "MIPI_CSI_RST#",
350				  "USER_LED1", "USER_LED2";
351	};
352};
353
354&lpi2c5 {
355	#address-cells = <1>;
356	#size-cells = <0>;
357	clock-frequency = <400000>;
358	pinctrl-names = "default", "sleep";
359	pinctrl-0 = <&pinctrl_lpi2c5>;
360	pinctrl-1 = <&pinctrl_lpi2c5>;
361	status = "okay";
362
363	dp_bridge: dp-bridge@f {
364		compatible = "toshiba,tc9595", "toshiba,tc358767";
365		reg = <0x0f>;
366		pinctrl-names = "default";
367		pinctrl-0 = <&pinctrl_tc9595>;
368		clock-names = "ref";
369		clocks = <&clk_dp>;
370		reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
371		interrupt-parent = <&gpio4>;
372		interrupts = <29 IRQ_TYPE_EDGE_RISING>;
373		toshiba,hpd-pin = <0>;
374		status = "disabled";
375
376		ports {
377			#address-cells = <1>;
378			#size-cells = <0>;
379
380			port@0 {
381				reg = <0>;
382
383				dp_dsi_in: endpoint {
384					data-lanes = <1 2 3 4>;
385				};
386			};
387		};
388	};
389};
390
391&lpuart1 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_uart1>;
394	status = "okay";
395};
396
397&lpuart2 {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_uart2>;
400	linux,rs485-enabled-at-boot-time;
401	status = "okay";
402};
403
404/* disabled per default, console for M33 */
405&lpuart3 {
406	pinctrl-names = "default";
407	pinctrl-0 = <&pinctrl_uart3>;
408	status = "disabled";
409};
410
411&lpuart6 {
412	pinctrl-names = "default";
413	pinctrl-0 = <&pinctrl_uart6>;
414	status = "okay";
415};
416
417&lpuart8 {
418	pinctrl-names = "default";
419	pinctrl-0 = <&pinctrl_uart8>;
420	status = "okay";
421};
422
423&pcf85063 {
424	/* RTC_EVENT# is connected on MBa93xxLA */
425	pinctrl-names = "default";
426	pinctrl-0 = <&pinctrl_pcf85063>;
427	interrupt-parent = <&gpio1>;
428	interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
429};
430
431&tpm5 {
432	pinctrl-names = "default";
433	pinctrl-0 = <&pinctrl_tpm5>;
434};
435
436&usdhc2 {
437	pinctrl-names = "default", "state_100mhz", "state_200mhz";
438	pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
439	pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
440	pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
441	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
442	vmmc-supply = <&reg_usdhc2_vmmc>;
443	bus-width = <4>;
444	no-sdio;
445	no-mmc;
446	disable-wp;
447	status = "okay";
448};
449
450&iomuxc {
451	pinctrl_eqos: eqosgrp {
452		fsl,pins = <
453			/* PD | FSEL_2 | DSE X4 */
454			MX93_PAD_ENET1_MDC__ENET_QOS_MDC		0x51e
455			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO		0x4000051e
456			/* PD | FSEL_2 | DSE X6 */
457			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e
458			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e
459			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2		0x57e
460			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3		0x57e
461			/* PD | FSEL_3 | DSE X6 */
462			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
463			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e
464			/* PD | FSEL_2 | DSE X4 */
465			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x51e
466			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x51e
467			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2		0x51e
468			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3		0x51e
469			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x51e
470			/* PD | FSEL_3 | DSE X3 */
471			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
472		>;
473	};
474
475	pinctrl_eqos_phy: eqosphygrp {
476		fsl,pins = <
477			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x1306
478		>;
479	};
480
481	pinctrl_fec: fecgrp {
482		fsl,pins = <
483			/* PD | FSEL_2 | DSE X4 */
484			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
485			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000051e
486			/* PD | FSEL_2 | DSE X6 */
487			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
488			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
489			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
490			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
491			/* PD | FSEL_3 | DSE X6 */
492			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
493			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
494			/* PD | FSEL_2 | DSE X4 */
495			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x51e
496			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x51e
497			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x51e
498			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x51e
499			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x51e
500			/* PD | FSEL_3 | DSE X3 */
501			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
502		>;
503	};
504
505	pinctrl_fec_phy: fecphygrp {
506		fsl,pins = <
507			MX93_PAD_CCM_CLKO2__GPIO3_IO27		0x1306
508		>;
509	};
510
511	pinctrl_flexcan1: flexcan1grp {
512		fsl,pins = <
513			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
514			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
515		>;
516	};
517
518	pinctrl_flexcan2: flexcan2grp {
519		fsl,pins = <
520			MX93_PAD_GPIO_IO25__CAN2_TX		0x139e
521			MX93_PAD_GPIO_IO27__CAN2_RX		0x139e
522		>;
523	};
524
525	pinctrl_lpi2c3: lpi2c3grp {
526		fsl,pins = <
527			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
528			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
529		>;
530	};
531
532	pinctrl_lpi2c5: lpi2c5grp {
533		fsl,pins = <
534			MX93_PAD_GPIO_IO22__LPI2C5_SDA		0x40000b9e
535			MX93_PAD_GPIO_IO23__LPI2C5_SCL		0x40000b9e
536		>;
537	};
538
539	pinctrl_pcf85063: pcf85063grp {
540		fsl,pins = <
541			MX93_PAD_SAI1_RXD0__GPIO1_IO14		0x1306
542		>;
543	};
544
545	pinctrl_pexp_irq: pexpirqgrp {
546		fsl,pins = <
547			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x1306
548		>;
549	};
550
551	pinctrl_tc9595: tc9595-grp {
552		fsl,pins = <
553			/* DP_IRQ */
554			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x1306
555		>;
556	};
557
558	pinctrl_tpm5: tpm5grp {
559		fsl,pins = <
560			MX93_PAD_GPIO_IO06__TPM5_CH0		0x57e
561		>;
562	};
563
564	pinctrl_typec: typecgrp {
565		fsl,pins = <
566			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x1306
567		>;
568	};
569
570	pinctrl_uart1: uart1grp {
571		fsl,pins = <
572			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
573			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e
574		>;
575	};
576
577	pinctrl_uart2: uart2grp {
578		fsl,pins = <
579			MX93_PAD_UART2_TXD__LPUART2_TX		0x31e
580			MX93_PAD_UART2_RXD__LPUART2_RX		0x31e
581			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B	0x51e
582		>;
583	};
584
585	pinctrl_uart3: uart3grp {
586		fsl,pins = <
587			MX93_PAD_GPIO_IO14__LPUART3_TX		0x31e
588			MX93_PAD_GPIO_IO15__LPUART3_RX		0x31e
589		>;
590	};
591
592	pinctrl_uart6: uart6grp {
593		fsl,pins = <
594			MX93_PAD_GPIO_IO04__LPUART6_TX		0x31e
595			MX93_PAD_GPIO_IO05__LPUART6_RX		0x31e
596		>;
597	};
598
599	pinctrl_uart8: uart8grp {
600		fsl,pins = <
601			MX93_PAD_GPIO_IO12__LPUART8_TX		0x31e
602			MX93_PAD_GPIO_IO13__LPUART8_RX		0x31e
603		>;
604	};
605
606	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
607		fsl,pins = <
608			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
609		>;
610	};
611
612	pinctrl_usdhc2_hs: usdhc2hsgrp {
613		fsl,pins = <
614			/* HYS | PD | PU | FSEL_3 | DSE X5 */
615			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17be
616			/* HYS | PD | PU | FSEL_3 | DSE X4 */
617			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
618			/* HYS | PD | PU | FSEL_3 | DSE X3 */
619			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
620			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
621			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
622			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
623			/* PD | PU | FSEL_2 | DSE X3 */
624			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
625		>;
626	};
627
628	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
629		fsl,pins = <
630			/* HYS | PD | PU | FSEL_3 | DSE X6 */
631			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17fe
632			/* HYS | PD | PU | FSEL_3 | DSE X4 */
633			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
634			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x139e
635			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x139e
636			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x139e
637			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x139e
638			/* PD | PU | FSEL_2 | DSE X3 */
639			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
640		>;
641	};
642};
643