1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 rt1015p: audio-codec { 214 compatible = "realtek,rt1015p"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&rt1015p_pins>; 217 sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>; 218 #sound-dai-cells = <0>; 219 }; 220 221 sound: sound { 222 mediatek,platform = <&afe>; 223 pinctrl-names = "aud_clk_mosi_off", 224 "aud_clk_mosi_on", 225 "aud_dat_mosi_off", 226 "aud_dat_mosi_on", 227 "aud_dat_miso_off", 228 "aud_dat_miso_on", 229 "vow_dat_miso_off", 230 "vow_dat_miso_on", 231 "vow_clk_miso_off", 232 "vow_clk_miso_on", 233 "aud_nle_mosi_off", 234 "aud_nle_mosi_on", 235 "aud_dat_miso2_off", 236 "aud_dat_miso2_on", 237 "aud_gpio_i2s3_off", 238 "aud_gpio_i2s3_on", 239 "aud_gpio_i2s8_off", 240 "aud_gpio_i2s8_on", 241 "aud_gpio_i2s9_off", 242 "aud_gpio_i2s9_on", 243 "aud_dat_mosi_ch34_off", 244 "aud_dat_mosi_ch34_on", 245 "aud_dat_miso_ch34_off", 246 "aud_dat_miso_ch34_on", 247 "aud_gpio_tdm_off", 248 "aud_gpio_tdm_on"; 249 pinctrl-0 = <&aud_clk_mosi_off_pins>; 250 pinctrl-1 = <&aud_clk_mosi_on_pins>; 251 pinctrl-2 = <&aud_dat_mosi_off_pins>; 252 pinctrl-3 = <&aud_dat_mosi_on_pins>; 253 pinctrl-4 = <&aud_dat_miso_off_pins>; 254 pinctrl-5 = <&aud_dat_miso_on_pins>; 255 pinctrl-6 = <&vow_dat_miso_off_pins>; 256 pinctrl-7 = <&vow_dat_miso_on_pins>; 257 pinctrl-8 = <&vow_clk_miso_off_pins>; 258 pinctrl-9 = <&vow_clk_miso_on_pins>; 259 pinctrl-10 = <&aud_nle_mosi_off_pins>; 260 pinctrl-11 = <&aud_nle_mosi_on_pins>; 261 pinctrl-12 = <&aud_dat_miso2_off_pins>; 262 pinctrl-13 = <&aud_dat_miso2_on_pins>; 263 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 264 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 265 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 266 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 267 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 268 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 269 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 270 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 271 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 272 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 273 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 274 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 275 }; 276}; 277 278&dsi0 { 279 status = "okay"; 280}; 281 282&dsi_out { 283 remote-endpoint = <&anx7625_in>; 284}; 285 286&gic { 287 mediatek,broken-save-restore-fw; 288}; 289 290&gpu { 291 mali-supply = <&mt6315_7_vbuck1>; 292 status = "okay"; 293}; 294 295&i2c0 { 296 status = "okay"; 297 298 clock-frequency = <400000>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c0_pins>; 301 302 touchscreen: touchscreen@10 { 303 reg = <0x10>; 304 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&touchscreen_pins>; 307 }; 308}; 309 310&i2c1 { 311 status = "okay"; 312 313 clock-frequency = <400000>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&i2c1_pins>; 316 317 rt5682: audio-codec@1a { 318 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 319 reg = <0x1a>; 320 interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>; 321 realtek,jd-src = <1>; 322 #sound-dai-cells = <1>; 323 324 AVDD-supply = <&mt6359_vio18_ldo_reg>; 325 DBVDD-supply = <&mt6359_vio18_ldo_reg>; 326 LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; 327 MICVDD-supply = <&pp3300_g>; 328 }; 329}; 330 331&i2c2 { 332 status = "okay"; 333 334 clock-frequency = <400000>; 335 clock-stretch-ns = <12600>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&i2c2_pins>; 338 339 trackpad@15 { 340 compatible = "elan,ekth3000"; 341 reg = <0x15>; 342 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&trackpad_pins>; 345 vcc-supply = <&pp3300_u>; 346 wakeup-source; 347 }; 348}; 349 350&i2c3 { 351 status = "okay"; 352 353 clock-frequency = <400000>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&i2c3_pins>; 356 357 anx_bridge: anx7625@58 { 358 compatible = "analogix,anx7625"; 359 reg = <0x58>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&anx7625_pins>; 362 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 363 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 364 vdd10-supply = <&pp1000_mipibrdg>; 365 vdd18-supply = <&pp1800_mipibrdg>; 366 vdd33-supply = <&pp3300_mipibrdg>; 367 368 ports { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 372 port@0 { 373 reg = <0>; 374 375 anx7625_in: endpoint { 376 remote-endpoint = <&dsi_out>; 377 }; 378 }; 379 380 port@1 { 381 reg = <1>; 382 383 anx7625_out: endpoint { 384 remote-endpoint = <&panel_in>; 385 }; 386 }; 387 }; 388 389 aux-bus { 390 panel: panel { 391 compatible = "edp-panel"; 392 power-supply = <&pp3300_mipibrdg>; 393 backlight = <&backlight_lcd0>; 394 395 port { 396 panel_in: endpoint { 397 remote-endpoint = <&anx7625_out>; 398 }; 399 }; 400 }; 401 }; 402 }; 403}; 404 405&i2c7 { 406 status = "okay"; 407 408 clock-frequency = <400000>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&i2c7_pins>; 411}; 412 413&mfg0 { 414 domain-supply = <&mt6315_7_vbuck1>; 415}; 416 417&mfg1 { 418 domain-supply = <&mt6359_vsram_others_ldo_reg>; 419}; 420 421&mipi_tx0 { 422 status = "okay"; 423}; 424 425&mmc0 { 426 status = "okay"; 427 428 pinctrl-names = "default", "state_uhs"; 429 pinctrl-0 = <&mmc0_default_pins>; 430 pinctrl-1 = <&mmc0_uhs_pins>; 431 bus-width = <8>; 432 max-frequency = <200000000>; 433 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 434 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 435 cap-mmc-highspeed; 436 mmc-hs200-1_8v; 437 mmc-hs400-1_8v; 438 supports-cqe; 439 cap-mmc-hw-reset; 440 mmc-hs400-enhanced-strobe; 441 hs400-ds-delay = <0x12814>; 442 no-sdio; 443 no-sd; 444 non-removable; 445}; 446 447&mmc1 { 448 status = "okay"; 449 450 pinctrl-names = "default", "state_uhs"; 451 pinctrl-0 = <&mmc1_default_pins>; 452 pinctrl-1 = <&mmc1_uhs_pins>; 453 bus-width = <4>; 454 max-frequency = <200000000>; 455 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 456 vmmc-supply = <&mt6360_ldo5_reg>; 457 vqmmc-supply = <&mt6360_ldo3_reg>; 458 cap-sd-highspeed; 459 sd-uhs-sdr50; 460 sd-uhs-sdr104; 461 no-sdio; 462 no-mmc; 463}; 464 465/* for CORE */ 466&mt6359_vgpu11_buck_reg { 467 regulator-always-on; 468}; 469 470&mt6359_vgpu11_sshub_buck_reg { 471 regulator-always-on; 472 regulator-min-microvolt = <575000>; 473 regulator-max-microvolt = <575000>; 474}; 475 476&mt6359_vrf12_ldo_reg { 477 regulator-always-on; 478}; 479 480&mt6359_vsram_others_ldo_reg { 481 regulator-min-microvolt = <750000>; 482 regulator-max-microvolt = <800000>; 483 regulator-coupled-with = <&mt6315_7_vbuck1>; 484 regulator-coupled-max-spread = <10000>; 485}; 486 487&mt6359_vufs_ldo_reg { 488 regulator-always-on; 489}; 490 491&mt6359codec { 492 mediatek,dmic-mode = <1>; /* one-wire */ 493 mediatek,mic-type-0 = <2>; /* DMIC */ 494 mediatek,mic-type-2 = <2>; /* DMIC */ 495}; 496 497&nor_flash { 498 status = "okay"; 499 500 pinctrl-names = "default"; 501 pinctrl-0 = <&nor_flash_pins>; 502 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 503 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 504 505 flash@0 { 506 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 507 reg = <0>; 508 spi-max-frequency = <52000000>; 509 spi-rx-bus-width = <2>; 510 spi-tx-bus-width = <2>; 511 }; 512}; 513 514&pcie { 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pcie_pins>; 517 518 pcie0: pcie@0,0 { 519 device_type = "pci"; 520 reg = <0x0000 0 0 0 0>; 521 num-lanes = <1>; 522 bus-range = <0x1 0x1>; 523 524 #address-cells = <3>; 525 #size-cells = <2>; 526 ranges; 527 528 wifi: wifi@0,0 { 529 reg = <0x10000 0 0 0 0x100000>, 530 <0x10000 0 0x100000 0 0x100000>; 531 memory-region = <&wifi_restricted_dma_region>; 532 }; 533 }; 534}; 535 536&pio { 537 /* 220 lines */ 538 gpio-line-names = "I2S_DP_LRCK", 539 "IS_DP_BCLK", 540 "I2S_DP_MCLK", 541 "I2S_DP_DATAOUT", 542 "SAR0_INT_ODL", 543 "EC_AP_INT_ODL", 544 "EDPBRDG_INT_ODL", 545 "DPBRDG_INT_ODL", 546 "DPBRDG_PWREN", 547 "DPBRDG_RST_ODL", 548 "I2S_HP_MCLK", 549 "I2S_HP_BCK", 550 "I2S_HP_LRCK", 551 "I2S_HP_DATAIN", 552 /* 553 * AP_FLASH_WP_L is crossystem ABI. Schematics 554 * call it AP_FLASH_WP_ODL. 555 */ 556 "AP_FLASH_WP_L", 557 "TRACKPAD_INT_ODL", 558 "EC_AP_HPD_OD", 559 "SD_CD_ODL", 560 "HP_INT_ODL_ALC", 561 "EN_PP1000_DPBRDG", 562 "AP_GPIO20", 563 "TOUCH_INT_L_1V8", 564 "UART_BT_WAKE_ODL", 565 "AP_GPIO23", 566 "AP_SPI_FLASH_CS_L", 567 "AP_SPI_FLASH_CLK", 568 "EN_PP3300_DPBRDG_DX", 569 "AP_SPI_FLASH_MOSI", 570 "AP_SPI_FLASH_MISO", 571 "I2S_HP_DATAOUT", 572 "AP_GPIO30", 573 "I2S_SPKR_MCLK", 574 "I2S_SPKR_BCLK", 575 "I2S_SPKR_LRCK", 576 "I2S_SPKR_DATAIN", 577 "I2S_SPKR_DATAOUT", 578 "AP_SPI_H1_TPM_CLK", 579 "AP_SPI_H1_TPM_CS_L", 580 "AP_SPI_H1_TPM_MISO", 581 "AP_SPI_H1_TPM_MOSI", 582 "BL_PWM", 583 "EDPBRDG_PWREN", 584 "EDPBRDG_RST_ODL", 585 "EN_PP3300_HUB", 586 "HUB_RST_L", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "SD_CLK", 594 "SD_CMD", 595 "SD_DATA3", 596 "SD_DATA0", 597 "SD_DATA2", 598 "SD_DATA1", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "PCIE_WAKE_ODL", 606 "PCIE_RST_L", 607 "PCIE_CLKREQ_ODL", 608 "", 609 "", 610 "", 611 "", 612 "", 613 "", 614 "", 615 "", 616 "", 617 "", 618 "", 619 "", 620 "", 621 "", 622 "", 623 "", 624 "", 625 "", 626 "", 627 "", 628 "", 629 "", 630 "", 631 "SPMI_SCL", 632 "SPMI_SDA", 633 "AP_GOOD", 634 "UART_DBG_TX_AP_RX", 635 "UART_AP_TX_DBG_RX", 636 "UART_AP_TX_BT_RX", 637 "UART_BT_TX_AP_RX", 638 "MIPI_DPI_D0_R", 639 "MIPI_DPI_D1_R", 640 "MIPI_DPI_D2_R", 641 "MIPI_DPI_D3_R", 642 "MIPI_DPI_D4_R", 643 "MIPI_DPI_D5_R", 644 "MIPI_DPI_D6_R", 645 "MIPI_DPI_D7_R", 646 "MIPI_DPI_D8_R", 647 "MIPI_DPI_D9_R", 648 "MIPI_DPI_D10_R", 649 "", 650 "", 651 "MIPI_DPI_DE_R", 652 "MIPI_DPI_D11_R", 653 "MIPI_DPI_VSYNC_R", 654 "MIPI_DPI_CLK_R", 655 "MIPI_DPI_HSYNC_R", 656 "PCM_BT_DATAIN", 657 "PCM_BT_SYNC", 658 "PCM_BT_DATAOUT", 659 "PCM_BT_CLK", 660 "AP_I2C_AUDIO_SCL", 661 "AP_I2C_AUDIO_SDA", 662 "SCP_I2C_SCL", 663 "SCP_I2C_SDA", 664 "AP_I2C_WLAN_SCL", 665 "AP_I2C_WLAN_SDA", 666 "AP_I2C_DPBRDG_SCL", 667 "AP_I2C_DPBRDG_SDA", 668 "EN_PP1800_DPBRDG_DX", 669 "EN_PP3300_EDP_DX", 670 "EN_PP1800_EDPBRDG_DX", 671 "EN_PP1000_EDPBRDG", 672 "SCP_JTAG0_TDO", 673 "SCP_JTAG0_TDI", 674 "SCP_JTAG0_TMS", 675 "SCP_JTAG0_TCK", 676 "SCP_JTAG0_TRSTN", 677 "EN_PP3000_VMC_PMU", 678 "EN_PP3300_DISPLAY_DX", 679 "TOUCH_RST_L_1V8", 680 "TOUCH_REPORT_DISABLE", 681 "", 682 "", 683 "AP_I2C_TRACKPAD_SCL_1V8", 684 "AP_I2C_TRACKPAD_SDA_1V8", 685 "EN_PP3300_WLAN", 686 "BT_KILL_L", 687 "WIFI_KILL_L", 688 "SET_VMC_VOLT_AT_1V8", 689 "EN_SPK", 690 "AP_WARM_RST_REQ", 691 "", 692 "", 693 "EN_PP3000_SD_S3", 694 "AP_EDP_BKLTEN", 695 "", 696 "", 697 "", 698 "AP_SPI_EC_CLK", 699 "AP_SPI_EC_CS_L", 700 "AP_SPI_EC_MISO", 701 "AP_SPI_EC_MOSI", 702 "AP_I2C_EDPBRDG_SCL", 703 "AP_I2C_EDPBRDG_SDA", 704 "MT6315_PROC_INT", 705 "MT6315_GPU_INT", 706 "UART_SERVO_TX_SCP_RX", 707 "UART_SCP_TX_SERVO_RX", 708 "BT_RTS_AP_CTS", 709 "AP_RTS_BT_CTS", 710 "UART_AP_WAKE_BT_ODL", 711 "WLAN_ALERT_ODL", 712 "EC_IN_RW_ODL", 713 "H1_AP_INT_ODL", 714 "", 715 "", 716 "", 717 "", 718 "", 719 "", 720 "", 721 "", 722 "", 723 "", 724 "", 725 "MSDC0_CMD", 726 "MSDC0_DAT0", 727 "MSDC0_DAT2", 728 "MSDC0_DAT4", 729 "MSDC0_DAT6", 730 "MSDC0_DAT1", 731 "MSDC0_DAT5", 732 "MSDC0_DAT7", 733 "MSDC0_DSL", 734 "MSDC0_CLK", 735 "MSDC0_DAT3", 736 "MSDC0_RST_L", 737 "SCP_VREQ_VAO", 738 "AUD_DAT_MOSI2", 739 "AUD_NLE_MOSI1", 740 "AUD_NLE_MOSI0", 741 "AUD_DAT_MISO2", 742 "AP_I2C_SAR_SDA", 743 "AP_I2C_SAR_SCL", 744 "AP_I2C_PWR_SCL", 745 "AP_I2C_PWR_SDA", 746 "AP_I2C_TS_SCL_1V8", 747 "AP_I2C_TS_SDA_1V8", 748 "SRCLKENA0", 749 "SRCLKENA1", 750 "AP_EC_WATCHDOG_L", 751 "PWRAP_SPI0_MI", 752 "PWRAP_SPI0_CSN", 753 "PWRAP_SPI0_MO", 754 "PWRAP_SPI0_CK", 755 "AP_RTC_CLK32K", 756 "AUD_CLK_MOSI", 757 "AUD_SYNC_MOSI", 758 "AUD_DAT_MOSI0", 759 "AUD_DAT_MOSI1", 760 "AUD_DAT_MISO0", 761 "AUD_DAT_MISO1"; 762 763 anx7625_pins: anx7625-default-pins { 764 pins-out { 765 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 766 <PINMUX_GPIO42__FUNC_GPIO42>; 767 output-low; 768 }; 769 770 pins-in { 771 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 772 input-enable; 773 bias-pull-up; 774 }; 775 }; 776 777 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 778 pins-mosi-off { 779 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 780 <PINMUX_GPIO215__FUNC_GPIO215>; 781 }; 782 }; 783 784 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 785 pins-mosi-on { 786 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 787 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 788 drive-strength = <10>; 789 }; 790 }; 791 792 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 793 pins-miso-off { 794 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 795 }; 796 }; 797 798 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 799 pins-miso-on { 800 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 801 }; 802 }; 803 804 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 805 pins-miso-off { 806 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 807 <PINMUX_GPIO219__FUNC_GPIO219>; 808 }; 809 }; 810 811 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 812 pins-miso-on { 813 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 814 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 815 drive-strength = <10>; 816 }; 817 }; 818 819 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 820 pins-miso-off { 821 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 822 }; 823 }; 824 825 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 826 pins-miso-on { 827 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 828 }; 829 }; 830 831 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 832 pins-mosi-off { 833 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 834 }; 835 }; 836 837 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 838 pins-mosi-on { 839 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 840 }; 841 }; 842 843 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 844 pins-mosi-off { 845 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 846 <PINMUX_GPIO217__FUNC_GPIO217>; 847 }; 848 }; 849 850 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 851 pins-mosi-on { 852 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 853 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 854 drive-strength = <10>; 855 }; 856 }; 857 858 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 859 pins-i2s3-off { 860 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 861 <PINMUX_GPIO33__FUNC_GPIO33>, 862 <PINMUX_GPIO35__FUNC_GPIO35>; 863 }; 864 }; 865 866 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 867 pins-i2s3-on { 868 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 869 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 870 <PINMUX_GPIO35__FUNC_I2S3_DO>; 871 }; 872 }; 873 874 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 875 pins-i2s8-off { 876 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 877 <PINMUX_GPIO11__FUNC_GPIO11>, 878 <PINMUX_GPIO12__FUNC_GPIO12>, 879 <PINMUX_GPIO13__FUNC_GPIO13>; 880 }; 881 }; 882 883 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 884 pins-i2s8-on { 885 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 886 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 887 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 888 <PINMUX_GPIO13__FUNC_I2S8_DI>; 889 }; 890 }; 891 892 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 893 pins-i2s9-off { 894 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 895 }; 896 }; 897 898 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 899 pins-i2s9-on { 900 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 901 }; 902 }; 903 904 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 905 pins-tdm-off { 906 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 907 <PINMUX_GPIO1__FUNC_GPIO1>, 908 <PINMUX_GPIO2__FUNC_GPIO2>, 909 <PINMUX_GPIO3__FUNC_GPIO3>; 910 }; 911 }; 912 913 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 914 pins-tdm-on { 915 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 916 <PINMUX_GPIO1__FUNC_TDM_BCK>, 917 <PINMUX_GPIO2__FUNC_TDM_MCK>, 918 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 919 }; 920 }; 921 922 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 923 pins-nle-mosi-off { 924 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 925 <PINMUX_GPIO198__FUNC_GPIO198>; 926 }; 927 }; 928 929 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 930 pins-nle-mosi-on { 931 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 932 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 933 }; 934 }; 935 936 cr50_int: cr50-irq-default-pins { 937 pins-gsc-ap-int-odl { 938 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 939 input-enable; 940 }; 941 }; 942 943 cros_ec_int: cros-ec-irq-default-pins { 944 pins-ec-ap-int-odl { 945 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 946 input-enable; 947 bias-pull-up; 948 }; 949 }; 950 951 i2c0_pins: i2c0-default-pins { 952 pins-bus { 953 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 954 <PINMUX_GPIO205__FUNC_SDA0>; 955 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 956 drive-strength-microamp = <1000>; 957 }; 958 }; 959 960 i2c1_pins: i2c1-default-pins { 961 pins-bus { 962 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 963 <PINMUX_GPIO119__FUNC_SDA1>; 964 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 965 drive-strength-microamp = <1000>; 966 }; 967 }; 968 969 i2c2_pins: i2c2-default-pins { 970 pins-bus { 971 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 972 <PINMUX_GPIO142__FUNC_SDA2>; 973 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 974 }; 975 }; 976 977 i2c3_pins: i2c3-default-pins { 978 pins-bus { 979 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 980 <PINMUX_GPIO161__FUNC_SDA3>; 981 bias-disable; 982 drive-strength-microamp = <1000>; 983 }; 984 }; 985 986 i2c7_pins: i2c7-default-pins { 987 pins-bus { 988 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 989 <PINMUX_GPIO125__FUNC_SDA7>; 990 bias-disable; 991 drive-strength-microamp = <1000>; 992 }; 993 }; 994 995 mmc0_default_pins: mmc0-default-pins { 996 pins-cmd-dat { 997 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 998 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 999 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1000 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1001 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1002 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1003 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1004 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1005 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1006 input-enable; 1007 drive-strength = <8>; 1008 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1009 }; 1010 1011 pins-clk { 1012 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1013 drive-strength = <8>; 1014 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1015 }; 1016 1017 pins-rst { 1018 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1019 drive-strength = <8>; 1020 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1021 }; 1022 }; 1023 1024 mmc0_uhs_pins: mmc0-uhs-pins { 1025 pins-cmd-dat { 1026 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1027 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1028 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1029 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1030 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1031 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1032 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1033 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1034 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1035 input-enable; 1036 drive-strength = <10>; 1037 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1038 }; 1039 1040 pins-clk { 1041 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1042 drive-strength = <10>; 1043 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1044 }; 1045 1046 pins-rst { 1047 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1048 drive-strength = <8>; 1049 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1050 }; 1051 1052 pins-ds { 1053 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1054 drive-strength = <10>; 1055 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1056 }; 1057 }; 1058 1059 mmc1_default_pins: mmc1-default-pins { 1060 pins-cmd-dat { 1061 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1062 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1063 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1064 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1065 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1066 input-enable; 1067 drive-strength = <8>; 1068 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1069 }; 1070 1071 pins-clk { 1072 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1073 drive-strength = <8>; 1074 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1075 }; 1076 1077 pins-insert { 1078 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1079 input-enable; 1080 bias-pull-up; 1081 }; 1082 }; 1083 1084 mmc1_uhs_pins: mmc1-uhs-pins { 1085 pins-cmd-dat { 1086 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1087 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1088 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1089 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1090 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1091 input-enable; 1092 drive-strength = <8>; 1093 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1094 }; 1095 1096 pins-clk { 1097 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1098 input-enable; 1099 drive-strength = <8>; 1100 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1101 }; 1102 }; 1103 1104 nor_flash_pins: nor-flash-default-pins { 1105 pins-cs-io1 { 1106 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1107 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1108 input-enable; 1109 bias-pull-up; 1110 drive-strength = <10>; 1111 }; 1112 1113 pins-io0 { 1114 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1115 bias-pull-up; 1116 drive-strength = <10>; 1117 }; 1118 1119 pins-clk { 1120 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1121 input-enable; 1122 bias-pull-up; 1123 drive-strength = <10>; 1124 }; 1125 }; 1126 1127 pcie_pins: pcie-default-pins { 1128 pins-pcie-wake { 1129 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1130 bias-pull-up; 1131 }; 1132 1133 pins-pcie-pereset { 1134 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1135 }; 1136 1137 pins-pcie-clkreq { 1138 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1139 bias-pull-up; 1140 }; 1141 1142 pins-wifi-kill { 1143 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1144 output-high; 1145 }; 1146 }; 1147 1148 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1149 pins-en { 1150 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1151 output-low; 1152 }; 1153 }; 1154 1155 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1156 pins-en { 1157 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1158 output-low; 1159 }; 1160 }; 1161 1162 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1163 pins-en { 1164 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1165 output-low; 1166 }; 1167 }; 1168 1169 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1170 pins-en { 1171 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1172 output-low; 1173 }; 1174 }; 1175 1176 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1177 pins-en { 1178 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1179 output-low; 1180 }; 1181 }; 1182 1183 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1184 pins-en { 1185 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1186 output-low; 1187 }; 1188 }; 1189 1190 pp3300_wlan_pins: pp3300-wlan-pins { 1191 pins-pcie-en-pp3300-wlan { 1192 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1193 output-high; 1194 }; 1195 }; 1196 1197 pwm0_pins: pwm0-default-pins { 1198 pins-pwm { 1199 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1200 }; 1201 1202 pins-inhibit { 1203 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1204 output-high; 1205 }; 1206 }; 1207 1208 rt1015p_pins: rt1015p-default-pins { 1209 pins { 1210 pinmux = <PINMUX_GPIO147__FUNC_GPIO147>; 1211 output-low; 1212 }; 1213 }; 1214 1215 scp_pins: scp-pins { 1216 pins-vreq-vao { 1217 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1218 }; 1219 }; 1220 1221 spi1_pins: spi1-default-pins { 1222 pins-cs-mosi-clk { 1223 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1224 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1225 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1226 bias-disable; 1227 }; 1228 1229 pins-miso { 1230 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1231 bias-pull-down; 1232 }; 1233 }; 1234 1235 spi5_pins: spi5-default-pins { 1236 pins-bus { 1237 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1238 <PINMUX_GPIO37__FUNC_GPIO37>, 1239 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1240 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1241 bias-disable; 1242 }; 1243 }; 1244 1245 trackpad_pins: trackpad-default-pins { 1246 pins-int-n { 1247 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1248 input-enable; 1249 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1250 }; 1251 }; 1252 1253 touchscreen_pins: touchscreen-default-pins { 1254 pins-irq { 1255 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1256 input-enable; 1257 bias-pull-up; 1258 }; 1259 1260 pins-reset { 1261 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1262 output-high; 1263 }; 1264 1265 pins-report-sw { 1266 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1267 output-low; 1268 }; 1269 }; 1270 1271 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1272 pins-miso-off { 1273 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1274 }; 1275 }; 1276 1277 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1278 pins-miso-on { 1279 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1280 }; 1281 }; 1282 1283 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1284 pins-miso-off { 1285 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1286 }; 1287 }; 1288 1289 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1290 pins-miso-on { 1291 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1292 }; 1293 }; 1294}; 1295 1296&pmic { 1297 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1298}; 1299 1300&pwm0 { 1301 status = "okay"; 1302 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&pwm0_pins>; 1305}; 1306 1307&scp { 1308 status = "okay"; 1309 1310 firmware-name = "mediatek/mt8192/scp.img"; 1311 memory-region = <&scp_mem_reserved>; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&scp_pins>; 1314 1315 cros-ec-rpmsg { 1316 compatible = "google,cros-ec-rpmsg"; 1317 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1318 }; 1319}; 1320 1321&spi1 { 1322 status = "okay"; 1323 1324 mediatek,pad-select = <0>; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&spi1_pins>; 1327 1328 cros_ec: ec@0 { 1329 compatible = "google,cros-ec-spi"; 1330 reg = <0>; 1331 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1332 spi-max-frequency = <3000000>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&cros_ec_int>; 1335 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 1339 base_detection: cbas { 1340 compatible = "google,cros-cbas"; 1341 }; 1342 1343 cros_ec_pwm: pwm { 1344 compatible = "google,cros-ec-pwm"; 1345 #pwm-cells = <1>; 1346 1347 status = "disabled"; 1348 }; 1349 1350 i2c_tunnel: i2c-tunnel { 1351 compatible = "google,cros-ec-i2c-tunnel"; 1352 google,remote-bus = <0>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 }; 1356 1357 mt6360_ldo3_reg: regulator@0 { 1358 compatible = "google,cros-ec-regulator"; 1359 reg = <0>; 1360 regulator-min-microvolt = <1800000>; 1361 regulator-max-microvolt = <3300000>; 1362 }; 1363 1364 mt6360_ldo5_reg: regulator@1 { 1365 compatible = "google,cros-ec-regulator"; 1366 reg = <1>; 1367 regulator-min-microvolt = <3300000>; 1368 regulator-max-microvolt = <3300000>; 1369 }; 1370 1371 typec { 1372 compatible = "google,cros-ec-typec"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 1376 usb_c0: connector@0 { 1377 compatible = "usb-c-connector"; 1378 reg = <0>; 1379 label = "left"; 1380 power-role = "dual"; 1381 data-role = "host"; 1382 try-power-role = "source"; 1383 }; 1384 1385 usb_c1: connector@1 { 1386 compatible = "usb-c-connector"; 1387 reg = <1>; 1388 label = "right"; 1389 power-role = "dual"; 1390 data-role = "host"; 1391 try-power-role = "source"; 1392 }; 1393 }; 1394 }; 1395}; 1396 1397&spi5 { 1398 status = "okay"; 1399 1400 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1401 mediatek,pad-select = <0>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&spi5_pins>; 1404 1405 tpm@0 { 1406 compatible = "google,cr50"; 1407 reg = <0>; 1408 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1409 spi-max-frequency = <1000000>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&cr50_int>; 1412 }; 1413}; 1414 1415&spmi { 1416 #address-cells = <2>; 1417 #size-cells = <0>; 1418 1419 mt6315_6: pmic@6 { 1420 compatible = "mediatek,mt6315-regulator"; 1421 reg = <0x6 SPMI_USID>; 1422 1423 regulators { 1424 mt6315_6_vbuck1: vbuck1 { 1425 regulator-compatible = "vbuck1"; 1426 regulator-name = "Vbcpu"; 1427 regulator-min-microvolt = <300000>; 1428 regulator-max-microvolt = <1193750>; 1429 regulator-enable-ramp-delay = <256>; 1430 regulator-allowed-modes = <0 1 2>; 1431 regulator-always-on; 1432 }; 1433 1434 mt6315_6_vbuck3: vbuck3 { 1435 regulator-compatible = "vbuck3"; 1436 regulator-name = "Vlcpu"; 1437 regulator-min-microvolt = <300000>; 1438 regulator-max-microvolt = <1193750>; 1439 regulator-enable-ramp-delay = <256>; 1440 regulator-allowed-modes = <0 1 2>; 1441 regulator-always-on; 1442 }; 1443 }; 1444 }; 1445 1446 mt6315_7: pmic@7 { 1447 compatible = "mediatek,mt6315-regulator"; 1448 reg = <0x7 SPMI_USID>; 1449 1450 regulators { 1451 mt6315_7_vbuck1: vbuck1 { 1452 regulator-compatible = "vbuck1"; 1453 regulator-name = "Vgpu"; 1454 regulator-min-microvolt = <606250>; 1455 regulator-max-microvolt = <800000>; 1456 regulator-enable-ramp-delay = <256>; 1457 regulator-allowed-modes = <0 1 2>; 1458 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1459 regulator-coupled-max-spread = <10000>; 1460 }; 1461 }; 1462 }; 1463}; 1464 1465&uart0 { 1466 status = "okay"; 1467}; 1468 1469&xhci { 1470 status = "okay"; 1471 1472 wakeup-source; 1473 vusb33-supply = <&pp3300_g>; 1474 vbus-supply = <&pp5000_a>; 1475}; 1476 1477#include <arm/cros-ec-keyboard.dtsi> 1478#include <arm/cros-ec-sbs.dtsi> 1479