1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&gic { 279 mediatek,broken-save-restore-fw; 280}; 281 282&gpu { 283 mali-supply = <&mt6315_7_vbuck1>; 284 status = "okay"; 285}; 286 287&i2c0 { 288 status = "okay"; 289 290 clock-frequency = <400000>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&i2c0_pins>; 293 294 touchscreen: touchscreen@10 { 295 reg = <0x10>; 296 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&touchscreen_pins>; 299 }; 300}; 301 302&i2c1 { 303 status = "okay"; 304 305 clock-frequency = <400000>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&i2c1_pins>; 308}; 309 310&i2c2 { 311 status = "okay"; 312 313 clock-frequency = <400000>; 314 clock-stretch-ns = <12600>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&i2c2_pins>; 317 318 trackpad@15 { 319 compatible = "elan,ekth3000"; 320 reg = <0x15>; 321 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&trackpad_pins>; 324 vcc-supply = <&pp3300_u>; 325 wakeup-source; 326 }; 327}; 328 329&i2c3 { 330 status = "okay"; 331 332 clock-frequency = <400000>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c3_pins>; 335 336 anx_bridge: anx7625@58 { 337 compatible = "analogix,anx7625"; 338 reg = <0x58>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&anx7625_pins>; 341 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 342 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 343 vdd10-supply = <&pp1000_mipibrdg>; 344 vdd18-supply = <&pp1800_mipibrdg>; 345 vdd33-supply = <&pp3300_mipibrdg>; 346 347 ports { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 port@0 { 352 reg = <0>; 353 354 anx7625_in: endpoint { 355 remote-endpoint = <&dsi_out>; 356 }; 357 }; 358 359 port@1 { 360 reg = <1>; 361 362 anx7625_out: endpoint { 363 remote-endpoint = <&panel_in>; 364 }; 365 }; 366 }; 367 368 aux-bus { 369 panel: panel { 370 compatible = "edp-panel"; 371 power-supply = <&pp3300_mipibrdg>; 372 backlight = <&backlight_lcd0>; 373 374 port { 375 panel_in: endpoint { 376 remote-endpoint = <&anx7625_out>; 377 }; 378 }; 379 }; 380 }; 381 }; 382}; 383 384&i2c7 { 385 status = "okay"; 386 387 clock-frequency = <400000>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&i2c7_pins>; 390}; 391 392&mfg0 { 393 domain-supply = <&mt6315_7_vbuck1>; 394}; 395 396&mfg1 { 397 domain-supply = <&mt6359_vsram_others_ldo_reg>; 398}; 399 400&mipi_tx0 { 401 status = "okay"; 402}; 403 404&mmc0 { 405 status = "okay"; 406 407 pinctrl-names = "default", "state_uhs"; 408 pinctrl-0 = <&mmc0_default_pins>; 409 pinctrl-1 = <&mmc0_uhs_pins>; 410 bus-width = <8>; 411 max-frequency = <200000000>; 412 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 413 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 414 cap-mmc-highspeed; 415 mmc-hs200-1_8v; 416 mmc-hs400-1_8v; 417 supports-cqe; 418 cap-mmc-hw-reset; 419 mmc-hs400-enhanced-strobe; 420 hs400-ds-delay = <0x12814>; 421 no-sdio; 422 no-sd; 423 non-removable; 424}; 425 426&mmc1 { 427 status = "okay"; 428 429 pinctrl-names = "default", "state_uhs"; 430 pinctrl-0 = <&mmc1_default_pins>; 431 pinctrl-1 = <&mmc1_uhs_pins>; 432 bus-width = <4>; 433 max-frequency = <200000000>; 434 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 435 vmmc-supply = <&mt6360_ldo5_reg>; 436 vqmmc-supply = <&mt6360_ldo3_reg>; 437 cap-sd-highspeed; 438 sd-uhs-sdr50; 439 sd-uhs-sdr104; 440 no-sdio; 441 no-mmc; 442}; 443 444/* for CORE */ 445&mt6359_vgpu11_buck_reg { 446 regulator-always-on; 447}; 448 449&mt6359_vgpu11_sshub_buck_reg { 450 regulator-always-on; 451 regulator-min-microvolt = <575000>; 452 regulator-max-microvolt = <575000>; 453}; 454 455&mt6359_vrf12_ldo_reg { 456 regulator-always-on; 457}; 458 459&mt6359_vsram_others_ldo_reg { 460 regulator-min-microvolt = <750000>; 461 regulator-max-microvolt = <800000>; 462 regulator-coupled-with = <&mt6315_7_vbuck1>; 463 regulator-coupled-max-spread = <10000>; 464}; 465 466&mt6359_vufs_ldo_reg { 467 regulator-always-on; 468}; 469 470&mt6359codec { 471 mediatek,dmic-mode = <1>; /* one-wire */ 472 mediatek,mic-type-0 = <2>; /* DMIC */ 473 mediatek,mic-type-2 = <2>; /* DMIC */ 474}; 475 476&nor_flash { 477 status = "okay"; 478 479 pinctrl-names = "default"; 480 pinctrl-0 = <&nor_flash_pins>; 481 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 482 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 483 484 flash@0 { 485 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 486 reg = <0>; 487 spi-max-frequency = <52000000>; 488 spi-rx-bus-width = <2>; 489 spi-tx-bus-width = <2>; 490 }; 491}; 492 493&pcie { 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pcie_pins>; 496 497 pcie0: pcie@0,0 { 498 device_type = "pci"; 499 reg = <0x0000 0 0 0 0>; 500 num-lanes = <1>; 501 bus-range = <0x1 0x1>; 502 503 #address-cells = <3>; 504 #size-cells = <2>; 505 ranges; 506 507 wifi: wifi@0,0 { 508 reg = <0x10000 0 0 0 0x100000>, 509 <0x10000 0 0x100000 0 0x100000>; 510 memory-region = <&wifi_restricted_dma_region>; 511 }; 512 }; 513}; 514 515&pio { 516 /* 220 lines */ 517 gpio-line-names = "I2S_DP_LRCK", 518 "IS_DP_BCLK", 519 "I2S_DP_MCLK", 520 "I2S_DP_DATAOUT", 521 "SAR0_INT_ODL", 522 "EC_AP_INT_ODL", 523 "EDPBRDG_INT_ODL", 524 "DPBRDG_INT_ODL", 525 "DPBRDG_PWREN", 526 "DPBRDG_RST_ODL", 527 "I2S_HP_MCLK", 528 "I2S_HP_BCK", 529 "I2S_HP_LRCK", 530 "I2S_HP_DATAIN", 531 /* 532 * AP_FLASH_WP_L is crossystem ABI. Schematics 533 * call it AP_FLASH_WP_ODL. 534 */ 535 "AP_FLASH_WP_L", 536 "TRACKPAD_INT_ODL", 537 "EC_AP_HPD_OD", 538 "SD_CD_ODL", 539 "HP_INT_ODL_ALC", 540 "EN_PP1000_DPBRDG", 541 "AP_GPIO20", 542 "TOUCH_INT_L_1V8", 543 "UART_BT_WAKE_ODL", 544 "AP_GPIO23", 545 "AP_SPI_FLASH_CS_L", 546 "AP_SPI_FLASH_CLK", 547 "EN_PP3300_DPBRDG_DX", 548 "AP_SPI_FLASH_MOSI", 549 "AP_SPI_FLASH_MISO", 550 "I2S_HP_DATAOUT", 551 "AP_GPIO30", 552 "I2S_SPKR_MCLK", 553 "I2S_SPKR_BCLK", 554 "I2S_SPKR_LRCK", 555 "I2S_SPKR_DATAIN", 556 "I2S_SPKR_DATAOUT", 557 "AP_SPI_H1_TPM_CLK", 558 "AP_SPI_H1_TPM_CS_L", 559 "AP_SPI_H1_TPM_MISO", 560 "AP_SPI_H1_TPM_MOSI", 561 "BL_PWM", 562 "EDPBRDG_PWREN", 563 "EDPBRDG_RST_ODL", 564 "EN_PP3300_HUB", 565 "HUB_RST_L", 566 "", 567 "", 568 "", 569 "", 570 "", 571 "", 572 "SD_CLK", 573 "SD_CMD", 574 "SD_DATA3", 575 "SD_DATA0", 576 "SD_DATA2", 577 "SD_DATA1", 578 "", 579 "", 580 "", 581 "", 582 "", 583 "", 584 "PCIE_WAKE_ODL", 585 "PCIE_RST_L", 586 "PCIE_CLKREQ_ODL", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "", 606 "", 607 "", 608 "", 609 "", 610 "SPMI_SCL", 611 "SPMI_SDA", 612 "AP_GOOD", 613 "UART_DBG_TX_AP_RX", 614 "UART_AP_TX_DBG_RX", 615 "UART_AP_TX_BT_RX", 616 "UART_BT_TX_AP_RX", 617 "MIPI_DPI_D0_R", 618 "MIPI_DPI_D1_R", 619 "MIPI_DPI_D2_R", 620 "MIPI_DPI_D3_R", 621 "MIPI_DPI_D4_R", 622 "MIPI_DPI_D5_R", 623 "MIPI_DPI_D6_R", 624 "MIPI_DPI_D7_R", 625 "MIPI_DPI_D8_R", 626 "MIPI_DPI_D9_R", 627 "MIPI_DPI_D10_R", 628 "", 629 "", 630 "MIPI_DPI_DE_R", 631 "MIPI_DPI_D11_R", 632 "MIPI_DPI_VSYNC_R", 633 "MIPI_DPI_CLK_R", 634 "MIPI_DPI_HSYNC_R", 635 "PCM_BT_DATAIN", 636 "PCM_BT_SYNC", 637 "PCM_BT_DATAOUT", 638 "PCM_BT_CLK", 639 "AP_I2C_AUDIO_SCL", 640 "AP_I2C_AUDIO_SDA", 641 "SCP_I2C_SCL", 642 "SCP_I2C_SDA", 643 "AP_I2C_WLAN_SCL", 644 "AP_I2C_WLAN_SDA", 645 "AP_I2C_DPBRDG_SCL", 646 "AP_I2C_DPBRDG_SDA", 647 "EN_PP1800_DPBRDG_DX", 648 "EN_PP3300_EDP_DX", 649 "EN_PP1800_EDPBRDG_DX", 650 "EN_PP1000_EDPBRDG", 651 "SCP_JTAG0_TDO", 652 "SCP_JTAG0_TDI", 653 "SCP_JTAG0_TMS", 654 "SCP_JTAG0_TCK", 655 "SCP_JTAG0_TRSTN", 656 "EN_PP3000_VMC_PMU", 657 "EN_PP3300_DISPLAY_DX", 658 "TOUCH_RST_L_1V8", 659 "TOUCH_REPORT_DISABLE", 660 "", 661 "", 662 "AP_I2C_TRACKPAD_SCL_1V8", 663 "AP_I2C_TRACKPAD_SDA_1V8", 664 "EN_PP3300_WLAN", 665 "BT_KILL_L", 666 "WIFI_KILL_L", 667 "SET_VMC_VOLT_AT_1V8", 668 "EN_SPK", 669 "AP_WARM_RST_REQ", 670 "", 671 "", 672 "EN_PP3000_SD_S3", 673 "AP_EDP_BKLTEN", 674 "", 675 "", 676 "", 677 "AP_SPI_EC_CLK", 678 "AP_SPI_EC_CS_L", 679 "AP_SPI_EC_MISO", 680 "AP_SPI_EC_MOSI", 681 "AP_I2C_EDPBRDG_SCL", 682 "AP_I2C_EDPBRDG_SDA", 683 "MT6315_PROC_INT", 684 "MT6315_GPU_INT", 685 "UART_SERVO_TX_SCP_RX", 686 "UART_SCP_TX_SERVO_RX", 687 "BT_RTS_AP_CTS", 688 "AP_RTS_BT_CTS", 689 "UART_AP_WAKE_BT_ODL", 690 "WLAN_ALERT_ODL", 691 "EC_IN_RW_ODL", 692 "H1_AP_INT_ODL", 693 "", 694 "", 695 "", 696 "", 697 "", 698 "", 699 "", 700 "", 701 "", 702 "", 703 "", 704 "MSDC0_CMD", 705 "MSDC0_DAT0", 706 "MSDC0_DAT2", 707 "MSDC0_DAT4", 708 "MSDC0_DAT6", 709 "MSDC0_DAT1", 710 "MSDC0_DAT5", 711 "MSDC0_DAT7", 712 "MSDC0_DSL", 713 "MSDC0_CLK", 714 "MSDC0_DAT3", 715 "MSDC0_RST_L", 716 "SCP_VREQ_VAO", 717 "AUD_DAT_MOSI2", 718 "AUD_NLE_MOSI1", 719 "AUD_NLE_MOSI0", 720 "AUD_DAT_MISO2", 721 "AP_I2C_SAR_SDA", 722 "AP_I2C_SAR_SCL", 723 "AP_I2C_PWR_SCL", 724 "AP_I2C_PWR_SDA", 725 "AP_I2C_TS_SCL_1V8", 726 "AP_I2C_TS_SDA_1V8", 727 "SRCLKENA0", 728 "SRCLKENA1", 729 "AP_EC_WATCHDOG_L", 730 "PWRAP_SPI0_MI", 731 "PWRAP_SPI0_CSN", 732 "PWRAP_SPI0_MO", 733 "PWRAP_SPI0_CK", 734 "AP_RTC_CLK32K", 735 "AUD_CLK_MOSI", 736 "AUD_SYNC_MOSI", 737 "AUD_DAT_MOSI0", 738 "AUD_DAT_MOSI1", 739 "AUD_DAT_MISO0", 740 "AUD_DAT_MISO1"; 741 742 anx7625_pins: anx7625-default-pins { 743 pins-out { 744 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 745 <PINMUX_GPIO42__FUNC_GPIO42>; 746 output-low; 747 }; 748 749 pins-in { 750 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 751 input-enable; 752 bias-pull-up; 753 }; 754 }; 755 756 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 757 pins-mosi-off { 758 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 759 <PINMUX_GPIO215__FUNC_GPIO215>; 760 }; 761 }; 762 763 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 764 pins-mosi-on { 765 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 766 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 767 drive-strength = <10>; 768 }; 769 }; 770 771 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 772 pins-miso-off { 773 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 774 }; 775 }; 776 777 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 778 pins-miso-on { 779 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 780 }; 781 }; 782 783 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 784 pins-miso-off { 785 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 786 <PINMUX_GPIO219__FUNC_GPIO219>; 787 }; 788 }; 789 790 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 791 pins-miso-on { 792 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 793 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 794 drive-strength = <10>; 795 }; 796 }; 797 798 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 799 pins-miso-off { 800 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 801 }; 802 }; 803 804 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 805 pins-miso-on { 806 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 807 }; 808 }; 809 810 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 811 pins-mosi-off { 812 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 813 }; 814 }; 815 816 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 817 pins-mosi-on { 818 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 819 }; 820 }; 821 822 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 823 pins-mosi-off { 824 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 825 <PINMUX_GPIO217__FUNC_GPIO217>; 826 }; 827 }; 828 829 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 830 pins-mosi-on { 831 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 832 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 833 drive-strength = <10>; 834 }; 835 }; 836 837 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 838 pins-i2s3-off { 839 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 840 <PINMUX_GPIO33__FUNC_GPIO33>, 841 <PINMUX_GPIO35__FUNC_GPIO35>; 842 }; 843 }; 844 845 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 846 pins-i2s3-on { 847 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 848 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 849 <PINMUX_GPIO35__FUNC_I2S3_DO>; 850 }; 851 }; 852 853 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 854 pins-i2s8-off { 855 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 856 <PINMUX_GPIO11__FUNC_GPIO11>, 857 <PINMUX_GPIO12__FUNC_GPIO12>, 858 <PINMUX_GPIO13__FUNC_GPIO13>; 859 }; 860 }; 861 862 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 863 pins-i2s8-on { 864 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 865 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 866 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 867 <PINMUX_GPIO13__FUNC_I2S8_DI>; 868 }; 869 }; 870 871 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 872 pins-i2s9-off { 873 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 874 }; 875 }; 876 877 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 878 pins-i2s9-on { 879 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 880 }; 881 }; 882 883 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 884 pins-tdm-off { 885 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 886 <PINMUX_GPIO1__FUNC_GPIO1>, 887 <PINMUX_GPIO2__FUNC_GPIO2>, 888 <PINMUX_GPIO3__FUNC_GPIO3>; 889 }; 890 }; 891 892 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 893 pins-tdm-on { 894 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 895 <PINMUX_GPIO1__FUNC_TDM_BCK>, 896 <PINMUX_GPIO2__FUNC_TDM_MCK>, 897 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 898 }; 899 }; 900 901 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 902 pins-nle-mosi-off { 903 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 904 <PINMUX_GPIO198__FUNC_GPIO198>; 905 }; 906 }; 907 908 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 909 pins-nle-mosi-on { 910 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 911 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 912 }; 913 }; 914 915 cr50_int: cr50-irq-default-pins { 916 pins-gsc-ap-int-odl { 917 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 918 input-enable; 919 }; 920 }; 921 922 cros_ec_int: cros-ec-irq-default-pins { 923 pins-ec-ap-int-odl { 924 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 925 input-enable; 926 bias-pull-up; 927 }; 928 }; 929 930 i2c0_pins: i2c0-default-pins { 931 pins-bus { 932 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 933 <PINMUX_GPIO205__FUNC_SDA0>; 934 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 935 drive-strength-microamp = <1000>; 936 }; 937 }; 938 939 i2c1_pins: i2c1-default-pins { 940 pins-bus { 941 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 942 <PINMUX_GPIO119__FUNC_SDA1>; 943 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 944 drive-strength-microamp = <1000>; 945 }; 946 }; 947 948 i2c2_pins: i2c2-default-pins { 949 pins-bus { 950 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 951 <PINMUX_GPIO142__FUNC_SDA2>; 952 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 953 }; 954 }; 955 956 i2c3_pins: i2c3-default-pins { 957 pins-bus { 958 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 959 <PINMUX_GPIO161__FUNC_SDA3>; 960 bias-disable; 961 drive-strength-microamp = <1000>; 962 }; 963 }; 964 965 i2c7_pins: i2c7-default-pins { 966 pins-bus { 967 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 968 <PINMUX_GPIO125__FUNC_SDA7>; 969 bias-disable; 970 drive-strength-microamp = <1000>; 971 }; 972 }; 973 974 mmc0_default_pins: mmc0-default-pins { 975 pins-cmd-dat { 976 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 977 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 978 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 979 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 980 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 981 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 982 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 983 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 984 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 985 input-enable; 986 drive-strength = <8>; 987 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 988 }; 989 990 pins-clk { 991 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 992 drive-strength = <8>; 993 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 994 }; 995 996 pins-rst { 997 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 998 drive-strength = <8>; 999 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1000 }; 1001 }; 1002 1003 mmc0_uhs_pins: mmc0-uhs-pins { 1004 pins-cmd-dat { 1005 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1006 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1007 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1008 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1009 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1010 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1011 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1012 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1013 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1014 input-enable; 1015 drive-strength = <10>; 1016 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1017 }; 1018 1019 pins-clk { 1020 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1021 drive-strength = <10>; 1022 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1023 }; 1024 1025 pins-rst { 1026 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1027 drive-strength = <8>; 1028 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1029 }; 1030 1031 pins-ds { 1032 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1033 drive-strength = <10>; 1034 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1035 }; 1036 }; 1037 1038 mmc1_default_pins: mmc1-default-pins { 1039 pins-cmd-dat { 1040 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1041 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1042 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1043 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1044 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1045 input-enable; 1046 drive-strength = <8>; 1047 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1048 }; 1049 1050 pins-clk { 1051 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1052 drive-strength = <8>; 1053 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1054 }; 1055 1056 pins-insert { 1057 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1058 input-enable; 1059 bias-pull-up; 1060 }; 1061 }; 1062 1063 mmc1_uhs_pins: mmc1-uhs-pins { 1064 pins-cmd-dat { 1065 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1066 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1067 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1068 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1069 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1070 input-enable; 1071 drive-strength = <8>; 1072 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1073 }; 1074 1075 pins-clk { 1076 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1077 input-enable; 1078 drive-strength = <8>; 1079 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1080 }; 1081 }; 1082 1083 nor_flash_pins: nor-flash-default-pins { 1084 pins-cs-io1 { 1085 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1086 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1087 input-enable; 1088 bias-pull-up; 1089 drive-strength = <10>; 1090 }; 1091 1092 pins-io0 { 1093 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1094 bias-pull-up; 1095 drive-strength = <10>; 1096 }; 1097 1098 pins-clk { 1099 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1100 input-enable; 1101 bias-pull-up; 1102 drive-strength = <10>; 1103 }; 1104 }; 1105 1106 pcie_pins: pcie-default-pins { 1107 pins-pcie-wake { 1108 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1109 bias-pull-up; 1110 }; 1111 1112 pins-pcie-pereset { 1113 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1114 }; 1115 1116 pins-pcie-clkreq { 1117 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1118 bias-pull-up; 1119 }; 1120 1121 pins-wifi-kill { 1122 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1123 output-high; 1124 }; 1125 }; 1126 1127 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1128 pins-en { 1129 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1130 output-low; 1131 }; 1132 }; 1133 1134 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1135 pins-en { 1136 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1137 output-low; 1138 }; 1139 }; 1140 1141 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1142 pins-en { 1143 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1144 output-low; 1145 }; 1146 }; 1147 1148 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1149 pins-en { 1150 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1151 output-low; 1152 }; 1153 }; 1154 1155 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1156 pins-en { 1157 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1158 output-low; 1159 }; 1160 }; 1161 1162 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1163 pins-en { 1164 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1165 output-low; 1166 }; 1167 }; 1168 1169 pp3300_wlan_pins: pp3300-wlan-pins { 1170 pins-pcie-en-pp3300-wlan { 1171 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1172 output-high; 1173 }; 1174 }; 1175 1176 pwm0_pins: pwm0-default-pins { 1177 pins-pwm { 1178 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1179 }; 1180 1181 pins-inhibit { 1182 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1183 output-high; 1184 }; 1185 }; 1186 1187 scp_pins: scp-pins { 1188 pins-vreq-vao { 1189 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1190 }; 1191 }; 1192 1193 spi1_pins: spi1-default-pins { 1194 pins-cs-mosi-clk { 1195 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1196 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1197 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1198 bias-disable; 1199 }; 1200 1201 pins-miso { 1202 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1203 bias-pull-down; 1204 }; 1205 }; 1206 1207 spi5_pins: spi5-default-pins { 1208 pins-bus { 1209 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1210 <PINMUX_GPIO37__FUNC_GPIO37>, 1211 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1212 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1213 bias-disable; 1214 }; 1215 }; 1216 1217 trackpad_pins: trackpad-default-pins { 1218 pins-int-n { 1219 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1220 input-enable; 1221 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1222 }; 1223 }; 1224 1225 touchscreen_pins: touchscreen-default-pins { 1226 pins-irq { 1227 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1228 input-enable; 1229 bias-pull-up; 1230 }; 1231 1232 pins-reset { 1233 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1234 output-high; 1235 }; 1236 1237 pins-report-sw { 1238 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1239 output-low; 1240 }; 1241 }; 1242 1243 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1244 pins-miso-off { 1245 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1246 }; 1247 }; 1248 1249 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1250 pins-miso-on { 1251 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1252 }; 1253 }; 1254 1255 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1256 pins-miso-off { 1257 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1258 }; 1259 }; 1260 1261 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1262 pins-miso-on { 1263 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1264 }; 1265 }; 1266}; 1267 1268&pmic { 1269 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1270}; 1271 1272&pwm0 { 1273 status = "okay"; 1274 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&pwm0_pins>; 1277}; 1278 1279&scp { 1280 status = "okay"; 1281 1282 firmware-name = "mediatek/mt8192/scp.img"; 1283 memory-region = <&scp_mem_reserved>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&scp_pins>; 1286 1287 cros-ec { 1288 compatible = "google,cros-ec-rpmsg"; 1289 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1290 }; 1291}; 1292 1293&spi1 { 1294 status = "okay"; 1295 1296 mediatek,pad-select = <0>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&spi1_pins>; 1299 1300 cros_ec: ec@0 { 1301 compatible = "google,cros-ec-spi"; 1302 reg = <0>; 1303 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1304 spi-max-frequency = <3000000>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&cros_ec_int>; 1307 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 1311 base_detection: cbas { 1312 compatible = "google,cros-cbas"; 1313 }; 1314 1315 cros_ec_pwm: pwm { 1316 compatible = "google,cros-ec-pwm"; 1317 #pwm-cells = <1>; 1318 1319 status = "disabled"; 1320 }; 1321 1322 i2c_tunnel: i2c-tunnel { 1323 compatible = "google,cros-ec-i2c-tunnel"; 1324 google,remote-bus = <0>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 }; 1328 1329 mt6360_ldo3_reg: regulator@0 { 1330 compatible = "google,cros-ec-regulator"; 1331 reg = <0>; 1332 regulator-min-microvolt = <1800000>; 1333 regulator-max-microvolt = <3300000>; 1334 }; 1335 1336 mt6360_ldo5_reg: regulator@1 { 1337 compatible = "google,cros-ec-regulator"; 1338 reg = <1>; 1339 regulator-min-microvolt = <3300000>; 1340 regulator-max-microvolt = <3300000>; 1341 }; 1342 1343 typec { 1344 compatible = "google,cros-ec-typec"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 1348 usb_c0: connector@0 { 1349 compatible = "usb-c-connector"; 1350 reg = <0>; 1351 label = "left"; 1352 power-role = "dual"; 1353 data-role = "host"; 1354 try-power-role = "source"; 1355 }; 1356 1357 usb_c1: connector@1 { 1358 compatible = "usb-c-connector"; 1359 reg = <1>; 1360 label = "right"; 1361 power-role = "dual"; 1362 data-role = "host"; 1363 try-power-role = "source"; 1364 }; 1365 }; 1366 }; 1367}; 1368 1369&spi5 { 1370 status = "okay"; 1371 1372 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1373 mediatek,pad-select = <0>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&spi5_pins>; 1376 1377 cr50@0 { 1378 compatible = "google,cr50"; 1379 reg = <0>; 1380 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1381 spi-max-frequency = <1000000>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&cr50_int>; 1384 }; 1385}; 1386 1387&spmi { 1388 #address-cells = <2>; 1389 #size-cells = <0>; 1390 1391 mt6315_6: pmic@6 { 1392 compatible = "mediatek,mt6315-regulator"; 1393 reg = <0x6 SPMI_USID>; 1394 1395 regulators { 1396 mt6315_6_vbuck1: vbuck1 { 1397 regulator-compatible = "vbuck1"; 1398 regulator-name = "Vbcpu"; 1399 regulator-min-microvolt = <300000>; 1400 regulator-max-microvolt = <1193750>; 1401 regulator-enable-ramp-delay = <256>; 1402 regulator-allowed-modes = <0 1 2>; 1403 regulator-always-on; 1404 }; 1405 1406 mt6315_6_vbuck3: vbuck3 { 1407 regulator-compatible = "vbuck3"; 1408 regulator-name = "Vlcpu"; 1409 regulator-min-microvolt = <300000>; 1410 regulator-max-microvolt = <1193750>; 1411 regulator-enable-ramp-delay = <256>; 1412 regulator-allowed-modes = <0 1 2>; 1413 regulator-always-on; 1414 }; 1415 }; 1416 }; 1417 1418 mt6315_7: pmic@7 { 1419 compatible = "mediatek,mt6315-regulator"; 1420 reg = <0x7 SPMI_USID>; 1421 1422 regulators { 1423 mt6315_7_vbuck1: vbuck1 { 1424 regulator-compatible = "vbuck1"; 1425 regulator-name = "Vgpu"; 1426 regulator-min-microvolt = <606250>; 1427 regulator-max-microvolt = <800000>; 1428 regulator-enable-ramp-delay = <256>; 1429 regulator-allowed-modes = <0 1 2>; 1430 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1431 regulator-coupled-max-spread = <10000>; 1432 }; 1433 }; 1434 }; 1435}; 1436 1437&uart0 { 1438 status = "okay"; 1439}; 1440 1441&xhci { 1442 status = "okay"; 1443 1444 wakeup-source; 1445 vusb33-supply = <&pp3300_g>; 1446 vbus-supply = <&pp5000_a>; 1447}; 1448 1449#include <arm/cros-ec-keyboard.dtsi> 1450#include <arm/cros-ec-sbs.dtsi> 1451