1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/interconnect/qcom,icc.h> 10#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom,rpmhpd.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 clock-frequency = <76800000>; 28 #clock-cells = <0>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 clock-frequency = <32000>; 34 #clock-cells = <0>; 35 }; 36 37 bi_tcxo_div2: bi-tcxo-div2-clk { 38 compatible = "fixed-factor-clock"; 39 #clock-cells = <0>; 40 41 clocks = <&rpmhcc RPMH_CXO_CLK>; 42 clock-mult = <1>; 43 clock-div = <2>; 44 }; 45 46 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <2>; 58 #size-cells = <0>; 59 60 CPU0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_0>; 66 power-domains = <&CPU_PD0>; 67 power-domain-names = "psci"; 68 cpu-idle-states = <&CLUSTER_C4>; 69 70 L2_0: l2-cache { 71 compatible = "cache"; 72 cache-level = <2>; 73 cache-unified; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,oryon"; 80 reg = <0x0 0x100>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 power-domains = <&CPU_PD1>; 84 power-domain-names = "psci"; 85 cpu-idle-states = <&CLUSTER_C4>; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,oryon"; 91 reg = <0x0 0x200>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_0>; 94 power-domains = <&CPU_PD2>; 95 power-domain-names = "psci"; 96 cpu-idle-states = <&CLUSTER_C4>; 97 }; 98 99 CPU3: cpu@300 { 100 device_type = "cpu"; 101 compatible = "qcom,oryon"; 102 reg = <0x0 0x300>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_0>; 105 power-domains = <&CPU_PD3>; 106 power-domain-names = "psci"; 107 cpu-idle-states = <&CLUSTER_C4>; 108 }; 109 110 CPU4: cpu@10000 { 111 device_type = "cpu"; 112 compatible = "qcom,oryon"; 113 reg = <0x0 0x10000>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_1>; 116 power-domains = <&CPU_PD4>; 117 power-domain-names = "psci"; 118 cpu-idle-states = <&CLUSTER_C4>; 119 120 L2_1: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 }; 125 }; 126 127 CPU5: cpu@10100 { 128 device_type = "cpu"; 129 compatible = "qcom,oryon"; 130 reg = <0x0 0x10100>; 131 enable-method = "psci"; 132 next-level-cache = <&L2_1>; 133 power-domains = <&CPU_PD5>; 134 power-domain-names = "psci"; 135 cpu-idle-states = <&CLUSTER_C4>; 136 }; 137 138 CPU6: cpu@10200 { 139 device_type = "cpu"; 140 compatible = "qcom,oryon"; 141 reg = <0x0 0x10200>; 142 enable-method = "psci"; 143 next-level-cache = <&L2_1>; 144 power-domains = <&CPU_PD6>; 145 power-domain-names = "psci"; 146 cpu-idle-states = <&CLUSTER_C4>; 147 }; 148 149 CPU7: cpu@10300 { 150 device_type = "cpu"; 151 compatible = "qcom,oryon"; 152 reg = <0x0 0x10300>; 153 enable-method = "psci"; 154 next-level-cache = <&L2_1>; 155 power-domains = <&CPU_PD7>; 156 power-domain-names = "psci"; 157 cpu-idle-states = <&CLUSTER_C4>; 158 }; 159 160 CPU8: cpu@20000 { 161 device_type = "cpu"; 162 compatible = "qcom,oryon"; 163 reg = <0x0 0x20000>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_2>; 166 power-domains = <&CPU_PD8>; 167 power-domain-names = "psci"; 168 cpu-idle-states = <&CLUSTER_C4>; 169 170 L2_2: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 }; 175 }; 176 177 CPU9: cpu@20100 { 178 device_type = "cpu"; 179 compatible = "qcom,oryon"; 180 reg = <0x0 0x20100>; 181 enable-method = "psci"; 182 next-level-cache = <&L2_2>; 183 power-domains = <&CPU_PD9>; 184 power-domain-names = "psci"; 185 cpu-idle-states = <&CLUSTER_C4>; 186 }; 187 188 CPU10: cpu@20200 { 189 device_type = "cpu"; 190 compatible = "qcom,oryon"; 191 reg = <0x0 0x20200>; 192 enable-method = "psci"; 193 next-level-cache = <&L2_2>; 194 power-domains = <&CPU_PD10>; 195 power-domain-names = "psci"; 196 cpu-idle-states = <&CLUSTER_C4>; 197 }; 198 199 CPU11: cpu@20300 { 200 device_type = "cpu"; 201 compatible = "qcom,oryon"; 202 reg = <0x0 0x20300>; 203 enable-method = "psci"; 204 next-level-cache = <&L2_2>; 205 power-domains = <&CPU_PD11>; 206 power-domain-names = "psci"; 207 cpu-idle-states = <&CLUSTER_C4>; 208 }; 209 210 cpu-map { 211 cluster0 { 212 core0 { 213 cpu = <&CPU0>; 214 }; 215 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 220 core2 { 221 cpu = <&CPU2>; 222 }; 223 224 core3 { 225 cpu = <&CPU3>; 226 }; 227 }; 228 229 cluster1 { 230 core0 { 231 cpu = <&CPU4>; 232 }; 233 234 core1 { 235 cpu = <&CPU5>; 236 }; 237 238 core2 { 239 cpu = <&CPU6>; 240 }; 241 242 core3 { 243 cpu = <&CPU7>; 244 }; 245 }; 246 247 cluster2 { 248 core0 { 249 cpu = <&CPU8>; 250 }; 251 252 core1 { 253 cpu = <&CPU9>; 254 }; 255 256 core2 { 257 cpu = <&CPU10>; 258 }; 259 260 core3 { 261 cpu = <&CPU11>; 262 }; 263 }; 264 }; 265 266 idle-states { 267 entry-method = "psci"; 268 269 CLUSTER_C4: cpu-sleep-0 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "ret"; 272 arm,psci-suspend-param = <0x00000004>; 273 entry-latency-us = <180>; 274 exit-latency-us = <320>; 275 min-residency-us = <1000>; 276 }; 277 }; 278 279 domain-idle-states { 280 CLUSTER_CL4: cluster-sleep-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "l2-ret"; 283 arm,psci-suspend-param = <0x01000044>; 284 entry-latency-us = <350>; 285 exit-latency-us = <500>; 286 min-residency-us = <2500>; 287 }; 288 289 CLUSTER_CL5: cluster-sleep-1 { 290 compatible = "arm,idle-state"; 291 idle-state-name = "ret-pll-off"; 292 arm,psci-suspend-param = <0x01000054>; 293 entry-latency-us = <2200>; 294 exit-latency-us = <2500>; 295 min-residency-us = <7000>; 296 }; 297 }; 298 }; 299 300 firmware { 301 scm: scm { 302 compatible = "qcom,scm-x1e80100", "qcom,scm"; 303 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 304 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 305 }; 306 }; 307 308 clk_virt: interconnect-0 { 309 compatible = "qcom,x1e80100-clk-virt"; 310 #interconnect-cells = <2>; 311 qcom,bcm-voters = <&apps_bcm_voter>; 312 }; 313 314 mc_virt: interconnect-1 { 315 compatible = "qcom,x1e80100-mc-virt"; 316 #interconnect-cells = <2>; 317 qcom,bcm-voters = <&apps_bcm_voter>; 318 }; 319 320 memory@80000000 { 321 device_type = "memory"; 322 /* We expect the bootloader to fill in the size */ 323 reg = <0 0x80000000 0 0>; 324 }; 325 326 pmu { 327 compatible = "arm,armv8-pmuv3"; 328 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 329 }; 330 331 psci { 332 compatible = "arm,psci-1.0"; 333 method = "smc"; 334 335 CPU_PD0: power-domain-cpu0 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD0>; 338 }; 339 340 CPU_PD1: power-domain-cpu1 { 341 #power-domain-cells = <0>; 342 power-domains = <&CLUSTER_PD0>; 343 }; 344 345 CPU_PD2: power-domain-cpu2 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_PD0>; 348 }; 349 350 CPU_PD3: power-domain-cpu3 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD0>; 353 }; 354 355 CPU_PD4: power-domain-cpu4 { 356 #power-domain-cells = <0>; 357 power-domains = <&CLUSTER_PD1>; 358 }; 359 360 CPU_PD5: power-domain-cpu5 { 361 #power-domain-cells = <0>; 362 power-domains = <&CLUSTER_PD1>; 363 }; 364 365 CPU_PD6: power-domain-cpu6 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD1>; 368 }; 369 370 CPU_PD7: power-domain-cpu7 { 371 #power-domain-cells = <0>; 372 power-domains = <&CLUSTER_PD1>; 373 }; 374 375 CPU_PD8: power-domain-cpu8 { 376 #power-domain-cells = <0>; 377 power-domains = <&CLUSTER_PD2>; 378 }; 379 380 CPU_PD9: power-domain-cpu9 { 381 #power-domain-cells = <0>; 382 power-domains = <&CLUSTER_PD2>; 383 }; 384 385 CPU_PD10: power-domain-cpu10 { 386 #power-domain-cells = <0>; 387 power-domains = <&CLUSTER_PD2>; 388 }; 389 390 CPU_PD11: power-domain-cpu11 { 391 #power-domain-cells = <0>; 392 power-domains = <&CLUSTER_PD2>; 393 }; 394 395 CLUSTER_PD0: power-domain-cpu-cluster0 { 396 #power-domain-cells = <0>; 397 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 398 }; 399 400 CLUSTER_PD1: power-domain-cpu-cluster1 { 401 #power-domain-cells = <0>; 402 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 403 }; 404 405 CLUSTER_PD2: power-domain-cpu-cluster2 { 406 #power-domain-cells = <0>; 407 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 408 }; 409 }; 410 411 reserved-memory { 412 #address-cells = <2>; 413 #size-cells = <2>; 414 ranges; 415 416 gunyah_hyp_mem: gunyah-hyp@80000000 { 417 reg = <0x0 0x80000000 0x0 0x800000>; 418 no-map; 419 }; 420 421 hyp_elf_package_mem: hyp-elf-package@80800000 { 422 reg = <0x0 0x80800000 0x0 0x200000>; 423 no-map; 424 }; 425 426 ncc_mem: ncc@80a00000 { 427 reg = <0x0 0x80a00000 0x0 0x400000>; 428 no-map; 429 }; 430 431 cpucp_log_mem: cpucp-log@80e00000 { 432 reg = <0x0 0x80e00000 0x0 0x40000>; 433 no-map; 434 }; 435 436 cpucp_mem: cpucp@80e40000 { 437 reg = <0x0 0x80e40000 0x0 0x540000>; 438 no-map; 439 }; 440 441 reserved-region@81380000 { 442 reg = <0x0 0x81380000 0x0 0x80000>; 443 no-map; 444 }; 445 446 tags_mem: tags-region@81400000 { 447 reg = <0x0 0x81400000 0x0 0x1a0000>; 448 no-map; 449 }; 450 451 xbl_dtlog_mem: xbl-dtlog@81a00000 { 452 reg = <0x0 0x81a00000 0x0 0x40000>; 453 no-map; 454 }; 455 456 xbl_ramdump_mem: xbl-ramdump@81a40000 { 457 reg = <0x0 0x81a40000 0x0 0x1c0000>; 458 no-map; 459 }; 460 461 aop_image_mem: aop-image@81c00000 { 462 reg = <0x0 0x81c00000 0x0 0x60000>; 463 no-map; 464 }; 465 466 aop_cmd_db_mem: aop-cmd-db@81c60000 { 467 compatible = "qcom,cmd-db"; 468 reg = <0x0 0x81c60000 0x0 0x20000>; 469 no-map; 470 }; 471 472 aop_config_mem: aop-config@81c80000 { 473 reg = <0x0 0x81c80000 0x0 0x20000>; 474 no-map; 475 }; 476 477 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 478 reg = <0x0 0x81ca0000 0x0 0x40000>; 479 no-map; 480 }; 481 482 tme_log_mem: tme-log@81ce0000 { 483 reg = <0x0 0x81ce0000 0x0 0x4000>; 484 no-map; 485 }; 486 487 uefi_log_mem: uefi-log@81ce4000 { 488 reg = <0x0 0x81ce4000 0x0 0x10000>; 489 no-map; 490 }; 491 492 secdata_apss_mem: secdata-apss@81cff000 { 493 reg = <0x0 0x81cff000 0x0 0x1000>; 494 no-map; 495 }; 496 497 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 498 reg = <0x0 0x81e00000 0x0 0x100000>; 499 no-map; 500 }; 501 502 gpu_prr_mem: gpu-prr@81f00000 { 503 reg = <0x0 0x81f00000 0x0 0x10000>; 504 no-map; 505 }; 506 507 tpm_control_mem: tpm-control@81f10000 { 508 reg = <0x0 0x81f10000 0x0 0x10000>; 509 no-map; 510 }; 511 512 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 513 reg = <0x0 0x81f20000 0x0 0x10000>; 514 no-map; 515 }; 516 517 pld_pep_mem: pld-pep@81f30000 { 518 reg = <0x0 0x81f30000 0x0 0x6000>; 519 no-map; 520 }; 521 522 pld_gmu_mem: pld-gmu@81f36000 { 523 reg = <0x0 0x81f36000 0x0 0x1000>; 524 no-map; 525 }; 526 527 pld_pdp_mem: pld-pdp@81f37000 { 528 reg = <0x0 0x81f37000 0x0 0x1000>; 529 no-map; 530 }; 531 532 tz_stat_mem: tz-stat@82700000 { 533 reg = <0x0 0x82700000 0x0 0x100000>; 534 no-map; 535 }; 536 537 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 538 reg = <0x0 0x82800000 0x0 0xc00000>; 539 no-map; 540 }; 541 542 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 543 reg = <0x0 0x84b00000 0x0 0x800000>; 544 no-map; 545 }; 546 547 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 548 reg = <0x0 0x85300000 0x0 0x80000>; 549 no-map; 550 }; 551 552 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 553 reg = <0x0 0x866c0000 0x0 0x40000>; 554 no-map; 555 }; 556 557 spss_region_mem: spss-region@86700000 { 558 reg = <0x0 0x86700000 0x0 0x400000>; 559 no-map; 560 }; 561 562 adsp_boot_mem: adsp-boot@86b00000 { 563 reg = <0x0 0x86b00000 0x0 0xc00000>; 564 no-map; 565 }; 566 567 video_mem: video@87700000 { 568 reg = <0x0 0x87700000 0x0 0x700000>; 569 no-map; 570 }; 571 572 adspslpi_mem: adspslpi@87e00000 { 573 reg = <0x0 0x87e00000 0x0 0x3a00000>; 574 no-map; 575 }; 576 577 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 578 reg = <0x0 0x8b800000 0x0 0x80000>; 579 no-map; 580 }; 581 582 cdsp_mem: cdsp@8b900000 { 583 reg = <0x0 0x8b900000 0x0 0x2000000>; 584 no-map; 585 }; 586 587 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 588 reg = <0x0 0x8d900000 0x0 0x80000>; 589 no-map; 590 }; 591 592 gpu_microcode_mem: gpu-microcode@8d9fe000 { 593 reg = <0x0 0x8d9fe000 0x0 0x2000>; 594 no-map; 595 }; 596 597 cvp_mem: cvp@8da00000 { 598 reg = <0x0 0x8da00000 0x0 0x700000>; 599 no-map; 600 }; 601 602 camera_mem: camera@8e100000 { 603 reg = <0x0 0x8e100000 0x0 0x800000>; 604 no-map; 605 }; 606 607 av1_encoder_mem: av1-encoder@8e900000 { 608 reg = <0x0 0x8e900000 0x0 0x700000>; 609 no-map; 610 }; 611 612 reserved-region@8f000000 { 613 reg = <0x0 0x8f000000 0x0 0xa00000>; 614 no-map; 615 }; 616 617 wpss_mem: wpss@8fa00000 { 618 reg = <0x0 0x8fa00000 0x0 0x1900000>; 619 no-map; 620 }; 621 622 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 623 reg = <0x0 0x91300000 0x0 0x80000>; 624 no-map; 625 }; 626 627 xbl_sc_mem: xbl-sc@d8000000 { 628 reg = <0x0 0xd8000000 0x0 0x40000>; 629 no-map; 630 }; 631 632 reserved-region@d8040000 { 633 reg = <0x0 0xd8040000 0x0 0xa0000>; 634 no-map; 635 }; 636 637 qtee_mem: qtee@d80e0000 { 638 reg = <0x0 0xd80e0000 0x0 0x520000>; 639 no-map; 640 }; 641 642 ta_mem: ta@d8600000 { 643 reg = <0x0 0xd8600000 0x0 0x8a00000>; 644 no-map; 645 }; 646 647 tags_mem1: tags@e1000000 { 648 reg = <0x0 0xe1000000 0x0 0x26a0000>; 649 no-map; 650 }; 651 652 llcc_lpi_mem: llcc-lpi@ff800000 { 653 reg = <0x0 0xff800000 0x0 0x600000>; 654 no-map; 655 }; 656 657 smem_mem: smem@ffe00000 { 658 compatible = "qcom,smem"; 659 reg = <0x0 0xffe00000 0x0 0x200000>; 660 hwlocks = <&tcsr_mutex 3>; 661 no-map; 662 }; 663 }; 664 665 soc: soc@0 { 666 compatible = "simple-bus"; 667 668 #address-cells = <2>; 669 #size-cells = <2>; 670 dma-ranges = <0 0 0 0 0x10 0>; 671 ranges = <0 0 0 0 0x10 0>; 672 673 gcc: clock-controller@100000 { 674 compatible = "qcom,x1e80100-gcc"; 675 reg = <0 0x00100000 0 0x200000>; 676 677 clocks = <&bi_tcxo_div2>, 678 <&sleep_clk>, 679 <0>, 680 <0>, 681 <0>, 682 <0>, 683 <0>, 684 <0>, 685 <0>, 686 <0>; 687 688 power-domains = <&rpmhpd RPMHPD_CX>; 689 #clock-cells = <1>; 690 #reset-cells = <1>; 691 #power-domain-cells = <1>; 692 }; 693 694 gpi_dma2: dma-controller@800000 { 695 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 696 reg = <0 0x00800000 0 0x60000>; 697 698 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 710 711 dma-channels = <12>; 712 dma-channel-mask = <0x3e>; 713 #dma-cells = <3>; 714 715 iommus = <&apps_smmu 0x436 0x0>; 716 717 status = "disabled"; 718 }; 719 720 qupv3_2: geniqup@8c0000 { 721 compatible = "qcom,geni-se-qup"; 722 reg = <0 0x008c0000 0 0x2000>; 723 724 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 725 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 726 clock-names = "m-ahb", 727 "s-ahb"; 728 729 iommus = <&apps_smmu 0x423 0x0>; 730 731 #address-cells = <2>; 732 #size-cells = <2>; 733 ranges; 734 735 status = "disabled"; 736 737 i2c16: i2c@880000 { 738 compatible = "qcom,geni-i2c"; 739 reg = <0 0x00880000 0 0x4000>; 740 741 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 742 743 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 744 clock-names = "se"; 745 746 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 747 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 748 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 749 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 750 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 752 interconnect-names = "qup-core", 753 "qup-config", 754 "qup-memory"; 755 756 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 757 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 758 dma-names = "tx", 759 "rx"; 760 761 pinctrl-0 = <&qup_i2c16_data_clk>; 762 pinctrl-names = "default"; 763 764 #address-cells = <1>; 765 #size-cells = <0>; 766 767 status = "disabled"; 768 }; 769 770 spi16: spi@880000 { 771 compatible = "qcom,geni-spi"; 772 reg = <0 0x00880000 0 0x4000>; 773 774 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 775 776 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 777 clock-names = "se"; 778 779 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 780 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 781 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 782 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 783 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 784 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 785 interconnect-names = "qup-core", 786 "qup-config", 787 "qup-memory"; 788 789 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 790 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 791 dma-names = "tx", 792 "rx"; 793 794 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 795 pinctrl-names = "default"; 796 797 #address-cells = <1>; 798 #size-cells = <0>; 799 800 status = "disabled"; 801 }; 802 803 i2c17: i2c@884000 { 804 compatible = "qcom,geni-i2c"; 805 reg = <0 0x00884000 0 0x4000>; 806 807 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 808 809 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 810 clock-names = "se"; 811 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 813 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 814 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 815 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 816 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 817 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 818 interconnect-names = "qup-core", 819 "qup-config", 820 "qup-memory"; 821 822 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 824 dma-names = "tx", 825 "rx"; 826 827 pinctrl-0 = <&qup_i2c17_data_clk>; 828 pinctrl-names = "default"; 829 830 #address-cells = <1>; 831 #size-cells = <0>; 832 833 status = "disabled"; 834 }; 835 836 spi17: spi@884000 { 837 compatible = "qcom,geni-spi"; 838 reg = <0 0x00884000 0 0x4000>; 839 840 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 841 842 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 843 clock-names = "se"; 844 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 846 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 847 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 848 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 849 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 850 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 851 interconnect-names = "qup-core", 852 "qup-config", 853 "qup-memory"; 854 855 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 856 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 857 dma-names = "tx", 858 "rx"; 859 860 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 861 pinctrl-names = "default"; 862 863 #address-cells = <1>; 864 #size-cells = <0>; 865 866 status = "disabled"; 867 }; 868 869 i2c18: i2c@888000 { 870 compatible = "qcom,geni-i2c"; 871 reg = <0 0x00888000 0 0x4000>; 872 873 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 874 875 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 876 clock-names = "se"; 877 878 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 879 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 880 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 881 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 882 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 884 interconnect-names = "qup-core", 885 "qup-config", 886 "qup-memory"; 887 888 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 889 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 890 dma-names = "tx", 891 "rx"; 892 893 pinctrl-0 = <&qup_i2c18_data_clk>; 894 pinctrl-names = "default"; 895 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 status = "disabled"; 900 }; 901 902 spi18: spi@888000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0 0x00888000 0 0x4000>; 905 906 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 907 908 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 909 clock-names = "se"; 910 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 912 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 914 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 915 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 917 interconnect-names = "qup-core", 918 "qup-config", 919 "qup-memory"; 920 921 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 922 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 923 dma-names = "tx", 924 "rx"; 925 926 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 927 pinctrl-names = "default"; 928 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 status = "disabled"; 933 }; 934 935 i2c19: i2c@88c000 { 936 compatible = "qcom,geni-i2c"; 937 reg = <0 0x0088c000 0 0x4000>; 938 939 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 940 941 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 942 clock-names = "se"; 943 944 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 945 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 947 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 948 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 949 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 950 interconnect-names = "qup-core", 951 "qup-config", 952 "qup-memory"; 953 954 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 956 dma-names = "tx", 957 "rx"; 958 959 pinctrl-0 = <&qup_i2c19_data_clk>; 960 pinctrl-names = "default"; 961 962 #address-cells = <1>; 963 #size-cells = <0>; 964 965 status = "disabled"; 966 }; 967 968 spi19: spi@88c000 { 969 compatible = "qcom,geni-spi"; 970 reg = <0 0x0088c000 0 0x4000>; 971 972 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 973 974 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 975 clock-names = "se"; 976 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 978 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 980 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 981 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 983 interconnect-names = "qup-core", 984 "qup-config", 985 "qup-memory"; 986 987 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 988 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 989 dma-names = "tx", 990 "rx"; 991 992 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 993 pinctrl-names = "default"; 994 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 status = "disabled"; 999 }; 1000 1001 i2c20: i2c@890000 { 1002 compatible = "qcom,geni-i2c"; 1003 reg = <0 0x00890000 0 0x4000>; 1004 1005 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1006 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1008 clock-names = "se"; 1009 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1011 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1012 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1013 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1014 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1015 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1016 interconnect-names = "qup-core", 1017 "qup-config", 1018 "qup-memory"; 1019 1020 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1021 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1022 dma-names = "tx", 1023 "rx"; 1024 1025 pinctrl-0 = <&qup_i2c20_data_clk>; 1026 pinctrl-names = "default"; 1027 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 1031 status = "disabled"; 1032 }; 1033 1034 spi20: spi@890000 { 1035 compatible = "qcom,geni-spi"; 1036 reg = <0 0x00890000 0 0x4000>; 1037 1038 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1039 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1041 clock-names = "se"; 1042 1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1044 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1045 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1046 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1047 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1049 interconnect-names = "qup-core", 1050 "qup-config", 1051 "qup-memory"; 1052 1053 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1054 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1055 dma-names = "tx", 1056 "rx"; 1057 1058 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1059 pinctrl-names = "default"; 1060 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 status = "disabled"; 1065 }; 1066 1067 i2c21: i2c@894000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x00894000 0 0x4000>; 1070 1071 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1072 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1074 clock-names = "se"; 1075 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1077 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1079 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1080 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1082 interconnect-names = "qup-core", 1083 "qup-config", 1084 "qup-memory"; 1085 1086 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1087 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1088 dma-names = "tx", 1089 "rx"; 1090 1091 pinctrl-0 = <&qup_i2c21_data_clk>; 1092 pinctrl-names = "default"; 1093 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 status = "disabled"; 1098 }; 1099 1100 spi21: spi@894000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00894000 0 0x4000>; 1103 1104 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1105 1106 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1107 clock-names = "se"; 1108 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1110 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1111 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1112 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1113 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1115 interconnect-names = "qup-core", 1116 "qup-config", 1117 "qup-memory"; 1118 1119 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1120 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1121 dma-names = "tx", 1122 "rx"; 1123 1124 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1125 pinctrl-names = "default"; 1126 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 1130 status = "disabled"; 1131 }; 1132 1133 uart21: serial@894000 { 1134 compatible = "qcom,geni-uart"; 1135 reg = <0 0x00894000 0 0x4000>; 1136 1137 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1138 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1140 clock-names = "se"; 1141 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1143 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1145 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1146 interconnect-names = "qup-core", 1147 "qup-config"; 1148 1149 pinctrl-0 = <&qup_uart21_default>; 1150 pinctrl-names = "default"; 1151 1152 status = "disabled"; 1153 }; 1154 1155 i2c22: i2c@898000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x00898000 0 0x4000>; 1158 1159 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1160 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1162 clock-names = "se"; 1163 1164 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1165 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1166 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1167 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1168 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1170 interconnect-names = "qup-core", 1171 "qup-config", 1172 "qup-memory"; 1173 1174 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1175 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1176 dma-names = "tx", 1177 "rx"; 1178 1179 pinctrl-0 = <&qup_i2c22_data_clk>; 1180 pinctrl-names = "default"; 1181 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 1185 status = "disabled"; 1186 }; 1187 1188 spi22: spi@898000 { 1189 compatible = "qcom,geni-spi"; 1190 reg = <0 0x00898000 0 0x4000>; 1191 1192 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1193 1194 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1195 clock-names = "se"; 1196 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1201 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", 1204 "qup-config", 1205 "qup-memory"; 1206 1207 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1208 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1209 dma-names = "tx", 1210 "rx"; 1211 1212 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1213 pinctrl-names = "default"; 1214 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 1218 status = "disabled"; 1219 }; 1220 1221 i2c23: i2c@89c000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x0089c000 0 0x4000>; 1224 1225 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1226 1227 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1228 clock-names = "se"; 1229 1230 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1231 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1232 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1233 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1234 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1235 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1236 interconnect-names = "qup-core", 1237 "qup-config", 1238 "qup-memory"; 1239 1240 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1241 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1242 dma-names = "tx", 1243 "rx"; 1244 1245 pinctrl-0 = <&qup_i2c23_data_clk>; 1246 pinctrl-names = "default"; 1247 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 1251 status = "disabled"; 1252 }; 1253 1254 spi23: spi@89c000 { 1255 compatible = "qcom,geni-spi"; 1256 reg = <0 0x0089c000 0 0x4000>; 1257 1258 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1259 1260 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1261 clock-names = "se"; 1262 1263 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1266 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1267 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1269 interconnect-names = "qup-core", 1270 "qup-config", 1271 "qup-memory"; 1272 1273 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1274 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1275 dma-names = "tx", 1276 "rx"; 1277 1278 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1279 pinctrl-names = "default"; 1280 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 status = "disabled"; 1285 }; 1286 }; 1287 1288 gpi_dma1: dma-controller@a00000 { 1289 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1290 reg = <0 0x00a00000 0 0x60000>; 1291 1292 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1304 1305 dma-channels = <12>; 1306 dma-channel-mask = <0x3e>; 1307 #dma-cells = <3>; 1308 1309 iommus = <&apps_smmu 0x136 0x0>; 1310 1311 status = "disabled"; 1312 }; 1313 1314 qupv3_1: geniqup@ac0000 { 1315 compatible = "qcom,geni-se-qup"; 1316 reg = <0 0x00ac0000 0 0x2000>; 1317 1318 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1319 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1320 clock-names = "m-ahb", 1321 "s-ahb"; 1322 1323 iommus = <&apps_smmu 0x123 0x0>; 1324 1325 #address-cells = <2>; 1326 #size-cells = <2>; 1327 ranges; 1328 1329 status = "disabled"; 1330 1331 i2c8: i2c@a80000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00a80000 0 0x4000>; 1334 1335 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1336 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1338 clock-names = "se"; 1339 1340 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1343 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1344 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1346 interconnect-names = "qup-core", 1347 "qup-config", 1348 "qup-memory"; 1349 1350 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1351 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1352 dma-names = "tx", 1353 "rx"; 1354 1355 pinctrl-0 = <&qup_i2c8_data_clk>; 1356 pinctrl-names = "default"; 1357 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 1361 status = "disabled"; 1362 }; 1363 1364 spi8: spi@a80000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0 0x00a80000 0 0x4000>; 1367 1368 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1369 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1371 clock-names = "se"; 1372 1373 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1374 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1376 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1377 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1379 interconnect-names = "qup-core", 1380 "qup-config", 1381 "qup-memory"; 1382 1383 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1384 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1385 dma-names = "tx", 1386 "rx"; 1387 1388 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1389 pinctrl-names = "default"; 1390 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 1394 status = "disabled"; 1395 }; 1396 1397 i2c9: i2c@a84000 { 1398 compatible = "qcom,geni-i2c"; 1399 reg = <0 0x00a84000 0 0x4000>; 1400 1401 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1402 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1404 clock-names = "se"; 1405 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1407 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1409 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1410 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1412 interconnect-names = "qup-core", 1413 "qup-config", 1414 "qup-memory"; 1415 1416 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1417 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1418 dma-names = "tx", 1419 "rx"; 1420 1421 pinctrl-0 = <&qup_i2c9_data_clk>; 1422 pinctrl-names = "default"; 1423 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 1427 status = "disabled"; 1428 }; 1429 1430 spi9: spi@a84000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00a84000 0 0x4000>; 1433 1434 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1435 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1437 clock-names = "se"; 1438 1439 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1440 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1442 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1443 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1444 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1445 interconnect-names = "qup-core", 1446 "qup-config", 1447 "qup-memory"; 1448 1449 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1450 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1451 dma-names = "tx", 1452 "rx"; 1453 1454 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1455 pinctrl-names = "default"; 1456 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 1460 status = "disabled"; 1461 }; 1462 1463 i2c10: i2c@a88000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0 0x00a88000 0 0x4000>; 1466 1467 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1468 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1470 clock-names = "se"; 1471 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1473 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1474 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1475 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1476 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1477 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1478 interconnect-names = "qup-core", 1479 "qup-config", 1480 "qup-memory"; 1481 1482 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1483 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1484 dma-names = "tx", 1485 "rx"; 1486 1487 pinctrl-0 = <&qup_i2c10_data_clk>; 1488 pinctrl-names = "default"; 1489 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 1493 status = "disabled"; 1494 }; 1495 1496 spi10: spi@a88000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00a88000 0 0x4000>; 1499 1500 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1501 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1503 clock-names = "se"; 1504 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1506 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1507 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1508 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1509 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1510 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1511 interconnect-names = "qup-core", 1512 "qup-config", 1513 "qup-memory"; 1514 1515 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1516 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1517 dma-names = "tx", 1518 "rx"; 1519 1520 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1521 pinctrl-names = "default"; 1522 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 1526 status = "disabled"; 1527 }; 1528 1529 i2c11: i2c@a8c000 { 1530 compatible = "qcom,geni-i2c"; 1531 reg = <0 0x00a8c000 0 0x4000>; 1532 1533 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1534 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1536 clock-names = "se"; 1537 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1539 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1541 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1542 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1544 interconnect-names = "qup-core", 1545 "qup-config", 1546 "qup-memory"; 1547 1548 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1549 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1550 dma-names = "tx", 1551 "rx"; 1552 1553 pinctrl-0 = <&qup_i2c11_data_clk>; 1554 pinctrl-names = "default"; 1555 1556 #address-cells = <1>; 1557 #size-cells = <0>; 1558 1559 status = "disabled"; 1560 }; 1561 1562 spi11: spi@a8c000 { 1563 compatible = "qcom,geni-spi"; 1564 reg = <0 0x00a8c000 0 0x4000>; 1565 1566 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1567 1568 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1569 clock-names = "se"; 1570 1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1572 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1573 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1574 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1575 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1576 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1577 interconnect-names = "qup-core", 1578 "qup-config", 1579 "qup-memory"; 1580 1581 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1582 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1583 dma-names = "tx", 1584 "rx"; 1585 1586 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1587 pinctrl-names = "default"; 1588 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 status = "disabled"; 1593 }; 1594 1595 i2c12: i2c@a90000 { 1596 compatible = "qcom,geni-i2c"; 1597 reg = <0 0x00a90000 0 0x4000>; 1598 1599 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1600 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1602 clock-names = "se"; 1603 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1608 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1610 interconnect-names = "qup-core", 1611 "qup-config", 1612 "qup-memory"; 1613 1614 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1615 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1616 dma-names = "tx", 1617 "rx"; 1618 1619 pinctrl-0 = <&qup_i2c12_data_clk>; 1620 pinctrl-names = "default"; 1621 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 1625 status = "disabled"; 1626 }; 1627 1628 spi12: spi@a90000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00a90000 0 0x4000>; 1631 1632 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1633 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1635 clock-names = "se"; 1636 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1638 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1640 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1641 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1643 interconnect-names = "qup-core", 1644 "qup-config", 1645 "qup-memory"; 1646 1647 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1648 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1649 dma-names = "tx", 1650 "rx"; 1651 1652 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1653 pinctrl-names = "default"; 1654 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 1658 status = "disabled"; 1659 }; 1660 1661 i2c13: i2c@a94000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a94000 0 0x4000>; 1664 1665 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1666 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1668 clock-names = "se"; 1669 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1671 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1672 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1673 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1674 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1676 interconnect-names = "qup-core", 1677 "qup-config", 1678 "qup-memory"; 1679 1680 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1681 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1682 dma-names = "tx", 1683 "rx"; 1684 1685 pinctrl-0 = <&qup_i2c13_data_clk>; 1686 pinctrl-names = "default"; 1687 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 1691 status = "disabled"; 1692 }; 1693 1694 spi13: spi@a94000 { 1695 compatible = "qcom,geni-spi"; 1696 reg = <0 0x00a94000 0 0x4000>; 1697 1698 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1699 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1701 clock-names = "se"; 1702 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1704 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1705 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1706 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1707 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1708 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1709 interconnect-names = "qup-core", 1710 "qup-config", 1711 "qup-memory"; 1712 1713 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1714 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1715 dma-names = "tx", 1716 "rx"; 1717 1718 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1719 pinctrl-names = "default"; 1720 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 status = "disabled"; 1725 }; 1726 1727 i2c14: i2c@a98000 { 1728 compatible = "qcom,geni-i2c"; 1729 reg = <0 0x00a98000 0 0x4000>; 1730 1731 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1732 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1734 clock-names = "se"; 1735 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1737 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1739 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1740 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1741 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1742 interconnect-names = "qup-core", 1743 "qup-config", 1744 "qup-memory"; 1745 1746 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1747 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1748 dma-names = "tx", 1749 "rx"; 1750 1751 pinctrl-0 = <&qup_i2c14_data_clk>; 1752 pinctrl-names = "default"; 1753 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 1757 status = "disabled"; 1758 }; 1759 1760 spi14: spi@a98000 { 1761 compatible = "qcom,geni-spi"; 1762 reg = <0 0x00a98000 0 0x4000>; 1763 1764 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1765 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1767 clock-names = "se"; 1768 1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1770 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1772 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1773 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1775 interconnect-names = "qup-core", 1776 "qup-config", 1777 "qup-memory"; 1778 1779 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1781 dma-names = "tx", 1782 "rx"; 1783 1784 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1785 pinctrl-names = "default"; 1786 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 1790 status = "disabled"; 1791 }; 1792 1793 i2c15: i2c@a9c000 { 1794 compatible = "qcom,geni-i2c"; 1795 reg = <0 0x00a9c000 0 0x4000>; 1796 1797 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1798 1799 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1800 clock-names = "se"; 1801 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1803 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1804 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1805 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1806 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1807 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1808 interconnect-names = "qup-core", 1809 "qup-config", 1810 "qup-memory"; 1811 1812 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1813 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1814 dma-names = "tx", 1815 "rx"; 1816 1817 pinctrl-0 = <&qup_i2c15_data_clk>; 1818 pinctrl-names = "default"; 1819 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 1823 status = "disabled"; 1824 }; 1825 1826 spi15: spi@a9c000 { 1827 compatible = "qcom,geni-spi"; 1828 reg = <0 0x00a9c000 0 0x4000>; 1829 1830 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1831 1832 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1833 clock-names = "se"; 1834 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1836 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1837 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1838 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1839 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1840 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1841 interconnect-names = "qup-core", 1842 "qup-config", 1843 "qup-memory"; 1844 1845 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1846 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1847 dma-names = "tx", 1848 "rx"; 1849 1850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1851 pinctrl-names = "default"; 1852 1853 #address-cells = <1>; 1854 #size-cells = <0>; 1855 1856 status = "disabled"; 1857 }; 1858 }; 1859 1860 gpi_dma0: dma-controller@b00000 { 1861 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1862 reg = <0 0x00b00000 0 0x60000>; 1863 1864 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1876 1877 dma-channels = <12>; 1878 dma-channel-mask = <0x3e>; 1879 #dma-cells = <3>; 1880 1881 iommus = <&apps_smmu 0x456 0x0>; 1882 1883 status = "disabled"; 1884 }; 1885 1886 qupv3_0: geniqup@bc0000 { 1887 compatible = "qcom,geni-se-qup"; 1888 reg = <0 0x00bc0000 0 0x2000>; 1889 1890 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1891 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1892 clock-names = "m-ahb", 1893 "s-ahb"; 1894 1895 iommus = <&apps_smmu 0x443 0x0>; 1896 #address-cells = <2>; 1897 #size-cells = <2>; 1898 ranges; 1899 1900 status = "disabled"; 1901 1902 i2c0: i2c@b80000 { 1903 compatible = "qcom,geni-i2c"; 1904 reg = <0 0xb80000 0 0x4000>; 1905 1906 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1907 1908 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1909 clock-names = "se"; 1910 1911 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1912 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1914 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1915 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1917 interconnect-names = "qup-core", 1918 "qup-config", 1919 "qup-memory"; 1920 1921 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1922 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1923 dma-names = "tx", 1924 "rx"; 1925 1926 pinctrl-0 = <&qup_i2c0_data_clk>; 1927 pinctrl-names = "default"; 1928 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 1932 status = "disabled"; 1933 }; 1934 1935 spi0: spi@b80000 { 1936 compatible = "qcom,geni-spi"; 1937 reg = <0 0x00b80000 0 0x4000>; 1938 1939 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1940 1941 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1942 clock-names = "se"; 1943 1944 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1945 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1947 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1948 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1949 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1950 interconnect-names = "qup-core", 1951 "qup-config", 1952 "qup-memory"; 1953 1954 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1955 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1956 dma-names = "tx", 1957 "rx"; 1958 1959 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1960 pinctrl-names = "default"; 1961 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 1965 status = "disabled"; 1966 }; 1967 1968 i2c1: i2c@b84000 { 1969 compatible = "qcom,geni-i2c"; 1970 reg = <0 0x00b84000 0 0x4000>; 1971 1972 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1973 1974 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1975 clock-names = "se"; 1976 1977 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1978 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1980 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1981 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1983 interconnect-names = "qup-core", 1984 "qup-config", 1985 "qup-memory"; 1986 1987 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1988 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1989 dma-names = "tx", 1990 "rx"; 1991 1992 pinctrl-0 = <&qup_i2c1_data_clk>; 1993 pinctrl-names = "default"; 1994 1995 #address-cells = <1>; 1996 #size-cells = <0>; 1997 1998 status = "disabled"; 1999 }; 2000 2001 spi1: spi@b84000 { 2002 compatible = "qcom,geni-spi"; 2003 reg = <0 0x00b84000 0 0x4000>; 2004 2005 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2006 2007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2008 clock-names = "se"; 2009 2010 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2011 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2012 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2013 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2014 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2015 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2016 interconnect-names = "qup-core", 2017 "qup-config", 2018 "qup-memory"; 2019 2020 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2021 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2022 dma-names = "tx", 2023 "rx"; 2024 2025 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2026 pinctrl-names = "default"; 2027 2028 #address-cells = <1>; 2029 #size-cells = <0>; 2030 2031 status = "disabled"; 2032 }; 2033 2034 i2c2: i2c@b88000 { 2035 compatible = "qcom,geni-i2c"; 2036 reg = <0 0x00b88000 0 0x4000>; 2037 2038 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2039 2040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2041 clock-names = "se"; 2042 2043 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2044 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2045 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2046 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2047 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2049 interconnect-names = "qup-core", 2050 "qup-config", 2051 "qup-memory"; 2052 2053 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2054 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2055 dma-names = "tx", 2056 "rx"; 2057 2058 pinctrl-0 = <&qup_i2c2_data_clk>; 2059 pinctrl-names = "default"; 2060 2061 #address-cells = <1>; 2062 #size-cells = <0>; 2063 2064 status = "disabled"; 2065 }; 2066 2067 spi2: spi@b88000 { 2068 compatible = "qcom,geni-spi"; 2069 reg = <0 0xb88000 0 0x4000>; 2070 2071 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2072 2073 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2074 clock-names = "se"; 2075 2076 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2077 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2079 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2080 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2082 interconnect-names = "qup-core", 2083 "qup-config", 2084 "qup-memory"; 2085 2086 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2087 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2088 dma-names = "tx", 2089 "rx"; 2090 2091 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2092 pinctrl-names = "default"; 2093 2094 #address-cells = <1>; 2095 #size-cells = <0>; 2096 2097 status = "disabled"; 2098 }; 2099 2100 i2c3: i2c@b8c000 { 2101 compatible = "qcom,geni-i2c"; 2102 reg = <0 0x00b8c000 0 0x4000>; 2103 2104 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2105 2106 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2107 clock-names = "se"; 2108 2109 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2110 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2111 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2112 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2113 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2115 interconnect-names = "qup-core", 2116 "qup-config", 2117 "qup-memory"; 2118 2119 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2120 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2121 dma-names = "tx", 2122 "rx"; 2123 2124 pinctrl-0 = <&qup_i2c3_data_clk>; 2125 pinctrl-names = "default"; 2126 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 spi3: spi@b8c000 { 2134 compatible = "qcom,geni-spi"; 2135 reg = <0 0x00b8c000 0 0x4000>; 2136 2137 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2138 2139 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2140 clock-names = "se"; 2141 2142 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2143 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2145 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2146 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2147 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2148 interconnect-names = "qup-core", 2149 "qup-config", 2150 "qup-memory"; 2151 2152 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2153 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2154 dma-names = "tx", 2155 "rx"; 2156 2157 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2158 pinctrl-names = "default"; 2159 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 2163 status = "disabled"; 2164 }; 2165 2166 i2c4: i2c@b90000 { 2167 compatible = "qcom,geni-i2c"; 2168 reg = <0 0xb90000 0 0x4000>; 2169 2170 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2171 2172 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2173 clock-names = "se"; 2174 2175 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2176 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2177 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2178 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2179 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2181 interconnect-names = "qup-core", 2182 "qup-config", 2183 "qup-memory"; 2184 2185 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2186 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2187 dma-names = "tx", 2188 "rx"; 2189 2190 pinctrl-0 = <&qup_i2c4_data_clk>; 2191 pinctrl-names = "default"; 2192 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 2196 status = "disabled"; 2197 }; 2198 2199 spi4: spi@b90000 { 2200 compatible = "qcom,geni-spi"; 2201 reg = <0 0x00b90000 0 0x4000>; 2202 2203 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2204 2205 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2206 clock-names = "se"; 2207 2208 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2209 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2211 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2212 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2213 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2214 interconnect-names = "qup-core", 2215 "qup-config", 2216 "qup-memory"; 2217 2218 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2219 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2220 dma-names = "tx", 2221 "rx"; 2222 2223 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2224 pinctrl-names = "default"; 2225 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 2229 status = "disabled"; 2230 }; 2231 2232 i2c5: i2c@b94000 { 2233 compatible = "qcom,geni-i2c"; 2234 reg = <0 0x00b94000 0 0x4000>; 2235 2236 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2239 clock-names = "se"; 2240 2241 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2242 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2244 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2245 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2247 interconnect-names = "qup-core", 2248 "qup-config", 2249 "qup-memory"; 2250 2251 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2252 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2253 dma-names = "tx", 2254 "rx"; 2255 2256 pinctrl-0 = <&qup_i2c5_data_clk>; 2257 pinctrl-names = "default"; 2258 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 2262 status = "disabled"; 2263 }; 2264 2265 spi5: spi@b94000 { 2266 compatible = "qcom,geni-spi"; 2267 reg = <0 0x00b94000 0 0x4000>; 2268 2269 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2270 2271 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2272 clock-names = "se"; 2273 2274 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2275 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2276 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2277 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2278 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2279 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2280 interconnect-names = "qup-core", 2281 "qup-config", 2282 "qup-memory"; 2283 2284 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2285 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2286 dma-names = "tx", 2287 "rx"; 2288 2289 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2290 pinctrl-names = "default"; 2291 2292 #address-cells = <1>; 2293 #size-cells = <0>; 2294 2295 status = "disabled"; 2296 }; 2297 2298 i2c6: i2c@b98000 { 2299 compatible = "qcom,geni-i2c"; 2300 reg = <0 0x00b98000 0 0x4000>; 2301 2302 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2303 2304 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2305 clock-names = "se"; 2306 2307 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2308 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2310 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2311 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2313 interconnect-names = "qup-core", 2314 "qup-config", 2315 "qup-memory"; 2316 2317 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2318 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2319 dma-names = "tx", 2320 "rx"; 2321 2322 pinctrl-0 = <&qup_i2c6_data_clk>; 2323 pinctrl-names = "default"; 2324 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 2328 status = "disabled"; 2329 }; 2330 2331 spi6: spi@b98000 { 2332 compatible = "qcom,geni-spi"; 2333 reg = <0 0x00b98000 0 0x4000>; 2334 2335 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2336 2337 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2338 clock-names = "se"; 2339 2340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2343 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2344 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2346 interconnect-names = "qup-core", 2347 "qup-config", 2348 "qup-memory"; 2349 2350 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2351 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2352 dma-names = "tx", 2353 "rx"; 2354 2355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2356 pinctrl-names = "default"; 2357 2358 #address-cells = <1>; 2359 #size-cells = <0>; 2360 2361 status = "disabled"; 2362 }; 2363 2364 i2c7: i2c@b9c000 { 2365 compatible = "qcom,geni-i2c"; 2366 reg = <0 0x00b9c000 0 0x4000>; 2367 2368 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2369 2370 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2371 clock-names = "se"; 2372 2373 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2374 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2376 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2377 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2379 interconnect-names = "qup-core", 2380 "qup-config", 2381 "qup-memory"; 2382 2383 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2384 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2385 dma-names = "tx", 2386 "rx"; 2387 2388 pinctrl-0 = <&qup_i2c7_data_clk>; 2389 pinctrl-names = "default"; 2390 2391 #address-cells = <1>; 2392 #size-cells = <0>; 2393 2394 status = "disabled"; 2395 }; 2396 2397 spi7: spi@b9c000 { 2398 compatible = "qcom,geni-spi"; 2399 reg = <0 0x00b9c000 0 0x4000>; 2400 2401 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2402 2403 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2404 clock-names = "se"; 2405 2406 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2407 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2409 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2410 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2412 interconnect-names = "qup-core", 2413 "qup-config", 2414 "qup-memory"; 2415 2416 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2417 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2418 dma-names = "tx", 2419 "rx"; 2420 2421 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2422 pinctrl-names = "default"; 2423 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 2427 status = "disabled"; 2428 }; 2429 }; 2430 2431 cnoc_main: interconnect@1500000 { 2432 compatible = "qcom,x1e80100-cnoc-main"; 2433 reg = <0 0x1500000 0 0x14400>; 2434 2435 qcom,bcm-voters = <&apps_bcm_voter>; 2436 2437 #interconnect-cells = <2>; 2438 }; 2439 2440 config_noc: interconnect@1600000 { 2441 compatible = "qcom,x1e80100-cnoc-cfg"; 2442 reg = <0 0x1600000 0 0x6600>; 2443 2444 qcom,bcm-voters = <&apps_bcm_voter>; 2445 2446 #interconnect-cells = <2>; 2447 }; 2448 2449 system_noc: interconnect@1680000 { 2450 compatible = "qcom,x1e80100-system-noc"; 2451 reg = <0 0x1680000 0 0x1c080>; 2452 2453 qcom,bcm-voters = <&apps_bcm_voter>; 2454 2455 #interconnect-cells = <2>; 2456 }; 2457 2458 pcie_south_anoc: interconnect@16c0000 { 2459 compatible = "qcom,x1e80100-pcie-south-anoc"; 2460 reg = <0 0x16c0000 0 0xd080>; 2461 2462 qcom,bcm-voters = <&apps_bcm_voter>; 2463 2464 #interconnect-cells = <2>; 2465 }; 2466 2467 pcie_center_anoc: interconnect@16d0000 { 2468 compatible = "qcom,x1e80100-pcie-center-anoc"; 2469 reg = <0 0x16d0000 0 0x7000>; 2470 2471 qcom,bcm-voters = <&apps_bcm_voter>; 2472 2473 #interconnect-cells = <2>; 2474 }; 2475 2476 aggre1_noc: interconnect@16e0000 { 2477 compatible = "qcom,x1e80100-aggre1-noc"; 2478 reg = <0 0x16E0000 0 0x14400>; 2479 2480 qcom,bcm-voters = <&apps_bcm_voter>; 2481 2482 #interconnect-cells = <2>; 2483 }; 2484 2485 aggre2_noc: interconnect@1700000 { 2486 compatible = "qcom,x1e80100-aggre2-noc"; 2487 reg = <0 0x1700000 0 0x1c400>; 2488 2489 qcom,bcm-voters = <&apps_bcm_voter>; 2490 2491 #interconnect-cells = <2>; 2492 }; 2493 2494 pcie_north_anoc: interconnect@1740000 { 2495 compatible = "qcom,x1e80100-pcie-north-anoc"; 2496 reg = <0 0x1740000 0 0x9080>; 2497 2498 qcom,bcm-voters = <&apps_bcm_voter>; 2499 2500 #interconnect-cells = <2>; 2501 }; 2502 2503 usb_center_anoc: interconnect@1750000 { 2504 compatible = "qcom,x1e80100-usb-center-anoc"; 2505 reg = <0 0x1750000 0 0x8800>; 2506 2507 qcom,bcm-voters = <&apps_bcm_voter>; 2508 2509 #interconnect-cells = <2>; 2510 }; 2511 2512 usb_north_anoc: interconnect@1760000 { 2513 compatible = "qcom,x1e80100-usb-north-anoc"; 2514 reg = <0 0x1760000 0 0x7080>; 2515 2516 qcom,bcm-voters = <&apps_bcm_voter>; 2517 2518 #interconnect-cells = <2>; 2519 }; 2520 2521 usb_south_anoc: interconnect@1770000 { 2522 compatible = "qcom,x1e80100-usb-south-anoc"; 2523 reg = <0 0x1770000 0 0xf080>; 2524 2525 qcom,bcm-voters = <&apps_bcm_voter>; 2526 2527 #interconnect-cells = <2>; 2528 }; 2529 2530 mmss_noc: interconnect@1780000 { 2531 compatible = "qcom,x1e80100-mmss-noc"; 2532 reg = <0 0x1780000 0 0x5B800>; 2533 2534 qcom,bcm-voters = <&apps_bcm_voter>; 2535 2536 #interconnect-cells = <2>; 2537 }; 2538 2539 tcsr_mutex: hwlock@1f40000 { 2540 compatible = "qcom,tcsr-mutex"; 2541 reg = <0 0x01f40000 0 0x20000>; 2542 #hwlock-cells = <1>; 2543 }; 2544 2545 gem_noc: interconnect@26400000 { 2546 compatible = "qcom,x1e80100-gem-noc"; 2547 reg = <0 0x26400000 0 0x311200>; 2548 2549 qcom,bcm-voters = <&apps_bcm_voter>; 2550 2551 #interconnect-cells = <2>; 2552 }; 2553 2554 nsp_noc: interconnect@320c0000 { 2555 compatible = "qcom,x1e80100-nsp-noc"; 2556 reg = <0 0x320C0000 0 0xE080>; 2557 2558 qcom,bcm-voters = <&apps_bcm_voter>; 2559 2560 #interconnect-cells = <2>; 2561 }; 2562 2563 lpass_ag_noc: interconnect@7e40000 { 2564 compatible = "qcom,x1e80100-lpass-ag-noc"; 2565 reg = <0 0x7e40000 0 0xE080>; 2566 2567 qcom,bcm-voters = <&apps_bcm_voter>; 2568 2569 #interconnect-cells = <2>; 2570 }; 2571 2572 lpass_lpiaon_noc: interconnect@7400000 { 2573 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 2574 reg = <0 0x7400000 0 0x19080>; 2575 2576 qcom,bcm-voters = <&apps_bcm_voter>; 2577 2578 #interconnect-cells = <2>; 2579 }; 2580 2581 lpass_lpicx_noc: interconnect@7430000 { 2582 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 2583 reg = <0 0x7430000 0 0x3A200>; 2584 2585 qcom,bcm-voters = <&apps_bcm_voter>; 2586 2587 #interconnect-cells = <2>; 2588 }; 2589 2590 pdc: interrupt-controller@b220000 { 2591 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 2592 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2593 2594 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 2595 <47 522 52>, <99 609 32>, 2596 <131 717 12>, <143 816 19>; 2597 #interrupt-cells = <2>; 2598 interrupt-parent = <&intc>; 2599 interrupt-controller; 2600 }; 2601 2602 tlmm: pinctrl@f100000 { 2603 compatible = "qcom,x1e80100-tlmm"; 2604 reg = <0 0x0f100000 0 0xf00000>; 2605 2606 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2607 2608 gpio-controller; 2609 #gpio-cells = <2>; 2610 2611 interrupt-controller; 2612 #interrupt-cells = <2>; 2613 2614 gpio-ranges = <&tlmm 0 0 239>; 2615 wakeup-parent = <&pdc>; 2616 2617 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2618 /* SDA, SCL */ 2619 pins = "gpio0", "gpio1"; 2620 function = "qup0_se0"; 2621 drive-strength = <2>; 2622 bias-pull-up = <2200>; 2623 }; 2624 2625 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2626 /* SDA, SCL */ 2627 pins = "gpio4", "gpio5"; 2628 function = "qup0_se1"; 2629 drive-strength = <2>; 2630 bias-pull-up = <2200>; 2631 }; 2632 2633 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2634 /* SDA, SCL */ 2635 pins = "gpio8", "gpio9"; 2636 function = "qup0_se2"; 2637 drive-strength = <2>; 2638 bias-pull-up = <2200>; 2639 }; 2640 2641 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2642 /* SDA, SCL */ 2643 pins = "gpio12", "gpio13"; 2644 function = "qup0_se3"; 2645 drive-strength = <2>; 2646 bias-pull-up = <2200>; 2647 }; 2648 2649 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2650 /* SDA, SCL */ 2651 pins = "gpio16", "gpio17"; 2652 function = "qup0_se4"; 2653 drive-strength = <2>; 2654 bias-pull-up = <2200>; 2655 }; 2656 2657 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2658 /* SDA, SCL */ 2659 pins = "gpio20", "gpio21"; 2660 function = "qup0_se5"; 2661 drive-strength = <2>; 2662 bias-pull-up = <2200>; 2663 }; 2664 2665 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2666 /* SDA, SCL */ 2667 pins = "gpio24", "gpio25"; 2668 function = "qup0_se6"; 2669 drive-strength = <2>; 2670 bias-pull-up = <2200>; 2671 }; 2672 2673 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2674 /* SDA, SCL */ 2675 pins = "gpio14", "gpio15"; 2676 function = "qup0_se7"; 2677 drive-strength = <2>; 2678 bias-pull-up = <2200>; 2679 }; 2680 2681 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2682 /* SDA, SCL */ 2683 pins = "gpio32", "gpio33"; 2684 function = "qup1_se0"; 2685 drive-strength = <2>; 2686 bias-pull-up = <2200>; 2687 }; 2688 2689 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2690 /* SDA, SCL */ 2691 pins = "gpio36", "gpio37"; 2692 function = "qup1_se1"; 2693 drive-strength = <2>; 2694 bias-pull-up = <2200>; 2695 }; 2696 2697 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2698 /* SDA, SCL */ 2699 pins = "gpio40", "gpio41"; 2700 function = "qup1_se2"; 2701 drive-strength = <2>; 2702 bias-pull-up = <2200>; 2703 }; 2704 2705 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2706 /* SDA, SCL */ 2707 pins = "gpio44", "gpio45"; 2708 function = "qup1_se3"; 2709 drive-strength = <2>; 2710 bias-pull-up = <2200>; 2711 }; 2712 2713 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2714 /* SDA, SCL */ 2715 pins = "gpio48", "gpio49"; 2716 function = "qup1_se4"; 2717 drive-strength = <2>; 2718 bias-pull-up = <2200>; 2719 }; 2720 2721 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2722 /* SDA, SCL */ 2723 pins = "gpio52", "gpio53"; 2724 function = "qup1_se5"; 2725 drive-strength = <2>; 2726 bias-pull-up = <2200>; 2727 }; 2728 2729 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 2730 /* SDA, SCL */ 2731 pins = "gpio56", "gpio57"; 2732 function = "qup1_se6"; 2733 drive-strength = <2>; 2734 bias-pull-up = <2200>; 2735 }; 2736 2737 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2738 /* SDA, SCL */ 2739 pins = "gpio54", "gpio55"; 2740 function = "qup1_se7"; 2741 drive-strength = <2>; 2742 bias-pull-up = <2200>; 2743 }; 2744 2745 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 2746 /* SDA, SCL */ 2747 pins = "gpio64", "gpio65"; 2748 function = "qup2_se0"; 2749 drive-strength = <2>; 2750 bias-pull-up = <2200>; 2751 }; 2752 2753 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 2754 /* SDA, SCL */ 2755 pins = "gpio68", "gpio69"; 2756 function = "qup2_se1"; 2757 drive-strength = <2>; 2758 bias-pull-up = <2200>; 2759 }; 2760 2761 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 2762 /* SDA, SCL */ 2763 pins = "gpio72", "gpio73"; 2764 function = "qup2_se2"; 2765 drive-strength = <2>; 2766 bias-pull-up = <2200>; 2767 }; 2768 2769 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 2770 /* SDA, SCL */ 2771 pins = "gpio76", "gpio77"; 2772 function = "qup2_se3"; 2773 drive-strength = <2>; 2774 bias-pull-up = <2200>; 2775 }; 2776 2777 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 2778 /* SDA, SCL */ 2779 pins = "gpio80", "gpio81"; 2780 function = "qup2_se4"; 2781 drive-strength = <2>; 2782 bias-pull-up = <2200>; 2783 }; 2784 2785 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 2786 /* SDA, SCL */ 2787 pins = "gpio84", "gpio85"; 2788 function = "qup2_se5"; 2789 drive-strength = <2>; 2790 bias-pull-up = <2200>; 2791 }; 2792 2793 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 2794 /* SDA, SCL */ 2795 pins = "gpio88", "gpio89"; 2796 function = "qup2_se6"; 2797 drive-strength = <2>; 2798 bias-pull-up = <2200>; 2799 }; 2800 2801 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 2802 /* SDA, SCL */ 2803 pins = "gpio86", "gpio87"; 2804 function = "qup2_se7"; 2805 drive-strength = <2>; 2806 bias-pull-up = <2200>; 2807 }; 2808 2809 qup_spi0_cs: qup-spi0-cs-state { 2810 pins = "gpio3"; 2811 function = "qup0_se0"; 2812 drive-strength = <6>; 2813 bias-disable; 2814 }; 2815 2816 qup_spi0_data_clk: qup-spi0-data-clk-state { 2817 /* MISO, MOSI, CLK */ 2818 pins = "gpio0", "gpio1", "gpio2"; 2819 function = "qup0_se0"; 2820 drive-strength = <6>; 2821 bias-disable; 2822 }; 2823 2824 qup_spi1_cs: qup-spi1-cs-state { 2825 pins = "gpio7"; 2826 function = "qup0_se1"; 2827 drive-strength = <6>; 2828 bias-disable; 2829 }; 2830 2831 qup_spi1_data_clk: qup-spi1-data-clk-state { 2832 /* MISO, MOSI, CLK */ 2833 pins = "gpio4", "gpio5", "gpio6"; 2834 function = "qup0_se1"; 2835 drive-strength = <6>; 2836 bias-disable; 2837 }; 2838 2839 qup_spi2_cs: qup-spi2-cs-state { 2840 pins = "gpio11"; 2841 function = "qup0_se2"; 2842 drive-strength = <6>; 2843 bias-disable; 2844 }; 2845 2846 qup_spi2_data_clk: qup-spi2-data-clk-state { 2847 /* MISO, MOSI, CLK */ 2848 pins = "gpio8", "gpio9", "gpio10"; 2849 function = "qup0_se2"; 2850 drive-strength = <6>; 2851 bias-disable; 2852 }; 2853 2854 qup_spi3_cs: qup-spi3-cs-state { 2855 pins = "gpio15"; 2856 function = "qup0_se3"; 2857 drive-strength = <6>; 2858 bias-disable; 2859 }; 2860 2861 qup_spi3_data_clk: qup-spi3-data-clk-state { 2862 /* MISO, MOSI, CLK */ 2863 pins = "gpio12", "gpio13", "gpio14"; 2864 function = "qup0_se3"; 2865 drive-strength = <6>; 2866 bias-disable; 2867 }; 2868 2869 qup_spi4_cs: qup-spi4-cs-state { 2870 pins = "gpio19"; 2871 function = "qup0_se4"; 2872 drive-strength = <6>; 2873 bias-disable; 2874 }; 2875 2876 qup_spi4_data_clk: qup-spi4-data-clk-state { 2877 /* MISO, MOSI, CLK */ 2878 pins = "gpio16", "gpio17", "gpio18"; 2879 function = "qup0_se4"; 2880 drive-strength = <6>; 2881 bias-disable; 2882 }; 2883 2884 qup_spi5_cs: qup-spi5-cs-state { 2885 pins = "gpio23"; 2886 function = "qup0_se5"; 2887 drive-strength = <6>; 2888 bias-disable; 2889 }; 2890 2891 qup_spi5_data_clk: qup-spi5-data-clk-state { 2892 /* MISO, MOSI, CLK */ 2893 pins = "gpio20", "gpio21", "gpio22"; 2894 function = "qup0_se5"; 2895 drive-strength = <6>; 2896 bias-disable; 2897 }; 2898 2899 qup_spi6_cs: qup-spi6-cs-state { 2900 pins = "gpio27"; 2901 function = "qup0_se6"; 2902 drive-strength = <6>; 2903 bias-disable; 2904 }; 2905 2906 qup_spi6_data_clk: qup-spi6-data-clk-state { 2907 /* MISO, MOSI, CLK */ 2908 pins = "gpio24", "gpio25", "gpio26"; 2909 function = "qup0_se6"; 2910 drive-strength = <6>; 2911 bias-disable; 2912 }; 2913 2914 qup_spi7_cs: qup-spi7-cs-state { 2915 pins = "gpio13"; 2916 function = "qup0_se7"; 2917 drive-strength = <6>; 2918 bias-disable; 2919 }; 2920 2921 qup_spi7_data_clk: qup-spi7-data-clk-state { 2922 /* MISO, MOSI, CLK */ 2923 pins = "gpio14", "gpio15", "gpio12"; 2924 function = "qup0_se7"; 2925 drive-strength = <6>; 2926 bias-disable; 2927 }; 2928 2929 qup_spi8_cs: qup-spi8-cs-state { 2930 pins = "gpio35"; 2931 function = "qup1_se0"; 2932 drive-strength = <6>; 2933 bias-disable; 2934 }; 2935 2936 qup_spi8_data_clk: qup-spi8-data-clk-state { 2937 /* MISO, MOSI, CLK */ 2938 pins = "gpio32", "gpio33", "gpio34"; 2939 function = "qup1_se0"; 2940 drive-strength = <6>; 2941 bias-disable; 2942 }; 2943 2944 qup_spi9_cs: qup-spi9-cs-state { 2945 pins = "gpio39"; 2946 function = "qup1_se1"; 2947 drive-strength = <6>; 2948 bias-disable; 2949 }; 2950 2951 qup_spi9_data_clk: qup-spi9-data-clk-state { 2952 /* MISO, MOSI, CLK */ 2953 pins = "gpio36", "gpio37", "gpio38"; 2954 function = "qup1_se1"; 2955 drive-strength = <6>; 2956 bias-disable; 2957 }; 2958 2959 qup_spi10_cs: qup-spi10-cs-state { 2960 pins = "gpio43"; 2961 function = "qup1_se2"; 2962 drive-strength = <6>; 2963 bias-disable; 2964 }; 2965 2966 qup_spi10_data_clk: qup-spi10-data-clk-state { 2967 /* MISO, MOSI, CLK */ 2968 pins = "gpio40", "gpio41", "gpio42"; 2969 function = "qup1_se2"; 2970 drive-strength = <6>; 2971 bias-disable; 2972 }; 2973 2974 qup_spi11_cs: qup-spi11-cs-state { 2975 pins = "gpio47"; 2976 function = "qup1_se3"; 2977 drive-strength = <6>; 2978 bias-disable; 2979 }; 2980 2981 qup_spi11_data_clk: qup-spi11-data-clk-state { 2982 /* MISO, MOSI, CLK */ 2983 pins = "gpio44", "gpio45", "gpio46"; 2984 function = "qup1_se3"; 2985 drive-strength = <6>; 2986 bias-disable; 2987 }; 2988 2989 qup_spi12_cs: qup-spi12-cs-state { 2990 pins = "gpio51"; 2991 function = "qup1_se4"; 2992 drive-strength = <6>; 2993 bias-disable; 2994 }; 2995 2996 qup_spi12_data_clk: qup-spi12-data-clk-state { 2997 /* MISO, MOSI, CLK */ 2998 pins = "gpio48", "gpio49", "gpio50"; 2999 function = "qup1_se4"; 3000 drive-strength = <6>; 3001 bias-disable; 3002 }; 3003 3004 qup_spi13_cs: qup-spi13-cs-state { 3005 pins = "gpio55"; 3006 function = "qup1_se5"; 3007 drive-strength = <6>; 3008 bias-disable; 3009 }; 3010 3011 qup_spi13_data_clk: qup-spi13-data-clk-state { 3012 /* MISO, MOSI, CLK */ 3013 pins = "gpio52", "gpio53", "gpio54"; 3014 function = "qup1_se5"; 3015 drive-strength = <6>; 3016 bias-disable; 3017 }; 3018 3019 qup_spi14_cs: qup-spi14-cs-state { 3020 pins = "gpio59"; 3021 function = "qup1_se6"; 3022 drive-strength = <6>; 3023 bias-disable; 3024 }; 3025 3026 qup_spi14_data_clk: qup-spi14-data-clk-state { 3027 /* MISO, MOSI, CLK */ 3028 pins = "gpio56", "gpio57", "gpio58"; 3029 function = "qup1_se6"; 3030 drive-strength = <6>; 3031 bias-disable; 3032 }; 3033 3034 qup_spi15_cs: qup-spi15-cs-state { 3035 pins = "gpio53"; 3036 function = "qup1_se7"; 3037 drive-strength = <6>; 3038 bias-disable; 3039 }; 3040 3041 qup_spi15_data_clk: qup-spi15-data-clk-state { 3042 /* MISO, MOSI, CLK */ 3043 pins = "gpio54", "gpio55", "gpio52"; 3044 function = "qup1_se7"; 3045 drive-strength = <6>; 3046 bias-disable; 3047 }; 3048 3049 qup_spi16_cs: qup-spi16-cs-state { 3050 pins = "gpio67"; 3051 function = "qup2_se0"; 3052 drive-strength = <6>; 3053 bias-disable; 3054 }; 3055 3056 qup_spi16_data_clk: qup-spi16-data-clk-state { 3057 /* MISO, MOSI, CLK */ 3058 pins = "gpio64", "gpio65", "gpio66"; 3059 function = "qup2_se0"; 3060 drive-strength = <6>; 3061 bias-disable; 3062 }; 3063 3064 qup_spi17_cs: qup-spi17-cs-state { 3065 pins = "gpio71"; 3066 function = "qup2_se1"; 3067 drive-strength = <6>; 3068 bias-disable; 3069 }; 3070 3071 qup_spi17_data_clk: qup-spi17-data-clk-state { 3072 /* MISO, MOSI, CLK */ 3073 pins = "gpio68", "gpio69", "gpio70"; 3074 function = "qup2_se1"; 3075 drive-strength = <6>; 3076 bias-disable; 3077 }; 3078 3079 qup_spi18_cs: qup-spi18-cs-state { 3080 pins = "gpio75"; 3081 function = "qup2_se2"; 3082 drive-strength = <6>; 3083 bias-disable; 3084 }; 3085 3086 qup_spi18_data_clk: qup-spi18-data-clk-state { 3087 /* MISO, MOSI, CLK */ 3088 pins = "gpio72", "gpio73", "gpio74"; 3089 function = "qup2_se2"; 3090 drive-strength = <6>; 3091 bias-disable; 3092 }; 3093 3094 qup_spi19_cs: qup-spi19-cs-state { 3095 pins = "gpio79"; 3096 function = "qup2_se3"; 3097 drive-strength = <6>; 3098 bias-disable; 3099 }; 3100 3101 qup_spi19_data_clk: qup-spi19-data-clk-state { 3102 /* MISO, MOSI, CLK */ 3103 pins = "gpio76", "gpio77", "gpio78"; 3104 function = "qup2_se3"; 3105 drive-strength = <6>; 3106 bias-disable; 3107 }; 3108 3109 qup_spi20_cs: qup-spi20-cs-state { 3110 pins = "gpio83"; 3111 function = "qup2_se4"; 3112 drive-strength = <6>; 3113 bias-disable; 3114 }; 3115 3116 qup_spi20_data_clk: qup-spi20-data-clk-state { 3117 /* MISO, MOSI, CLK */ 3118 pins = "gpio80", "gpio81", "gpio82"; 3119 function = "qup2_se4"; 3120 drive-strength = <6>; 3121 bias-disable; 3122 }; 3123 3124 qup_spi21_cs: qup-spi21-cs-state { 3125 pins = "gpio87"; 3126 function = "qup2_se5"; 3127 drive-strength = <6>; 3128 bias-disable; 3129 }; 3130 3131 qup_spi21_data_clk: qup-spi21-data-clk-state { 3132 /* MISO, MOSI, CLK */ 3133 pins = "gpio84", "gpio85", "gpio86"; 3134 function = "qup2_se5"; 3135 drive-strength = <6>; 3136 bias-disable; 3137 }; 3138 3139 qup_spi22_cs: qup-spi22-cs-state { 3140 pins = "gpio91"; 3141 function = "qup2_se6"; 3142 drive-strength = <6>; 3143 bias-disable; 3144 }; 3145 3146 qup_spi22_data_clk: qup-spi22-data-clk-state { 3147 /* MISO, MOSI, CLK */ 3148 pins = "gpio88", "gpio89", "gpio90"; 3149 function = "qup2_se6"; 3150 drive-strength = <6>; 3151 bias-disable; 3152 }; 3153 3154 qup_spi23_cs: qup-spi23-cs-state { 3155 pins = "gpio85"; 3156 function = "qup2_se7"; 3157 drive-strength = <6>; 3158 bias-disable; 3159 }; 3160 3161 qup_spi23_data_clk: qup-spi23-data-clk-state { 3162 /* MISO, MOSI, CLK */ 3163 pins = "gpio86", "gpio87", "gpio84"; 3164 function = "qup2_se7"; 3165 drive-strength = <6>; 3166 bias-disable; 3167 }; 3168 3169 qup_uart21_default: qup-uart21-default-state { 3170 /* TX, RX */ 3171 pins = "gpio86", "gpio87"; 3172 function = "qup2_se5"; 3173 drive-strength= <2>; 3174 bias-disable; 3175 }; 3176 }; 3177 3178 apps_smmu: iommu@15000000 { 3179 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3180 reg = <0 0x15000000 0 0x100000>; 3181 3182 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3279 3280 #iommu-cells = <2>; 3281 #global-interrupts = <1>; 3282 }; 3283 3284 intc: interrupt-controller@17000000 { 3285 compatible = "arm,gic-v3"; 3286 reg = <0 0x17000000 0 0x10000>, /* GICD */ 3287 <0 0x17080000 0 0x480000>; /* GICR * 12 */ 3288 3289 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3290 3291 #interrupt-cells = <3>; 3292 interrupt-controller; 3293 3294 #redistributor-regions = <1>; 3295 redistributor-stride = <0x0 0x40000>; 3296 3297 #address-cells = <2>; 3298 #size-cells = <2>; 3299 ranges; 3300 3301 gic_its: msi-controller@17040000 { 3302 compatible = "arm,gic-v3-its"; 3303 reg = <0 0x17040000 0 0x40000>; 3304 3305 msi-controller; 3306 #msi-cells = <1>; 3307 3308 status = "disabled"; 3309 }; 3310 }; 3311 3312 apps_rsc: rsc@17500000 { 3313 compatible = "qcom,rpmh-rsc"; 3314 reg = <0 0x17500000 0 0x10000>, 3315 <0 0x17510000 0 0x10000>, 3316 <0 0x17520000 0 0x10000>; 3317 reg-names = "drv-0", "drv-1", "drv-2"; 3318 qcom,drv-count = <3>; 3319 3320 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3323 qcom,tcs-offset = <0xd00>; 3324 qcom,drv-id = <2>; 3325 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3326 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3327 3328 label = "apps_rsc"; 3329 3330 apps_bcm_voter: bcm-voter { 3331 compatible = "qcom,bcm-voter"; 3332 }; 3333 3334 rpmhcc: clock-controller { 3335 compatible = "qcom,x1e80100-rpmh-clk"; 3336 3337 clocks = <&xo_board>; 3338 clock-names = "xo"; 3339 3340 #clock-cells = <1>; 3341 }; 3342 3343 rpmhpd: power-controller { 3344 compatible = "qcom,x1e80100-rpmhpd"; 3345 3346 operating-points-v2 = <&rpmhpd_opp_table>; 3347 3348 #power-domain-cells = <1>; 3349 3350 rpmhpd_opp_table: opp-table { 3351 compatible = "operating-points-v2"; 3352 3353 rpmhpd_opp_ret: opp-16 { 3354 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3355 }; 3356 3357 rpmhpd_opp_min_svs: opp-48 { 3358 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3359 }; 3360 3361 rpmhpd_opp_low_svs_d2: opp-52 { 3362 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3363 }; 3364 3365 rpmhpd_opp_low_svs_d1: opp-56 { 3366 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3367 }; 3368 3369 rpmhpd_opp_low_svs_d0: opp-60 { 3370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3371 }; 3372 3373 rpmhpd_opp_low_svs: opp-64 { 3374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3375 }; 3376 3377 rpmhpd_opp_low_svs_l1: opp-80 { 3378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3379 }; 3380 3381 rpmhpd_opp_svs: opp-128 { 3382 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3383 }; 3384 3385 rpmhpd_opp_svs_l0: opp-144 { 3386 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3387 }; 3388 3389 rpmhpd_opp_svs_l1: opp-192 { 3390 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3391 }; 3392 3393 rpmhpd_opp_nom: opp-256 { 3394 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3395 }; 3396 3397 rpmhpd_opp_nom_l1: opp-320 { 3398 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3399 }; 3400 3401 rpmhpd_opp_nom_l2: opp-336 { 3402 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3403 }; 3404 3405 rpmhpd_opp_turbo: opp-384 { 3406 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3407 }; 3408 3409 rpmhpd_opp_turbo_l1: opp-416 { 3410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3411 }; 3412 }; 3413 }; 3414 }; 3415 3416 timer@17800000 { 3417 compatible = "arm,armv7-timer-mem"; 3418 reg = <0 0x17800000 0 0x1000>; 3419 3420 #address-cells = <2>; 3421 #size-cells = <1>; 3422 ranges = <0 0 0 0 0x20000000>; 3423 3424 frame@17801000 { 3425 reg = <0 0x17801000 0x1000>, 3426 <0 0x17802000 0x1000>; 3427 3428 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3430 3431 frame-number = <0>; 3432 }; 3433 3434 frame@17803000 { 3435 reg = <0 0x17803000 0x1000>; 3436 3437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3438 3439 frame-number = <1>; 3440 3441 status = "disabled"; 3442 }; 3443 3444 frame@17805000 { 3445 reg = <0 0x17805000 0x1000>; 3446 3447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3448 3449 frame-number = <2>; 3450 3451 status = "disabled"; 3452 }; 3453 3454 frame@17807000 { 3455 reg = <0 0x17807000 0x1000>; 3456 3457 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3458 3459 frame-number = <3>; 3460 3461 status = "disabled"; 3462 }; 3463 3464 frame@17809000 { 3465 reg = <0 0x17809000 0x1000>; 3466 3467 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3468 3469 frame-number = <4>; 3470 3471 status = "disabled"; 3472 }; 3473 3474 frame@1780b000 { 3475 reg = <0 0x1780b000 0x1000>; 3476 3477 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3478 3479 frame-number = <5>; 3480 3481 status = "disabled"; 3482 }; 3483 3484 frame@1780d000 { 3485 reg = <0 0x1780d000 0x1000>; 3486 3487 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3488 3489 frame-number = <6>; 3490 3491 status = "disabled"; 3492 }; 3493 }; 3494 3495 system-cache-controller@25000000 { 3496 compatible = "qcom,x1e80100-llcc"; 3497 reg = <0 0x25000000 0 0x200000>, 3498 <0 0x25200000 0 0x200000>, 3499 <0 0x25400000 0 0x200000>, 3500 <0 0x25600000 0 0x200000>, 3501 <0 0x25800000 0 0x200000>, 3502 <0 0x25a00000 0 0x200000>, 3503 <0 0x25c00000 0 0x200000>, 3504 <0 0x25e00000 0 0x200000>, 3505 <0 0x26000000 0 0x200000>; 3506 reg-names = "llcc0_base", 3507 "llcc1_base", 3508 "llcc2_base", 3509 "llcc3_base", 3510 "llcc4_base", 3511 "llcc5_base", 3512 "llcc6_base", 3513 "llcc7_base", 3514 "llcc_broadcast_base"; 3515 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3516 }; 3517 }; 3518 3519 timer { 3520 compatible = "arm,armv8-timer"; 3521 3522 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3523 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3524 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3525 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3526 }; 3527}; 3528