1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 operating-points-v2 = <&cpu0_opp_table>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x0 0x1>; 57 clocks = <&cru ARMCLK>; 58 #cooling-cells = <2>; 59 cpu-idle-states = <&CPU_SLEEP>; 60 dynamic-power-coefficient = <120>; 61 enable-method = "psci"; 62 next-level-cache = <&l2>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x2>; 70 clocks = <&cru ARMCLK>; 71 #cooling-cells = <2>; 72 cpu-idle-states = <&CPU_SLEEP>; 73 dynamic-power-coefficient = <120>; 74 enable-method = "psci"; 75 next-level-cache = <&l2>; 76 operating-points-v2 = <&cpu0_opp_table>; 77 }; 78 79 cpu3: cpu@3 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x3>; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP>; 86 dynamic-power-coefficient = <120>; 87 enable-method = "psci"; 88 next-level-cache = <&l2>; 89 operating-points-v2 = <&cpu0_opp_table>; 90 }; 91 92 idle-states { 93 entry-method = "psci"; 94 95 CPU_SLEEP: cpu-sleep { 96 compatible = "arm,idle-state"; 97 local-timer-stop; 98 arm,psci-suspend-param = <0x0010000>; 99 entry-latency-us = <120>; 100 exit-latency-us = <250>; 101 min-residency-us = <900>; 102 }; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 }; 110 }; 111 112 cpu0_opp_table: opp-table-0 { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <950000>; 119 clock-latency-ns = <40000>; 120 opp-suspend; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <950000>; 125 clock-latency-ns = <40000>; 126 }; 127 opp-816000000 { 128 opp-hz = /bits/ 64 <816000000>; 129 opp-microvolt = <1000000>; 130 clock-latency-ns = <40000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1100000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <1225000>; 140 clock-latency-ns = <40000>; 141 }; 142 opp-1296000000 { 143 opp-hz = /bits/ 64 <1296000000>; 144 opp-microvolt = <1300000>; 145 clock-latency-ns = <40000>; 146 }; 147 }; 148 149 analog_sound: analog-sound { 150 compatible = "simple-audio-card"; 151 simple-audio-card,format = "i2s"; 152 simple-audio-card,mclk-fs = <256>; 153 simple-audio-card,name = "Analog"; 154 status = "disabled"; 155 156 simple-audio-card,cpu { 157 sound-dai = <&i2s1>; 158 }; 159 160 simple-audio-card,codec { 161 sound-dai = <&codec>; 162 }; 163 }; 164 165 arm-pmu { 166 compatible = "arm,cortex-a53-pmu"; 167 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 172 }; 173 174 display_subsystem: display-subsystem { 175 compatible = "rockchip,display-subsystem"; 176 ports = <&vop_out>; 177 }; 178 179 hdmi_sound: hdmi-sound { 180 compatible = "simple-audio-card"; 181 simple-audio-card,format = "i2s"; 182 simple-audio-card,mclk-fs = <128>; 183 simple-audio-card,name = "HDMI"; 184 status = "disabled"; 185 186 simple-audio-card,cpu { 187 sound-dai = <&i2s0>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&hdmi>; 192 }; 193 }; 194 195 psci { 196 compatible = "arm,psci-1.0", "arm,psci-0.2"; 197 method = "smc"; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 206 }; 207 208 xin24m: xin24m { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <24000000>; 212 clock-output-names = "xin24m"; 213 }; 214 215 i2s0: i2s@ff000000 { 216 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 217 reg = <0x0 0xff000000 0x0 0x1000>; 218 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 220 clock-names = "i2s_clk", "i2s_hclk"; 221 dmas = <&dmac 11>, <&dmac 12>; 222 dma-names = "tx", "rx"; 223 #sound-dai-cells = <0>; 224 status = "disabled"; 225 }; 226 227 i2s1: i2s@ff010000 { 228 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 229 reg = <0x0 0xff010000 0x0 0x1000>; 230 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 232 clock-names = "i2s_clk", "i2s_hclk"; 233 dmas = <&dmac 14>, <&dmac 15>; 234 dma-names = "tx", "rx"; 235 #sound-dai-cells = <0>; 236 status = "disabled"; 237 }; 238 239 i2s2: i2s@ff020000 { 240 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff020000 0x0 0x1000>; 242 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 0>, <&dmac 1>; 246 dma-names = "tx", "rx"; 247 #sound-dai-cells = <0>; 248 status = "disabled"; 249 }; 250 251 spdif: spdif@ff030000 { 252 compatible = "rockchip,rk3328-spdif"; 253 reg = <0x0 0xff030000 0x0 0x1000>; 254 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 256 clock-names = "mclk", "hclk"; 257 dmas = <&dmac 10>; 258 dma-names = "tx"; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&spdifm2_tx>; 261 #sound-dai-cells = <0>; 262 status = "disabled"; 263 }; 264 265 pdm: pdm@ff040000 { 266 compatible = "rockchip,pdm"; 267 reg = <0x0 0xff040000 0x0 0x1000>; 268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 269 clock-names = "pdm_clk", "pdm_hclk"; 270 dmas = <&dmac 16>; 271 dma-names = "rx"; 272 pinctrl-names = "default", "sleep"; 273 pinctrl-0 = <&pdmm0_clk 274 &pdmm0_sdi0 275 &pdmm0_sdi1 276 &pdmm0_sdi2 277 &pdmm0_sdi3>; 278 pinctrl-1 = <&pdmm0_clk_sleep 279 &pdmm0_sdi0_sleep 280 &pdmm0_sdi1_sleep 281 &pdmm0_sdi2_sleep 282 &pdmm0_sdi3_sleep>; 283 status = "disabled"; 284 }; 285 286 grf: syscon@ff100000 { 287 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 288 reg = <0x0 0xff100000 0x0 0x1000>; 289 290 io_domains: io-domains { 291 compatible = "rockchip,rk3328-io-voltage-domain"; 292 status = "disabled"; 293 }; 294 295 grf_gpio: gpio { 296 compatible = "rockchip,rk3328-grf-gpio"; 297 gpio-controller; 298 #gpio-cells = <2>; 299 }; 300 301 power: power-controller { 302 compatible = "rockchip,rk3328-power-controller"; 303 #power-domain-cells = <1>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 power-domain@RK3328_PD_HEVC { 308 reg = <RK3328_PD_HEVC>; 309 #power-domain-cells = <0>; 310 }; 311 power-domain@RK3328_PD_VIDEO { 312 reg = <RK3328_PD_VIDEO>; 313 clocks = <&cru ACLK_RKVDEC>, 314 <&cru HCLK_RKVDEC>, 315 <&cru SCLK_VDEC_CABAC>, 316 <&cru SCLK_VDEC_CORE>; 317 #power-domain-cells = <0>; 318 }; 319 power-domain@RK3328_PD_VPU { 320 reg = <RK3328_PD_VPU>; 321 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 322 #power-domain-cells = <0>; 323 }; 324 }; 325 326 reboot-mode { 327 compatible = "syscon-reboot-mode"; 328 offset = <0x5c8>; 329 mode-normal = <BOOT_NORMAL>; 330 mode-recovery = <BOOT_RECOVERY>; 331 mode-bootloader = <BOOT_FASTBOOT>; 332 mode-loader = <BOOT_BL_DOWNLOAD>; 333 }; 334 }; 335 336 uart0: serial@ff110000 { 337 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 338 reg = <0x0 0xff110000 0x0 0x100>; 339 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 341 clock-names = "baudclk", "apb_pclk"; 342 dmas = <&dmac 2>, <&dmac 3>; 343 dma-names = "tx", "rx"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 346 reg-io-width = <4>; 347 reg-shift = <2>; 348 status = "disabled"; 349 }; 350 351 uart1: serial@ff120000 { 352 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 353 reg = <0x0 0xff120000 0x0 0x100>; 354 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 356 clock-names = "baudclk", "apb_pclk"; 357 dmas = <&dmac 4>, <&dmac 5>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 361 reg-io-width = <4>; 362 reg-shift = <2>; 363 status = "disabled"; 364 }; 365 366 uart2: serial@ff130000 { 367 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 368 reg = <0x0 0xff130000 0x0 0x100>; 369 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 371 clock-names = "baudclk", "apb_pclk"; 372 dmas = <&dmac 6>, <&dmac 7>; 373 dma-names = "tx", "rx"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&uart2m1_xfer>; 376 reg-io-width = <4>; 377 reg-shift = <2>; 378 status = "disabled"; 379 }; 380 381 i2c0: i2c@ff150000 { 382 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 383 reg = <0x0 0xff150000 0x0 0x1000>; 384 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 388 clock-names = "i2c", "pclk"; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&i2c0_xfer>; 391 status = "disabled"; 392 }; 393 394 i2c1: i2c@ff160000 { 395 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 396 reg = <0x0 0xff160000 0x0 0x1000>; 397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 401 clock-names = "i2c", "pclk"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&i2c1_xfer>; 404 status = "disabled"; 405 }; 406 407 i2c2: i2c@ff170000 { 408 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 409 reg = <0x0 0xff170000 0x0 0x1000>; 410 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 414 clock-names = "i2c", "pclk"; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&i2c2_xfer>; 417 status = "disabled"; 418 }; 419 420 i2c3: i2c@ff180000 { 421 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 422 reg = <0x0 0xff180000 0x0 0x1000>; 423 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 427 clock-names = "i2c", "pclk"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&i2c3_xfer>; 430 status = "disabled"; 431 }; 432 433 spi0: spi@ff190000 { 434 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 435 reg = <0x0 0xff190000 0x0 0x1000>; 436 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 440 clock-names = "spiclk", "apb_pclk"; 441 dmas = <&dmac 8>, <&dmac 9>; 442 dma-names = "tx", "rx"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 445 status = "disabled"; 446 }; 447 448 wdt: watchdog@ff1a0000 { 449 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 450 reg = <0x0 0xff1a0000 0x0 0x100>; 451 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru PCLK_WDT>; 453 }; 454 455 pwm0: pwm@ff1b0000 { 456 compatible = "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff1b0000 0x0 0x10>; 458 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm0_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm1: pwm@ff1b0010 { 467 compatible = "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff1b0010 0x0 0x10>; 469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm1_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm2: pwm@ff1b0020 { 478 compatible = "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff1b0020 0x0 0x10>; 480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm2_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm3: pwm@ff1b0030 { 489 compatible = "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff1b0030 0x0 0x10>; 491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pwmir_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 dmac: dma-controller@ff1f0000 { 500 compatible = "arm,pl330", "arm,primecell"; 501 reg = <0x0 0xff1f0000 0x0 0x4000>; 502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 504 arm,pl330-periph-burst; 505 clocks = <&cru ACLK_DMAC>; 506 clock-names = "apb_pclk"; 507 #dma-cells = <1>; 508 }; 509 510 thermal-zones { 511 soc_thermal: soc-thermal { 512 polling-delay-passive = <20>; 513 polling-delay = <1000>; 514 sustainable-power = <1000>; 515 516 thermal-sensors = <&tsadc 0>; 517 518 trips { 519 threshold: trip-point0 { 520 temperature = <70000>; 521 hysteresis = <2000>; 522 type = "passive"; 523 }; 524 target: trip-point1 { 525 temperature = <85000>; 526 hysteresis = <2000>; 527 type = "passive"; 528 }; 529 soc_crit: soc-crit { 530 temperature = <95000>; 531 hysteresis = <2000>; 532 type = "critical"; 533 }; 534 }; 535 536 cooling-maps { 537 map0 { 538 trip = <&target>; 539 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 543 contribution = <4096>; 544 }; 545 }; 546 }; 547 548 }; 549 550 tsadc: tsadc@ff250000 { 551 compatible = "rockchip,rk3328-tsadc"; 552 reg = <0x0 0xff250000 0x0 0x100>; 553 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 554 assigned-clocks = <&cru SCLK_TSADC>; 555 assigned-clock-rates = <50000>; 556 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 557 clock-names = "tsadc", "apb_pclk"; 558 pinctrl-names = "init", "default", "sleep"; 559 pinctrl-0 = <&otp_pin>; 560 pinctrl-1 = <&otp_out>; 561 pinctrl-2 = <&otp_pin>; 562 resets = <&cru SRST_TSADC>; 563 reset-names = "tsadc-apb"; 564 rockchip,grf = <&grf>; 565 rockchip,hw-tshut-temp = <100000>; 566 #thermal-sensor-cells = <1>; 567 status = "disabled"; 568 }; 569 570 efuse: efuse@ff260000 { 571 compatible = "rockchip,rk3328-efuse"; 572 reg = <0x0 0xff260000 0x0 0x50>; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 clocks = <&cru SCLK_EFUSE>; 576 clock-names = "pclk_efuse"; 577 rockchip,efuse-size = <0x20>; 578 579 /* Data cells */ 580 efuse_id: id@7 { 581 reg = <0x07 0x10>; 582 }; 583 cpu_leakage: cpu-leakage@17 { 584 reg = <0x17 0x1>; 585 }; 586 logic_leakage: logic-leakage@19 { 587 reg = <0x19 0x1>; 588 }; 589 efuse_cpu_version: cpu-version@1a { 590 reg = <0x1a 0x1>; 591 bits = <3 3>; 592 }; 593 }; 594 595 saradc: adc@ff280000 { 596 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 597 reg = <0x0 0xff280000 0x0 0x100>; 598 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 599 #io-channel-cells = <1>; 600 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 601 clock-names = "saradc", "apb_pclk"; 602 resets = <&cru SRST_SARADC_P>; 603 reset-names = "saradc-apb"; 604 status = "disabled"; 605 }; 606 607 gpu: gpu@ff300000 { 608 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 609 reg = <0x0 0xff300000 0x0 0x30000>; 610 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-names = "gp", 618 "gpmmu", 619 "pp", 620 "pp0", 621 "ppmmu0", 622 "pp1", 623 "ppmmu1"; 624 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 625 clock-names = "bus", "core"; 626 resets = <&cru SRST_GPU_A>; 627 }; 628 629 h265e_mmu: iommu@ff330200 { 630 compatible = "rockchip,iommu"; 631 reg = <0x0 0xff330200 0 0x100>; 632 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 634 clock-names = "aclk", "iface"; 635 #iommu-cells = <0>; 636 status = "disabled"; 637 }; 638 639 vepu_mmu: iommu@ff340800 { 640 compatible = "rockchip,iommu"; 641 reg = <0x0 0xff340800 0x0 0x40>; 642 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 644 clock-names = "aclk", "iface"; 645 #iommu-cells = <0>; 646 status = "disabled"; 647 }; 648 649 vpu: video-codec@ff350000 { 650 compatible = "rockchip,rk3328-vpu"; 651 reg = <0x0 0xff350000 0x0 0x800>; 652 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 653 interrupt-names = "vdpu"; 654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 655 clock-names = "aclk", "hclk"; 656 iommus = <&vpu_mmu>; 657 power-domains = <&power RK3328_PD_VPU>; 658 }; 659 660 vpu_mmu: iommu@ff350800 { 661 compatible = "rockchip,iommu"; 662 reg = <0x0 0xff350800 0x0 0x40>; 663 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 665 clock-names = "aclk", "iface"; 666 #iommu-cells = <0>; 667 power-domains = <&power RK3328_PD_VPU>; 668 }; 669 670 vdec: video-codec@ff360000 { 671 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 672 reg = <0x0 0xff360000 0x0 0x480>; 673 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 675 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 676 clock-names = "axi", "ahb", "cabac", "core"; 677 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 678 <&cru SCLK_VDEC_CORE>; 679 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 680 iommus = <&vdec_mmu>; 681 power-domains = <&power RK3328_PD_VIDEO>; 682 }; 683 684 vdec_mmu: iommu@ff360480 { 685 compatible = "rockchip,iommu"; 686 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 687 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 689 clock-names = "aclk", "iface"; 690 #iommu-cells = <0>; 691 power-domains = <&power RK3328_PD_VIDEO>; 692 }; 693 694 vop: vop@ff370000 { 695 compatible = "rockchip,rk3328-vop"; 696 reg = <0x0 0xff370000 0x0 0x3efc>; 697 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 699 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 700 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 701 reset-names = "axi", "ahb", "dclk"; 702 iommus = <&vop_mmu>; 703 status = "disabled"; 704 705 vop_out: port { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 vop_out_hdmi: endpoint@0 { 710 reg = <0>; 711 remote-endpoint = <&hdmi_in_vop>; 712 }; 713 }; 714 }; 715 716 vop_mmu: iommu@ff373f00 { 717 compatible = "rockchip,iommu"; 718 reg = <0x0 0xff373f00 0x0 0x100>; 719 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 721 clock-names = "aclk", "iface"; 722 #iommu-cells = <0>; 723 status = "disabled"; 724 }; 725 726 hdmi: hdmi@ff3c0000 { 727 compatible = "rockchip,rk3328-dw-hdmi"; 728 reg = <0x0 0xff3c0000 0x0 0x20000>; 729 reg-io-width = <4>; 730 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cru PCLK_HDMI>, 733 <&cru SCLK_HDMI_SFC>, 734 <&cru SCLK_RTC32K>; 735 clock-names = "iahb", 736 "isfr", 737 "cec"; 738 phys = <&hdmiphy>; 739 phy-names = "hdmi"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 742 rockchip,grf = <&grf>; 743 #sound-dai-cells = <0>; 744 status = "disabled"; 745 746 ports { 747 hdmi_in: port { 748 hdmi_in_vop: endpoint { 749 remote-endpoint = <&vop_out_hdmi>; 750 }; 751 }; 752 }; 753 }; 754 755 codec: codec@ff410000 { 756 compatible = "rockchip,rk3328-codec"; 757 reg = <0x0 0xff410000 0x0 0x1000>; 758 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 759 clock-names = "pclk", "mclk"; 760 rockchip,grf = <&grf>; 761 #sound-dai-cells = <0>; 762 status = "disabled"; 763 }; 764 765 hdmiphy: phy@ff430000 { 766 compatible = "rockchip,rk3328-hdmi-phy"; 767 reg = <0x0 0xff430000 0x0 0x10000>; 768 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 770 clock-names = "sysclk", "refoclk", "refpclk"; 771 clock-output-names = "hdmi_phy"; 772 #clock-cells = <0>; 773 nvmem-cells = <&efuse_cpu_version>; 774 nvmem-cell-names = "cpu-version"; 775 #phy-cells = <0>; 776 status = "disabled"; 777 }; 778 779 cru: clock-controller@ff440000 { 780 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 781 reg = <0x0 0xff440000 0x0 0x1000>; 782 rockchip,grf = <&grf>; 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 assigned-clocks = 786 /* 787 * CPLL should run at 1200, but that is to high for 788 * the initial dividers of most of its children. 789 * We need set cpll child clk div first, 790 * and then set the cpll frequency. 791 */ 792 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 793 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 794 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 795 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 796 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 797 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 798 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 799 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 800 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 801 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 802 <&cru SCLK_WIFI>, <&cru ARMCLK>, 803 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 804 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 805 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 806 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 807 <&cru SCLK_RTC32K>; 808 assigned-clock-parents = 809 <&cru HDMIPHY>, <&cru PLL_APLL>, 810 <&cru PLL_GPLL>, <&xin24m>, 811 <&xin24m>, <&xin24m>; 812 assigned-clock-rates = 813 <0>, <61440000>, 814 <0>, <24000000>, 815 <24000000>, <24000000>, 816 <15000000>, <15000000>, 817 <100000000>, <100000000>, 818 <100000000>, <100000000>, 819 <50000000>, <100000000>, 820 <100000000>, <100000000>, 821 <50000000>, <50000000>, 822 <50000000>, <50000000>, 823 <24000000>, <600000000>, 824 <491520000>, <1200000000>, 825 <150000000>, <75000000>, 826 <75000000>, <150000000>, 827 <75000000>, <75000000>, 828 <32768>; 829 }; 830 831 usb2phy_grf: syscon@ff450000 { 832 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 833 "simple-mfd"; 834 reg = <0x0 0xff450000 0x0 0x10000>; 835 #address-cells = <1>; 836 #size-cells = <1>; 837 838 u2phy: usb2phy@100 { 839 compatible = "rockchip,rk3328-usb2phy"; 840 reg = <0x100 0x10>; 841 clocks = <&xin24m>; 842 clock-names = "phyclk"; 843 clock-output-names = "usb480m_phy"; 844 #clock-cells = <0>; 845 assigned-clocks = <&cru USB480M>; 846 assigned-clock-parents = <&u2phy>; 847 status = "disabled"; 848 849 u2phy_otg: otg-port { 850 #phy-cells = <0>; 851 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 854 interrupt-names = "otg-bvalid", "otg-id", 855 "linestate"; 856 status = "disabled"; 857 }; 858 859 u2phy_host: host-port { 860 #phy-cells = <0>; 861 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "linestate"; 863 status = "disabled"; 864 }; 865 }; 866 }; 867 868 sdmmc: mmc@ff500000 { 869 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 870 reg = <0x0 0xff500000 0x0 0x4000>; 871 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 873 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 874 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 875 fifo-depth = <0x100>; 876 max-frequency = <150000000>; 877 status = "disabled"; 878 }; 879 880 sdio: mmc@ff510000 { 881 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 882 reg = <0x0 0xff510000 0x0 0x4000>; 883 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 885 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 886 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 887 fifo-depth = <0x100>; 888 max-frequency = <150000000>; 889 status = "disabled"; 890 }; 891 892 emmc: mmc@ff520000 { 893 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 894 reg = <0x0 0xff520000 0x0 0x4000>; 895 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 897 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 898 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 899 fifo-depth = <0x100>; 900 max-frequency = <150000000>; 901 status = "disabled"; 902 }; 903 904 gmac2io: ethernet@ff540000 { 905 compatible = "rockchip,rk3328-gmac"; 906 reg = <0x0 0xff540000 0x0 0x10000>; 907 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 910 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 911 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 912 <&cru PCLK_MAC2IO>; 913 clock-names = "stmmaceth", "mac_clk_rx", 914 "mac_clk_tx", "clk_mac_ref", 915 "clk_mac_refout", "aclk_mac", 916 "pclk_mac"; 917 resets = <&cru SRST_GMAC2IO_A>; 918 reset-names = "stmmaceth"; 919 rockchip,grf = <&grf>; 920 tx-fifo-depth = <2048>; 921 rx-fifo-depth = <4096>; 922 snps,txpbl = <0x4>; 923 status = "disabled"; 924 }; 925 926 gmac2phy: ethernet@ff550000 { 927 compatible = "rockchip,rk3328-gmac"; 928 reg = <0x0 0xff550000 0x0 0x10000>; 929 rockchip,grf = <&grf>; 930 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "macirq"; 932 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 933 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 934 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 935 <&cru SCLK_MAC2PHY_OUT>; 936 clock-names = "stmmaceth", "mac_clk_rx", 937 "mac_clk_tx", "clk_mac_ref", 938 "aclk_mac", "pclk_mac", 939 "clk_macphy"; 940 resets = <&cru SRST_GMAC2PHY_A>; 941 reset-names = "stmmaceth"; 942 phy-mode = "rmii"; 943 phy-handle = <&phy>; 944 tx-fifo-depth = <2048>; 945 rx-fifo-depth = <4096>; 946 snps,txpbl = <0x4>; 947 clock_in_out = "output"; 948 status = "disabled"; 949 950 mdio { 951 compatible = "snps,dwmac-mdio"; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 phy: ethernet-phy@0 { 956 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 957 reg = <0>; 958 clocks = <&cru SCLK_MAC2PHY_OUT>; 959 resets = <&cru SRST_MACPHY>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 962 phy-is-integrated; 963 }; 964 }; 965 }; 966 967 usb20_otg: usb@ff580000 { 968 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 969 "snps,dwc2"; 970 reg = <0x0 0xff580000 0x0 0x40000>; 971 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru HCLK_OTG>; 973 clock-names = "otg"; 974 dr_mode = "otg"; 975 g-np-tx-fifo-size = <16>; 976 g-rx-fifo-size = <280>; 977 g-tx-fifo-size = <256 128 128 64 32 16>; 978 phys = <&u2phy_otg>; 979 phy-names = "usb2-phy"; 980 status = "disabled"; 981 }; 982 983 usb_host0_ehci: usb@ff5c0000 { 984 compatible = "generic-ehci"; 985 reg = <0x0 0xff5c0000 0x0 0x10000>; 986 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cru HCLK_HOST0>, <&u2phy>; 988 phys = <&u2phy_host>; 989 phy-names = "usb"; 990 status = "disabled"; 991 }; 992 993 usb_host0_ohci: usb@ff5d0000 { 994 compatible = "generic-ohci"; 995 reg = <0x0 0xff5d0000 0x0 0x10000>; 996 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru HCLK_HOST0>, <&u2phy>; 998 phys = <&u2phy_host>; 999 phy-names = "usb"; 1000 status = "disabled"; 1001 }; 1002 1003 usbdrd3: usb@ff600000 { 1004 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1005 reg = <0x0 0xff600000 0x0 0x100000>; 1006 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1008 <&cru ACLK_USB3OTG>; 1009 clock-names = "ref_clk", "suspend_clk", 1010 "bus_clk"; 1011 dr_mode = "otg"; 1012 phy_type = "utmi_wide"; 1013 snps,dis-del-phy-power-chg-quirk; 1014 snps,dis_enblslpm_quirk; 1015 snps,dis-tx-ipgap-linecheck-quirk; 1016 snps,dis-u2-freeclk-exists-quirk; 1017 snps,dis_u2_susphy_quirk; 1018 snps,dis_u3_susphy_quirk; 1019 status = "disabled"; 1020 }; 1021 1022 gic: interrupt-controller@ff811000 { 1023 compatible = "arm,gic-400"; 1024 #interrupt-cells = <3>; 1025 #address-cells = <0>; 1026 interrupt-controller; 1027 reg = <0x0 0xff811000 0 0x1000>, 1028 <0x0 0xff812000 0 0x2000>, 1029 <0x0 0xff814000 0 0x2000>, 1030 <0x0 0xff816000 0 0x2000>; 1031 interrupts = <GIC_PPI 9 1032 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1033 }; 1034 1035 crypto: crypto@ff060000 { 1036 compatible = "rockchip,rk3328-crypto"; 1037 reg = <0x0 0xff060000 0x0 0x4000>; 1038 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1040 <&cru SCLK_CRYPTO>; 1041 clock-names = "hclk_master", "hclk_slave", "sclk"; 1042 resets = <&cru SRST_CRYPTO>; 1043 reset-names = "crypto-rst"; 1044 }; 1045 1046 pinctrl: pinctrl { 1047 compatible = "rockchip,rk3328-pinctrl"; 1048 rockchip,grf = <&grf>; 1049 #address-cells = <2>; 1050 #size-cells = <2>; 1051 ranges; 1052 1053 gpio0: gpio@ff210000 { 1054 compatible = "rockchip,gpio-bank"; 1055 reg = <0x0 0xff210000 0x0 0x100>; 1056 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&cru PCLK_GPIO0>; 1058 1059 gpio-controller; 1060 #gpio-cells = <2>; 1061 1062 interrupt-controller; 1063 #interrupt-cells = <2>; 1064 }; 1065 1066 gpio1: gpio@ff220000 { 1067 compatible = "rockchip,gpio-bank"; 1068 reg = <0x0 0xff220000 0x0 0x100>; 1069 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru PCLK_GPIO1>; 1071 1072 gpio-controller; 1073 #gpio-cells = <2>; 1074 1075 interrupt-controller; 1076 #interrupt-cells = <2>; 1077 }; 1078 1079 gpio2: gpio@ff230000 { 1080 compatible = "rockchip,gpio-bank"; 1081 reg = <0x0 0xff230000 0x0 0x100>; 1082 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&cru PCLK_GPIO2>; 1084 1085 gpio-controller; 1086 #gpio-cells = <2>; 1087 1088 interrupt-controller; 1089 #interrupt-cells = <2>; 1090 }; 1091 1092 gpio3: gpio@ff240000 { 1093 compatible = "rockchip,gpio-bank"; 1094 reg = <0x0 0xff240000 0x0 0x100>; 1095 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cru PCLK_GPIO3>; 1097 1098 gpio-controller; 1099 #gpio-cells = <2>; 1100 1101 interrupt-controller; 1102 #interrupt-cells = <2>; 1103 }; 1104 1105 pcfg_pull_up: pcfg-pull-up { 1106 bias-pull-up; 1107 }; 1108 1109 pcfg_pull_down: pcfg-pull-down { 1110 bias-pull-down; 1111 }; 1112 1113 pcfg_pull_none: pcfg-pull-none { 1114 bias-disable; 1115 }; 1116 1117 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1118 bias-disable; 1119 drive-strength = <2>; 1120 }; 1121 1122 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1123 bias-pull-up; 1124 drive-strength = <2>; 1125 }; 1126 1127 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1128 bias-pull-up; 1129 drive-strength = <4>; 1130 }; 1131 1132 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1133 bias-disable; 1134 drive-strength = <4>; 1135 }; 1136 1137 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1138 bias-pull-down; 1139 drive-strength = <4>; 1140 }; 1141 1142 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1143 bias-disable; 1144 drive-strength = <8>; 1145 }; 1146 1147 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1148 bias-pull-up; 1149 drive-strength = <8>; 1150 }; 1151 1152 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1153 bias-disable; 1154 drive-strength = <12>; 1155 }; 1156 1157 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1158 bias-pull-up; 1159 drive-strength = <12>; 1160 }; 1161 1162 pcfg_output_high: pcfg-output-high { 1163 output-high; 1164 }; 1165 1166 pcfg_output_low: pcfg-output-low { 1167 output-low; 1168 }; 1169 1170 pcfg_input_high: pcfg-input-high { 1171 bias-pull-up; 1172 input-enable; 1173 }; 1174 1175 pcfg_input: pcfg-input { 1176 input-enable; 1177 }; 1178 1179 i2c0 { 1180 i2c0_xfer: i2c0-xfer { 1181 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1182 <2 RK_PD1 1 &pcfg_pull_none>; 1183 }; 1184 }; 1185 1186 i2c1 { 1187 i2c1_xfer: i2c1-xfer { 1188 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1189 <2 RK_PA5 2 &pcfg_pull_none>; 1190 }; 1191 }; 1192 1193 i2c2 { 1194 i2c2_xfer: i2c2-xfer { 1195 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1196 <2 RK_PB6 1 &pcfg_pull_none>; 1197 }; 1198 }; 1199 1200 i2c3 { 1201 i2c3_xfer: i2c3-xfer { 1202 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1203 <0 RK_PA6 2 &pcfg_pull_none>; 1204 }; 1205 i2c3_pins: i2c3-pins { 1206 rockchip,pins = 1207 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1208 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1209 }; 1210 }; 1211 1212 hdmi_i2c { 1213 hdmii2c_xfer: hdmii2c-xfer { 1214 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1215 <0 RK_PA6 1 &pcfg_pull_none>; 1216 }; 1217 }; 1218 1219 pdm-0 { 1220 pdmm0_clk: pdmm0-clk { 1221 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1222 }; 1223 1224 pdmm0_fsync: pdmm0-fsync { 1225 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1226 }; 1227 1228 pdmm0_sdi0: pdmm0-sdi0 { 1229 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1230 }; 1231 1232 pdmm0_sdi1: pdmm0-sdi1 { 1233 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1234 }; 1235 1236 pdmm0_sdi2: pdmm0-sdi2 { 1237 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1238 }; 1239 1240 pdmm0_sdi3: pdmm0-sdi3 { 1241 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1242 }; 1243 1244 pdmm0_clk_sleep: pdmm0-clk-sleep { 1245 rockchip,pins = 1246 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1247 }; 1248 1249 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1250 rockchip,pins = 1251 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1252 }; 1253 1254 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1255 rockchip,pins = 1256 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1257 }; 1258 1259 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1260 rockchip,pins = 1261 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1262 }; 1263 1264 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1265 rockchip,pins = 1266 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1267 }; 1268 1269 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1270 rockchip,pins = 1271 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1272 }; 1273 }; 1274 1275 tsadc { 1276 otp_pin: otp-pin { 1277 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1278 }; 1279 1280 otp_out: otp-out { 1281 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1282 }; 1283 }; 1284 1285 uart0 { 1286 uart0_xfer: uart0-xfer { 1287 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1288 <1 RK_PB0 1 &pcfg_pull_up>; 1289 }; 1290 1291 uart0_cts: uart0-cts { 1292 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1293 }; 1294 1295 uart0_rts: uart0-rts { 1296 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1297 }; 1298 1299 uart0_rts_pin: uart0-rts-pin { 1300 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1301 }; 1302 }; 1303 1304 uart1 { 1305 uart1_xfer: uart1-xfer { 1306 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1307 <3 RK_PA6 4 &pcfg_pull_up>; 1308 }; 1309 1310 uart1_cts: uart1-cts { 1311 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1312 }; 1313 1314 uart1_rts: uart1-rts { 1315 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1316 }; 1317 1318 uart1_rts_pin: uart1-rts-pin { 1319 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1320 }; 1321 }; 1322 1323 uart2-0 { 1324 uart2m0_xfer: uart2m0-xfer { 1325 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1326 <1 RK_PA1 2 &pcfg_pull_up>; 1327 }; 1328 }; 1329 1330 uart2-1 { 1331 uart2m1_xfer: uart2m1-xfer { 1332 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1333 <2 RK_PA1 1 &pcfg_pull_up>; 1334 }; 1335 }; 1336 1337 spi0-0 { 1338 spi0m0_clk: spi0m0-clk { 1339 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1340 }; 1341 1342 spi0m0_cs0: spi0m0-cs0 { 1343 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1344 }; 1345 1346 spi0m0_tx: spi0m0-tx { 1347 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1348 }; 1349 1350 spi0m0_rx: spi0m0-rx { 1351 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1352 }; 1353 1354 spi0m0_cs1: spi0m0-cs1 { 1355 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1356 }; 1357 }; 1358 1359 spi0-1 { 1360 spi0m1_clk: spi0m1-clk { 1361 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1362 }; 1363 1364 spi0m1_cs0: spi0m1-cs0 { 1365 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1366 }; 1367 1368 spi0m1_tx: spi0m1-tx { 1369 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1370 }; 1371 1372 spi0m1_rx: spi0m1-rx { 1373 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1374 }; 1375 1376 spi0m1_cs1: spi0m1-cs1 { 1377 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1378 }; 1379 }; 1380 1381 spi0-2 { 1382 spi0m2_clk: spi0m2-clk { 1383 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1384 }; 1385 1386 spi0m2_cs0: spi0m2-cs0 { 1387 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1388 }; 1389 1390 spi0m2_tx: spi0m2-tx { 1391 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1392 }; 1393 1394 spi0m2_rx: spi0m2-rx { 1395 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1396 }; 1397 }; 1398 1399 i2s1 { 1400 i2s1_mclk: i2s1-mclk { 1401 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1402 }; 1403 1404 i2s1_sclk: i2s1-sclk { 1405 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1406 }; 1407 1408 i2s1_lrckrx: i2s1-lrckrx { 1409 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1410 }; 1411 1412 i2s1_lrcktx: i2s1-lrcktx { 1413 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1414 }; 1415 1416 i2s1_sdi: i2s1-sdi { 1417 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1418 }; 1419 1420 i2s1_sdo: i2s1-sdo { 1421 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1422 }; 1423 1424 i2s1_sdio1: i2s1-sdio1 { 1425 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1426 }; 1427 1428 i2s1_sdio2: i2s1-sdio2 { 1429 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1430 }; 1431 1432 i2s1_sdio3: i2s1-sdio3 { 1433 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1434 }; 1435 1436 i2s1_sleep: i2s1-sleep { 1437 rockchip,pins = 1438 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1439 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1440 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1441 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1442 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1443 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1444 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1445 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1446 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1447 }; 1448 }; 1449 1450 i2s2-0 { 1451 i2s2m0_mclk: i2s2m0-mclk { 1452 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1453 }; 1454 1455 i2s2m0_sclk: i2s2m0-sclk { 1456 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1457 }; 1458 1459 i2s2m0_lrckrx: i2s2m0-lrckrx { 1460 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1461 }; 1462 1463 i2s2m0_lrcktx: i2s2m0-lrcktx { 1464 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1465 }; 1466 1467 i2s2m0_sdi: i2s2m0-sdi { 1468 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1469 }; 1470 1471 i2s2m0_sdo: i2s2m0-sdo { 1472 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1473 }; 1474 1475 i2s2m0_sleep: i2s2m0-sleep { 1476 rockchip,pins = 1477 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1478 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1479 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1480 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1481 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1482 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1483 }; 1484 }; 1485 1486 i2s2-1 { 1487 i2s2m1_mclk: i2s2m1-mclk { 1488 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1489 }; 1490 1491 i2s2m1_sclk: i2s2m1-sclk { 1492 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1493 }; 1494 1495 i2s2m1_lrckrx: i2sm1-lrckrx { 1496 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1497 }; 1498 1499 i2s2m1_lrcktx: i2s2m1-lrcktx { 1500 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1501 }; 1502 1503 i2s2m1_sdi: i2s2m1-sdi { 1504 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1505 }; 1506 1507 i2s2m1_sdo: i2s2m1-sdo { 1508 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1509 }; 1510 1511 i2s2m1_sleep: i2s2m1-sleep { 1512 rockchip,pins = 1513 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1514 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1515 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1516 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1517 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1518 }; 1519 }; 1520 1521 spdif-0 { 1522 spdifm0_tx: spdifm0-tx { 1523 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1524 }; 1525 }; 1526 1527 spdif-1 { 1528 spdifm1_tx: spdifm1-tx { 1529 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1530 }; 1531 }; 1532 1533 spdif-2 { 1534 spdifm2_tx: spdifm2-tx { 1535 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1536 }; 1537 }; 1538 1539 sdmmc0-0 { 1540 sdmmc0m0_pwren: sdmmc0m0-pwren { 1541 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1542 }; 1543 1544 sdmmc0m0_pin: sdmmc0m0-pin { 1545 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1546 }; 1547 }; 1548 1549 sdmmc0-1 { 1550 sdmmc0m1_pwren: sdmmc0m1-pwren { 1551 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1552 }; 1553 1554 sdmmc0m1_pin: sdmmc0m1-pin { 1555 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1556 }; 1557 }; 1558 1559 sdmmc0 { 1560 sdmmc0_clk: sdmmc0-clk { 1561 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1562 }; 1563 1564 sdmmc0_cmd: sdmmc0-cmd { 1565 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1566 }; 1567 1568 sdmmc0_dectn: sdmmc0-dectn { 1569 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1570 }; 1571 1572 sdmmc0_wrprt: sdmmc0-wrprt { 1573 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1574 }; 1575 1576 sdmmc0_bus1: sdmmc0-bus1 { 1577 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1578 }; 1579 1580 sdmmc0_bus4: sdmmc0-bus4 { 1581 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1582 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1583 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1584 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1585 }; 1586 1587 sdmmc0_pins: sdmmc0-pins { 1588 rockchip,pins = 1589 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1591 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1592 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1593 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1594 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1595 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1596 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1597 }; 1598 }; 1599 1600 sdmmc0ext { 1601 sdmmc0ext_clk: sdmmc0ext-clk { 1602 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1603 }; 1604 1605 sdmmc0ext_cmd: sdmmc0ext-cmd { 1606 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1607 }; 1608 1609 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1610 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1611 }; 1612 1613 sdmmc0ext_dectn: sdmmc0ext-dectn { 1614 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1615 }; 1616 1617 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1618 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1619 }; 1620 1621 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1622 rockchip,pins = 1623 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1624 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1625 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1626 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1627 }; 1628 1629 sdmmc0ext_pins: sdmmc0ext-pins { 1630 rockchip,pins = 1631 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1632 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1633 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1634 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1635 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1637 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1638 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1639 }; 1640 }; 1641 1642 sdmmc1 { 1643 sdmmc1_clk: sdmmc1-clk { 1644 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1645 }; 1646 1647 sdmmc1_cmd: sdmmc1-cmd { 1648 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1649 }; 1650 1651 sdmmc1_pwren: sdmmc1-pwren { 1652 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1653 }; 1654 1655 sdmmc1_wrprt: sdmmc1-wrprt { 1656 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1657 }; 1658 1659 sdmmc1_dectn: sdmmc1-dectn { 1660 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1661 }; 1662 1663 sdmmc1_bus1: sdmmc1-bus1 { 1664 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1665 }; 1666 1667 sdmmc1_bus4: sdmmc1-bus4 { 1668 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1669 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1670 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1671 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1672 }; 1673 1674 sdmmc1_pins: sdmmc1-pins { 1675 rockchip,pins = 1676 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1677 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1678 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1679 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1680 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1681 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1682 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1683 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1684 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1685 }; 1686 }; 1687 1688 emmc { 1689 emmc_clk: emmc-clk { 1690 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1691 }; 1692 1693 emmc_cmd: emmc-cmd { 1694 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1695 }; 1696 1697 emmc_pwren: emmc-pwren { 1698 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1699 }; 1700 1701 emmc_rstnout: emmc-rstnout { 1702 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1703 }; 1704 1705 emmc_bus1: emmc-bus1 { 1706 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1707 }; 1708 1709 emmc_bus4: emmc-bus4 { 1710 rockchip,pins = 1711 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1712 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1713 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1714 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1715 }; 1716 1717 emmc_bus8: emmc-bus8 { 1718 rockchip,pins = 1719 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1720 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1721 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1722 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1723 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1724 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1725 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1726 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1727 }; 1728 }; 1729 1730 pwm0 { 1731 pwm0_pin: pwm0-pin { 1732 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1733 }; 1734 }; 1735 1736 pwm1 { 1737 pwm1_pin: pwm1-pin { 1738 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1739 }; 1740 }; 1741 1742 pwm2 { 1743 pwm2_pin: pwm2-pin { 1744 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1745 }; 1746 }; 1747 1748 pwmir { 1749 pwmir_pin: pwmir-pin { 1750 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1751 }; 1752 }; 1753 1754 gmac-1 { 1755 rgmiim1_pins: rgmiim1-pins { 1756 rockchip,pins = 1757 /* mac_txclk */ 1758 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1759 /* mac_rxclk */ 1760 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1761 /* mac_mdio */ 1762 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1763 /* mac_txen */ 1764 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1765 /* mac_clk */ 1766 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1767 /* mac_rxdv */ 1768 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1769 /* mac_mdc */ 1770 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1771 /* mac_rxd1 */ 1772 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1773 /* mac_rxd0 */ 1774 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1775 /* mac_txd1 */ 1776 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1777 /* mac_txd0 */ 1778 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1779 /* mac_rxd3 */ 1780 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1781 /* mac_rxd2 */ 1782 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1783 /* mac_txd3 */ 1784 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1785 /* mac_txd2 */ 1786 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1787 1788 /* mac_txclk */ 1789 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1790 /* mac_txen */ 1791 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1792 /* mac_clk */ 1793 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1794 /* mac_txd1 */ 1795 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1796 /* mac_txd0 */ 1797 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1798 /* mac_txd3 */ 1799 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1800 /* mac_txd2 */ 1801 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1802 }; 1803 1804 rmiim1_pins: rmiim1-pins { 1805 rockchip,pins = 1806 /* mac_mdio */ 1807 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1808 /* mac_txen */ 1809 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1810 /* mac_clk */ 1811 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1812 /* mac_rxer */ 1813 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1814 /* mac_rxdv */ 1815 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1816 /* mac_mdc */ 1817 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1818 /* mac_rxd1 */ 1819 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1820 /* mac_rxd0 */ 1821 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1822 /* mac_txd1 */ 1823 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1824 /* mac_txd0 */ 1825 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1826 1827 /* mac_mdio */ 1828 <0 RK_PB3 1 &pcfg_pull_none>, 1829 /* mac_txen */ 1830 <0 RK_PB4 1 &pcfg_pull_none>, 1831 /* mac_clk */ 1832 <0 RK_PD0 1 &pcfg_pull_none>, 1833 /* mac_mdc */ 1834 <0 RK_PC3 1 &pcfg_pull_none>, 1835 /* mac_txd1 */ 1836 <0 RK_PC0 1 &pcfg_pull_none>, 1837 /* mac_txd0 */ 1838 <0 RK_PC1 1 &pcfg_pull_none>; 1839 }; 1840 }; 1841 1842 gmac2phy { 1843 fephyled_speed10: fephyled-speed10 { 1844 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1845 }; 1846 1847 fephyled_duplex: fephyled-duplex { 1848 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1849 }; 1850 1851 fephyled_rxm1: fephyled-rxm1 { 1852 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1853 }; 1854 1855 fephyled_txm1: fephyled-txm1 { 1856 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1857 }; 1858 1859 fephyled_linkm1: fephyled-linkm1 { 1860 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1861 }; 1862 }; 1863 1864 tsadc_pin { 1865 tsadc_int: tsadc-int { 1866 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1867 }; 1868 tsadc_pin: tsadc-pin { 1869 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1870 }; 1871 }; 1872 1873 hdmi_pin { 1874 hdmi_cec: hdmi-cec { 1875 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1876 }; 1877 1878 hdmi_hpd: hdmi-hpd { 1879 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1880 }; 1881 }; 1882 1883 cif-0 { 1884 dvp_d2d9_m0:dvp-d2d9-m0 { 1885 rockchip,pins = 1886 /* cif_d0 */ 1887 <3 RK_PA4 2 &pcfg_pull_none>, 1888 /* cif_d1 */ 1889 <3 RK_PA5 2 &pcfg_pull_none>, 1890 /* cif_d2 */ 1891 <3 RK_PA6 2 &pcfg_pull_none>, 1892 /* cif_d3 */ 1893 <3 RK_PA7 2 &pcfg_pull_none>, 1894 /* cif_d4 */ 1895 <3 RK_PB0 2 &pcfg_pull_none>, 1896 /* cif_d5m0 */ 1897 <3 RK_PB1 2 &pcfg_pull_none>, 1898 /* cif_d6m0 */ 1899 <3 RK_PB2 2 &pcfg_pull_none>, 1900 /* cif_d7m0 */ 1901 <3 RK_PB3 2 &pcfg_pull_none>, 1902 /* cif_href */ 1903 <3 RK_PA1 2 &pcfg_pull_none>, 1904 /* cif_vsync */ 1905 <3 RK_PA0 2 &pcfg_pull_none>, 1906 /* cif_clkoutm0 */ 1907 <3 RK_PA3 2 &pcfg_pull_none>, 1908 /* cif_clkin */ 1909 <3 RK_PA2 2 &pcfg_pull_none>; 1910 }; 1911 }; 1912 1913 cif-1 { 1914 dvp_d2d9_m1:dvp-d2d9-m1 { 1915 rockchip,pins = 1916 /* cif_d0 */ 1917 <3 RK_PA4 2 &pcfg_pull_none>, 1918 /* cif_d1 */ 1919 <3 RK_PA5 2 &pcfg_pull_none>, 1920 /* cif_d2 */ 1921 <3 RK_PA6 2 &pcfg_pull_none>, 1922 /* cif_d3 */ 1923 <3 RK_PA7 2 &pcfg_pull_none>, 1924 /* cif_d4 */ 1925 <3 RK_PB0 2 &pcfg_pull_none>, 1926 /* cif_d5m1 */ 1927 <2 RK_PC0 4 &pcfg_pull_none>, 1928 /* cif_d6m1 */ 1929 <2 RK_PC1 4 &pcfg_pull_none>, 1930 /* cif_d7m1 */ 1931 <2 RK_PC2 4 &pcfg_pull_none>, 1932 /* cif_href */ 1933 <3 RK_PA1 2 &pcfg_pull_none>, 1934 /* cif_vsync */ 1935 <3 RK_PA0 2 &pcfg_pull_none>, 1936 /* cif_clkoutm1 */ 1937 <2 RK_PB7 4 &pcfg_pull_none>, 1938 /* cif_clkin */ 1939 <3 RK_PA2 2 &pcfg_pull_none>; 1940 }; 1941 }; 1942 }; 1943}; 1944