1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 74 #include "miibus_if.h" 75 76 #include "if_aereg.h" 77 #include "if_aevar.h" 78 79 /* 80 * Devices supported by this driver. 81 */ 82 static struct ae_dev { 83 uint16_t vendorid; 84 uint16_t deviceid; 85 const char *name; 86 } ae_devs[] = { 87 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 88 "Attansic Technology Corp, L2 FastEthernet" }, 89 }; 90 #define AE_DEVS_COUNT nitems(ae_devs) 91 92 static struct resource_spec ae_res_spec_mem[] = { 93 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 94 { -1, 0, 0 } 95 }; 96 static struct resource_spec ae_res_spec_irq[] = { 97 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 98 { -1, 0, 0 } 99 }; 100 static struct resource_spec ae_res_spec_msi[] = { 101 { SYS_RES_IRQ, 1, RF_ACTIVE }, 102 { -1, 0, 0 } 103 }; 104 105 static int ae_probe(device_t dev); 106 static int ae_attach(device_t dev); 107 static void ae_pcie_init(ae_softc_t *sc); 108 static void ae_phy_reset(ae_softc_t *sc); 109 static void ae_phy_init(ae_softc_t *sc); 110 static int ae_reset(ae_softc_t *sc); 111 static void ae_init(void *arg); 112 static int ae_init_locked(ae_softc_t *sc); 113 static int ae_detach(device_t dev); 114 static int ae_miibus_readreg(device_t dev, int phy, int reg); 115 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 116 static void ae_miibus_statchg(device_t dev); 117 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 118 static int ae_mediachange(struct ifnet *ifp); 119 static void ae_retrieve_address(ae_softc_t *sc); 120 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 121 int error); 122 static int ae_alloc_rings(ae_softc_t *sc); 123 static void ae_dma_free(ae_softc_t *sc); 124 static int ae_shutdown(device_t dev); 125 static int ae_suspend(device_t dev); 126 static void ae_powersave_disable(ae_softc_t *sc); 127 static void ae_powersave_enable(ae_softc_t *sc); 128 static int ae_resume(device_t dev); 129 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 130 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 131 static void ae_start(struct ifnet *ifp); 132 static void ae_start_locked(struct ifnet *ifp); 133 static void ae_link_task(void *arg, int pending); 134 static void ae_stop_rxmac(ae_softc_t *sc); 135 static void ae_stop_txmac(ae_softc_t *sc); 136 static void ae_mac_config(ae_softc_t *sc); 137 static int ae_intr(void *arg); 138 static void ae_int_task(void *arg, int pending); 139 static void ae_tx_intr(ae_softc_t *sc); 140 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 141 static void ae_rx_intr(ae_softc_t *sc); 142 static void ae_watchdog(ae_softc_t *sc); 143 static void ae_tick(void *arg); 144 static void ae_rxfilter(ae_softc_t *sc); 145 static void ae_rxvlan(ae_softc_t *sc); 146 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 147 static void ae_stop(ae_softc_t *sc); 148 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 149 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 150 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 151 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 152 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 153 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 154 static void ae_init_tunables(ae_softc_t *sc); 155 156 static device_method_t ae_methods[] = { 157 /* Device interface. */ 158 DEVMETHOD(device_probe, ae_probe), 159 DEVMETHOD(device_attach, ae_attach), 160 DEVMETHOD(device_detach, ae_detach), 161 DEVMETHOD(device_shutdown, ae_shutdown), 162 DEVMETHOD(device_suspend, ae_suspend), 163 DEVMETHOD(device_resume, ae_resume), 164 165 /* MII interface. */ 166 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 169 170 { NULL, NULL } 171 }; 172 static driver_t ae_driver = { 173 "ae", 174 ae_methods, 175 sizeof(ae_softc_t) 176 }; 177 static devclass_t ae_devclass; 178 179 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 180 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 181 nitems(ae_devs)); 182 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 183 MODULE_DEPEND(ae, pci, 1, 1, 1); 184 MODULE_DEPEND(ae, ether, 1, 1, 1); 185 MODULE_DEPEND(ae, miibus, 1, 1, 1); 186 187 /* 188 * Tunables. 189 */ 190 static int msi_disable = 0; 191 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 192 193 #define AE_READ_4(sc, reg) \ 194 bus_read_4((sc)->mem[0], (reg)) 195 #define AE_READ_2(sc, reg) \ 196 bus_read_2((sc)->mem[0], (reg)) 197 #define AE_READ_1(sc, reg) \ 198 bus_read_1((sc)->mem[0], (reg)) 199 #define AE_WRITE_4(sc, reg, val) \ 200 bus_write_4((sc)->mem[0], (reg), (val)) 201 #define AE_WRITE_2(sc, reg, val) \ 202 bus_write_2((sc)->mem[0], (reg), (val)) 203 #define AE_WRITE_1(sc, reg, val) \ 204 bus_write_1((sc)->mem[0], (reg), (val)) 205 #define AE_PHY_READ(sc, reg) \ 206 ae_miibus_readreg(sc->dev, 0, reg) 207 #define AE_PHY_WRITE(sc, reg, val) \ 208 ae_miibus_writereg(sc->dev, 0, reg, val) 209 #define AE_CHECK_EADDR_VALID(eaddr) \ 210 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 211 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 212 #define AE_RXD_VLAN(vtag) \ 213 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 214 #define AE_TXD_VLAN(vtag) \ 215 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 216 217 static int 218 ae_probe(device_t dev) 219 { 220 uint16_t deviceid, vendorid; 221 int i; 222 223 vendorid = pci_get_vendor(dev); 224 deviceid = pci_get_device(dev); 225 226 /* 227 * Search through the list of supported devs for matching one. 228 */ 229 for (i = 0; i < AE_DEVS_COUNT; i++) { 230 if (vendorid == ae_devs[i].vendorid && 231 deviceid == ae_devs[i].deviceid) { 232 device_set_desc(dev, ae_devs[i].name); 233 return (BUS_PROBE_DEFAULT); 234 } 235 } 236 return (ENXIO); 237 } 238 239 static int 240 ae_attach(device_t dev) 241 { 242 ae_softc_t *sc; 243 struct ifnet *ifp; 244 uint8_t chiprev; 245 uint32_t pcirev; 246 int nmsi, pmc; 247 int error; 248 249 sc = device_get_softc(dev); /* Automatically allocated and zeroed 250 on attach. */ 251 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 252 sc->dev = dev; 253 254 /* 255 * Initialize mutexes and tasks. 256 */ 257 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 258 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 259 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 260 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 261 262 pci_enable_busmaster(dev); /* Enable bus mastering. */ 263 264 sc->spec_mem = ae_res_spec_mem; 265 266 /* 267 * Allocate memory-mapped registers. 268 */ 269 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 270 if (error != 0) { 271 device_printf(dev, "could not allocate memory resources.\n"); 272 sc->spec_mem = NULL; 273 goto fail; 274 } 275 276 /* 277 * Retrieve PCI and chip revisions. 278 */ 279 pcirev = pci_get_revid(dev); 280 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 281 AE_MASTER_REVNUM_MASK; 282 if (bootverbose) { 283 device_printf(dev, "pci device revision: %#04x\n", pcirev); 284 device_printf(dev, "chip id: %#02x\n", chiprev); 285 } 286 nmsi = pci_msi_count(dev); 287 if (bootverbose) 288 device_printf(dev, "MSI count: %d.\n", nmsi); 289 290 /* 291 * Allocate interrupt resources. 292 */ 293 if (msi_disable == 0 && nmsi == 1) { 294 error = pci_alloc_msi(dev, &nmsi); 295 if (error == 0) { 296 device_printf(dev, "Using MSI messages.\n"); 297 sc->spec_irq = ae_res_spec_msi; 298 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 299 if (error != 0) { 300 device_printf(dev, "MSI allocation failed.\n"); 301 sc->spec_irq = NULL; 302 pci_release_msi(dev); 303 } else { 304 sc->flags |= AE_FLAG_MSI; 305 } 306 } 307 } 308 if (sc->spec_irq == NULL) { 309 sc->spec_irq = ae_res_spec_irq; 310 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 311 if (error != 0) { 312 device_printf(dev, "could not allocate IRQ resources.\n"); 313 sc->spec_irq = NULL; 314 goto fail; 315 } 316 } 317 318 ae_init_tunables(sc); 319 320 ae_phy_reset(sc); /* Reset PHY. */ 321 error = ae_reset(sc); /* Reset the controller itself. */ 322 if (error != 0) 323 goto fail; 324 325 ae_pcie_init(sc); 326 327 ae_retrieve_address(sc); /* Load MAC address. */ 328 329 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 330 if (error != 0) 331 goto fail; 332 333 ifp = sc->ifp = if_alloc(IFT_ETHER); 334 if (ifp == NULL) { 335 device_printf(dev, "could not allocate ifnet structure.\n"); 336 error = ENXIO; 337 goto fail; 338 } 339 340 ifp->if_softc = sc; 341 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 343 ifp->if_ioctl = ae_ioctl; 344 ifp->if_start = ae_start; 345 ifp->if_init = ae_init; 346 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 347 ifp->if_hwassist = 0; 348 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 349 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 350 IFQ_SET_READY(&ifp->if_snd); 351 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 352 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 353 sc->flags |= AE_FLAG_PMG; 354 } 355 ifp->if_capenable = ifp->if_capabilities; 356 357 /* 358 * Configure and attach MII bus. 359 */ 360 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 361 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 362 MII_OFFSET_ANY, 0); 363 if (error != 0) { 364 device_printf(dev, "attaching PHYs failed\n"); 365 goto fail; 366 } 367 368 ether_ifattach(ifp, sc->eaddr); 369 /* Tell the upper layer(s) we support long frames. */ 370 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 371 372 /* 373 * Create and run all helper tasks. 374 */ 375 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 376 taskqueue_thread_enqueue, &sc->tq); 377 if (sc->tq == NULL) { 378 device_printf(dev, "could not create taskqueue.\n"); 379 ether_ifdetach(ifp); 380 error = ENXIO; 381 goto fail; 382 } 383 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 384 device_get_nameunit(sc->dev)); 385 386 /* 387 * Configure interrupt handlers. 388 */ 389 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 390 ae_intr, NULL, sc, &sc->intrhand); 391 if (error != 0) { 392 device_printf(dev, "could not set up interrupt handler.\n"); 393 taskqueue_free(sc->tq); 394 sc->tq = NULL; 395 ether_ifdetach(ifp); 396 goto fail; 397 } 398 399 gone_by_fcp101_dev(dev); 400 401 fail: 402 if (error != 0) 403 ae_detach(dev); 404 405 return (error); 406 } 407 408 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 409 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 410 411 static void 412 ae_init_tunables(ae_softc_t *sc) 413 { 414 struct sysctl_ctx_list *ctx; 415 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 416 struct ae_stats *ae_stats; 417 418 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 419 ae_stats = &sc->stats; 420 421 ctx = device_get_sysctl_ctx(sc->dev); 422 root = device_get_sysctl_tree(sc->dev); 423 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 424 CTLFLAG_RD, NULL, "ae statistics"); 425 426 /* 427 * Receiver statistcics. 428 */ 429 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 430 CTLFLAG_RD, NULL, "Rx MAC statistics"); 431 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 432 "broadcast frames", &ae_stats->rx_bcast); 433 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 434 "multicast frames", &ae_stats->rx_mcast); 435 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 436 "PAUSE frames", &ae_stats->rx_pause); 437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 438 "control frames", &ae_stats->rx_ctrl); 439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 440 "frames with CRC errors", &ae_stats->rx_crcerr); 441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 442 "frames with invalid opcode", &ae_stats->rx_codeerr); 443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 444 "runt frames", &ae_stats->rx_runt); 445 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 446 "fragmented frames", &ae_stats->rx_frag); 447 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 448 "frames with alignment errors", &ae_stats->rx_align); 449 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 450 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 451 452 /* 453 * Receiver statistcics. 454 */ 455 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 456 CTLFLAG_RD, NULL, "Tx MAC statistics"); 457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 458 "broadcast frames", &ae_stats->tx_bcast); 459 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 460 "multicast frames", &ae_stats->tx_mcast); 461 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 462 "PAUSE frames", &ae_stats->tx_pause); 463 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 464 "control frames", &ae_stats->tx_ctrl); 465 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 466 "deferrals occuried", &ae_stats->tx_defer); 467 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 468 "excessive deferrals occuried", &ae_stats->tx_excdefer); 469 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 470 "single collisions occuried", &ae_stats->tx_singlecol); 471 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 472 "multiple collisions occuried", &ae_stats->tx_multicol); 473 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 474 "late collisions occuried", &ae_stats->tx_latecol); 475 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 476 "transmit aborts due collisions", &ae_stats->tx_abortcol); 477 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 478 "Tx FIFO underruns", &ae_stats->tx_underrun); 479 } 480 481 static void 482 ae_pcie_init(ae_softc_t *sc) 483 { 484 485 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 486 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 487 } 488 489 static void 490 ae_phy_reset(ae_softc_t *sc) 491 { 492 493 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 494 DELAY(1000); /* XXX: pause(9) ? */ 495 } 496 497 static int 498 ae_reset(ae_softc_t *sc) 499 { 500 int i; 501 502 /* 503 * Issue a soft reset. 504 */ 505 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 506 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 507 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 508 509 /* 510 * Wait for reset to complete. 511 */ 512 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 513 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 514 break; 515 DELAY(10); 516 } 517 if (i == AE_RESET_TIMEOUT) { 518 device_printf(sc->dev, "reset timeout.\n"); 519 return (ENXIO); 520 } 521 522 /* 523 * Wait for everything to enter idle state. 524 */ 525 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 526 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 527 break; 528 DELAY(100); 529 } 530 if (i == AE_IDLE_TIMEOUT) { 531 device_printf(sc->dev, "could not enter idle state.\n"); 532 return (ENXIO); 533 } 534 return (0); 535 } 536 537 static void 538 ae_init(void *arg) 539 { 540 ae_softc_t *sc; 541 542 sc = (ae_softc_t *)arg; 543 AE_LOCK(sc); 544 ae_init_locked(sc); 545 AE_UNLOCK(sc); 546 } 547 548 static void 549 ae_phy_init(ae_softc_t *sc) 550 { 551 552 /* 553 * Enable link status change interrupt. 554 * XXX magic numbers. 555 */ 556 #ifdef notyet 557 AE_PHY_WRITE(sc, 18, 0xc00); 558 #endif 559 } 560 561 static int 562 ae_init_locked(ae_softc_t *sc) 563 { 564 struct ifnet *ifp; 565 struct mii_data *mii; 566 uint8_t eaddr[ETHER_ADDR_LEN]; 567 uint32_t val; 568 bus_addr_t addr; 569 570 AE_LOCK_ASSERT(sc); 571 572 ifp = sc->ifp; 573 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 574 return (0); 575 mii = device_get_softc(sc->miibus); 576 577 ae_stop(sc); 578 ae_reset(sc); 579 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 580 ae_phy_init(sc); 581 ae_powersave_disable(sc); 582 583 /* 584 * Clear and disable interrupts. 585 */ 586 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 587 588 /* 589 * Set the MAC address. 590 */ 591 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 592 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 593 AE_WRITE_4(sc, AE_EADDR0_REG, val); 594 val = eaddr[0] << 8 | eaddr[1]; 595 AE_WRITE_4(sc, AE_EADDR1_REG, val); 596 597 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 598 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 599 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 600 /* 601 * Set ring buffers base addresses. 602 */ 603 addr = sc->dma_rxd_busaddr; 604 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 605 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 606 addr = sc->dma_txd_busaddr; 607 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 608 addr = sc->dma_txs_busaddr; 609 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 610 611 /* 612 * Configure ring buffers sizes. 613 */ 614 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 615 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 616 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 617 618 /* 619 * Configure interframe gap parameters. 620 */ 621 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 622 AE_IFG_TXIPG_MASK) | 623 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 624 AE_IFG_RXIPG_MASK) | 625 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 626 AE_IFG_IPGR1_MASK) | 627 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 628 AE_IFG_IPGR2_MASK); 629 AE_WRITE_4(sc, AE_IFG_REG, val); 630 631 /* 632 * Configure half-duplex operation. 633 */ 634 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 635 AE_HDPX_LCOL_MASK) | 636 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 637 AE_HDPX_RETRY_MASK) | 638 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 639 AE_HDPX_ABEBT_MASK) | 640 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 641 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 642 AE_WRITE_4(sc, AE_HDPX_REG, val); 643 644 /* 645 * Configure interrupt moderate timer. 646 */ 647 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 648 val = AE_READ_4(sc, AE_MASTER_REG); 649 val |= AE_MASTER_IMT_EN; 650 AE_WRITE_4(sc, AE_MASTER_REG, val); 651 652 /* 653 * Configure interrupt clearing timer. 654 */ 655 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 656 657 /* 658 * Configure MTU. 659 */ 660 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 661 ETHER_CRC_LEN; 662 AE_WRITE_2(sc, AE_MTU_REG, val); 663 664 /* 665 * Configure cut-through threshold. 666 */ 667 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 668 669 /* 670 * Configure flow control. 671 */ 672 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 673 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 674 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 675 (AE_RXD_COUNT_DEFAULT / 12)); 676 677 /* 678 * Init mailboxes. 679 */ 680 sc->txd_cur = sc->rxd_cur = 0; 681 sc->txs_ack = sc->txd_ack = 0; 682 sc->rxd_cur = 0; 683 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 684 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 685 686 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 687 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 688 689 /* 690 * Enable DMA. 691 */ 692 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 693 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 694 695 /* 696 * Check if everything is OK. 697 */ 698 val = AE_READ_4(sc, AE_ISR_REG); 699 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 700 device_printf(sc->dev, "Initialization failed.\n"); 701 return (ENXIO); 702 } 703 704 /* 705 * Clear interrupt status. 706 */ 707 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 708 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 709 710 /* 711 * Enable interrupts. 712 */ 713 val = AE_READ_4(sc, AE_MASTER_REG); 714 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 715 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 716 717 /* 718 * Disable WOL. 719 */ 720 AE_WRITE_4(sc, AE_WOL_REG, 0); 721 722 /* 723 * Configure MAC. 724 */ 725 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 726 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 727 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 728 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 729 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 730 AE_MAC_PREAMBLE_MASK); 731 AE_WRITE_4(sc, AE_MAC_REG, val); 732 733 /* 734 * Configure Rx MAC. 735 */ 736 ae_rxfilter(sc); 737 ae_rxvlan(sc); 738 739 /* 740 * Enable Tx/Rx. 741 */ 742 val = AE_READ_4(sc, AE_MAC_REG); 743 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 744 745 sc->flags &= ~AE_FLAG_LINK; 746 mii_mediachg(mii); /* Switch to the current media. */ 747 748 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 749 750 ifp->if_drv_flags |= IFF_DRV_RUNNING; 751 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 752 753 #ifdef AE_DEBUG 754 device_printf(sc->dev, "Initialization complete.\n"); 755 #endif 756 757 return (0); 758 } 759 760 static int 761 ae_detach(device_t dev) 762 { 763 struct ae_softc *sc; 764 struct ifnet *ifp; 765 766 sc = device_get_softc(dev); 767 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 768 ifp = sc->ifp; 769 if (device_is_attached(dev)) { 770 AE_LOCK(sc); 771 sc->flags |= AE_FLAG_DETACH; 772 ae_stop(sc); 773 AE_UNLOCK(sc); 774 callout_drain(&sc->tick_ch); 775 taskqueue_drain(sc->tq, &sc->int_task); 776 taskqueue_drain(taskqueue_swi, &sc->link_task); 777 ether_ifdetach(ifp); 778 } 779 if (sc->tq != NULL) { 780 taskqueue_drain(sc->tq, &sc->int_task); 781 taskqueue_free(sc->tq); 782 sc->tq = NULL; 783 } 784 if (sc->miibus != NULL) { 785 device_delete_child(dev, sc->miibus); 786 sc->miibus = NULL; 787 } 788 bus_generic_detach(sc->dev); 789 ae_dma_free(sc); 790 if (sc->intrhand != NULL) { 791 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 792 sc->intrhand = NULL; 793 } 794 if (ifp != NULL) { 795 if_free(ifp); 796 sc->ifp = NULL; 797 } 798 if (sc->spec_irq != NULL) 799 bus_release_resources(dev, sc->spec_irq, sc->irq); 800 if (sc->spec_mem != NULL) 801 bus_release_resources(dev, sc->spec_mem, sc->mem); 802 if ((sc->flags & AE_FLAG_MSI) != 0) 803 pci_release_msi(dev); 804 mtx_destroy(&sc->mtx); 805 806 return (0); 807 } 808 809 static int 810 ae_miibus_readreg(device_t dev, int phy, int reg) 811 { 812 ae_softc_t *sc; 813 uint32_t val; 814 int i; 815 816 sc = device_get_softc(dev); 817 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 818 819 /* 820 * Locking is done in upper layers. 821 */ 822 823 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 824 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 825 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 826 AE_WRITE_4(sc, AE_MDIO_REG, val); 827 828 /* 829 * Wait for operation to complete. 830 */ 831 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 832 DELAY(2); 833 val = AE_READ_4(sc, AE_MDIO_REG); 834 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 835 break; 836 } 837 if (i == AE_MDIO_TIMEOUT) { 838 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 839 return (0); 840 } 841 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 842 } 843 844 static int 845 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 846 { 847 ae_softc_t *sc; 848 uint32_t aereg; 849 int i; 850 851 sc = device_get_softc(dev); 852 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 853 854 /* 855 * Locking is done in upper layers. 856 */ 857 858 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 859 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 860 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 861 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 862 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 863 864 /* 865 * Wait for operation to complete. 866 */ 867 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 868 DELAY(2); 869 aereg = AE_READ_4(sc, AE_MDIO_REG); 870 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 871 break; 872 } 873 if (i == AE_MDIO_TIMEOUT) { 874 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 875 } 876 return (0); 877 } 878 879 static void 880 ae_miibus_statchg(device_t dev) 881 { 882 ae_softc_t *sc; 883 884 sc = device_get_softc(dev); 885 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 886 } 887 888 static void 889 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 890 { 891 ae_softc_t *sc; 892 struct mii_data *mii; 893 894 sc = ifp->if_softc; 895 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 896 897 AE_LOCK(sc); 898 mii = device_get_softc(sc->miibus); 899 mii_pollstat(mii); 900 ifmr->ifm_status = mii->mii_media_status; 901 ifmr->ifm_active = mii->mii_media_active; 902 AE_UNLOCK(sc); 903 } 904 905 static int 906 ae_mediachange(struct ifnet *ifp) 907 { 908 ae_softc_t *sc; 909 struct mii_data *mii; 910 struct mii_softc *mii_sc; 911 int error; 912 913 /* XXX: check IFF_UP ?? */ 914 sc = ifp->if_softc; 915 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 916 AE_LOCK(sc); 917 mii = device_get_softc(sc->miibus); 918 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 919 PHY_RESET(mii_sc); 920 error = mii_mediachg(mii); 921 AE_UNLOCK(sc); 922 923 return (error); 924 } 925 926 static int 927 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 928 { 929 int error; 930 uint32_t val; 931 932 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 933 934 /* 935 * Not sure why, but Linux does this. 936 */ 937 val = AE_READ_4(sc, AE_SPICTL_REG); 938 if ((val & AE_SPICTL_VPD_EN) != 0) { 939 val &= ~AE_SPICTL_VPD_EN; 940 AE_WRITE_4(sc, AE_SPICTL_REG, val); 941 } 942 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 943 return (error); 944 } 945 946 static int 947 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 948 { 949 uint32_t val; 950 int i; 951 952 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 953 954 /* 955 * VPD registers start at offset 0x100. Read them. 956 */ 957 val = 0x100 + reg * 4; 958 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 959 AE_VPD_CAP_ADDR_MASK); 960 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 961 DELAY(2000); 962 val = AE_READ_4(sc, AE_VPD_CAP_REG); 963 if ((val & AE_VPD_CAP_DONE) != 0) 964 break; 965 } 966 if (i == AE_VPD_TIMEOUT) { 967 device_printf(sc->dev, "timeout reading VPD register %d.\n", 968 reg); 969 return (ETIMEDOUT); 970 } 971 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 972 return (0); 973 } 974 975 static int 976 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 977 { 978 uint32_t word, reg, val; 979 int error; 980 int found; 981 int vpdc; 982 int i; 983 984 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 985 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 986 987 /* 988 * Check for EEPROM. 989 */ 990 error = ae_check_eeprom_present(sc, &vpdc); 991 if (error != 0) 992 return (error); 993 994 /* 995 * Read the VPD configuration space. 996 * Each register is prefixed with signature, 997 * so we can check if it is valid. 998 */ 999 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 1000 error = ae_vpd_read_word(sc, i, &word); 1001 if (error != 0) 1002 break; 1003 1004 /* 1005 * Check signature. 1006 */ 1007 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1008 break; 1009 reg = word >> AE_VPD_REG_SHIFT; 1010 i++; /* Move to the next word. */ 1011 1012 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1013 continue; 1014 1015 error = ae_vpd_read_word(sc, i, &val); 1016 if (error != 0) 1017 break; 1018 if (reg == AE_EADDR0_REG) 1019 eaddr[0] = val; 1020 else 1021 eaddr[1] = val; 1022 found++; 1023 } 1024 1025 if (found < 2) 1026 return (ENOENT); 1027 1028 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1029 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1030 if (bootverbose) 1031 device_printf(sc->dev, 1032 "VPD ethernet address registers are invalid.\n"); 1033 return (EINVAL); 1034 } 1035 return (0); 1036 } 1037 1038 static int 1039 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1040 { 1041 1042 /* 1043 * BIOS is supposed to set this. 1044 */ 1045 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1046 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1047 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1048 1049 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1050 if (bootverbose) 1051 device_printf(sc->dev, 1052 "Ethernet address registers are invalid.\n"); 1053 return (EINVAL); 1054 } 1055 return (0); 1056 } 1057 1058 static void 1059 ae_retrieve_address(ae_softc_t *sc) 1060 { 1061 uint32_t eaddr[2] = {0, 0}; 1062 int error; 1063 1064 /* 1065 *Check for EEPROM. 1066 */ 1067 error = ae_get_vpd_eaddr(sc, eaddr); 1068 if (error != 0) 1069 error = ae_get_reg_eaddr(sc, eaddr); 1070 if (error != 0) { 1071 if (bootverbose) 1072 device_printf(sc->dev, 1073 "Generating random ethernet address.\n"); 1074 eaddr[0] = arc4random(); 1075 1076 /* 1077 * Set OUI to ASUSTek COMPUTER INC. 1078 */ 1079 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1080 sc->eaddr[1] = 0x1f; 1081 sc->eaddr[2] = 0xc6; 1082 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1083 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1084 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1085 } else { 1086 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1087 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1088 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1089 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1090 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1091 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1092 } 1093 } 1094 1095 static void 1096 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1097 { 1098 bus_addr_t *addr = arg; 1099 1100 if (error != 0) 1101 return; 1102 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1103 nsegs)); 1104 *addr = segs[0].ds_addr; 1105 } 1106 1107 static int 1108 ae_alloc_rings(ae_softc_t *sc) 1109 { 1110 bus_addr_t busaddr; 1111 int error; 1112 1113 /* 1114 * Create parent DMA tag. 1115 */ 1116 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1117 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1118 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1119 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1120 &sc->dma_parent_tag); 1121 if (error != 0) { 1122 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1123 return (error); 1124 } 1125 1126 /* 1127 * Create DMA tag for TxD. 1128 */ 1129 error = bus_dma_tag_create(sc->dma_parent_tag, 1130 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1131 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1132 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1133 &sc->dma_txd_tag); 1134 if (error != 0) { 1135 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1136 return (error); 1137 } 1138 1139 /* 1140 * Create DMA tag for TxS. 1141 */ 1142 error = bus_dma_tag_create(sc->dma_parent_tag, 1143 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1144 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1145 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1146 &sc->dma_txs_tag); 1147 if (error != 0) { 1148 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1149 return (error); 1150 } 1151 1152 /* 1153 * Create DMA tag for RxD. 1154 */ 1155 error = bus_dma_tag_create(sc->dma_parent_tag, 1156 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1157 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1158 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1159 &sc->dma_rxd_tag); 1160 if (error != 0) { 1161 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1162 return (error); 1163 } 1164 1165 /* 1166 * Allocate TxD DMA memory. 1167 */ 1168 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1169 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1170 &sc->dma_txd_map); 1171 if (error != 0) { 1172 device_printf(sc->dev, 1173 "could not allocate DMA memory for TxD ring.\n"); 1174 return (error); 1175 } 1176 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1177 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1178 if (error != 0 || busaddr == 0) { 1179 device_printf(sc->dev, 1180 "could not load DMA map for TxD ring.\n"); 1181 return (error); 1182 } 1183 sc->dma_txd_busaddr = busaddr; 1184 1185 /* 1186 * Allocate TxS DMA memory. 1187 */ 1188 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1189 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1190 &sc->dma_txs_map); 1191 if (error != 0) { 1192 device_printf(sc->dev, 1193 "could not allocate DMA memory for TxS ring.\n"); 1194 return (error); 1195 } 1196 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1197 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1198 if (error != 0 || busaddr == 0) { 1199 device_printf(sc->dev, 1200 "could not load DMA map for TxS ring.\n"); 1201 return (error); 1202 } 1203 sc->dma_txs_busaddr = busaddr; 1204 1205 /* 1206 * Allocate RxD DMA memory. 1207 */ 1208 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1209 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1210 &sc->dma_rxd_map); 1211 if (error != 0) { 1212 device_printf(sc->dev, 1213 "could not allocate DMA memory for RxD ring.\n"); 1214 return (error); 1215 } 1216 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1217 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1218 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1219 if (error != 0 || busaddr == 0) { 1220 device_printf(sc->dev, 1221 "could not load DMA map for RxD ring.\n"); 1222 return (error); 1223 } 1224 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1225 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1226 1227 return (0); 1228 } 1229 1230 static void 1231 ae_dma_free(ae_softc_t *sc) 1232 { 1233 1234 if (sc->dma_txd_tag != NULL) { 1235 if (sc->dma_txd_busaddr != 0) 1236 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1237 if (sc->txd_base != NULL) 1238 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1239 sc->dma_txd_map); 1240 bus_dma_tag_destroy(sc->dma_txd_tag); 1241 sc->dma_txd_tag = NULL; 1242 sc->txd_base = NULL; 1243 sc->dma_txd_busaddr = 0; 1244 } 1245 if (sc->dma_txs_tag != NULL) { 1246 if (sc->dma_txs_busaddr != 0) 1247 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1248 if (sc->txs_base != NULL) 1249 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1250 sc->dma_txs_map); 1251 bus_dma_tag_destroy(sc->dma_txs_tag); 1252 sc->dma_txs_tag = NULL; 1253 sc->txs_base = NULL; 1254 sc->dma_txs_busaddr = 0; 1255 } 1256 if (sc->dma_rxd_tag != NULL) { 1257 if (sc->dma_rxd_busaddr != 0) 1258 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1259 if (sc->rxd_base_dma != NULL) 1260 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1261 sc->dma_rxd_map); 1262 bus_dma_tag_destroy(sc->dma_rxd_tag); 1263 sc->dma_rxd_tag = NULL; 1264 sc->rxd_base_dma = NULL; 1265 sc->dma_rxd_busaddr = 0; 1266 } 1267 if (sc->dma_parent_tag != NULL) { 1268 bus_dma_tag_destroy(sc->dma_parent_tag); 1269 sc->dma_parent_tag = NULL; 1270 } 1271 } 1272 1273 static int 1274 ae_shutdown(device_t dev) 1275 { 1276 ae_softc_t *sc; 1277 int error; 1278 1279 sc = device_get_softc(dev); 1280 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1281 1282 error = ae_suspend(dev); 1283 AE_LOCK(sc); 1284 ae_powersave_enable(sc); 1285 AE_UNLOCK(sc); 1286 return (error); 1287 } 1288 1289 static void 1290 ae_powersave_disable(ae_softc_t *sc) 1291 { 1292 uint32_t val; 1293 1294 AE_LOCK_ASSERT(sc); 1295 1296 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1297 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1298 if (val & AE_PHY_DBG_POWERSAVE) { 1299 val &= ~AE_PHY_DBG_POWERSAVE; 1300 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1301 DELAY(1000); 1302 } 1303 } 1304 1305 static void 1306 ae_powersave_enable(ae_softc_t *sc) 1307 { 1308 uint32_t val; 1309 1310 AE_LOCK_ASSERT(sc); 1311 1312 /* 1313 * XXX magic numbers. 1314 */ 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1316 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1317 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1318 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1319 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1320 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1321 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1322 } 1323 1324 static void 1325 ae_pm_init(ae_softc_t *sc) 1326 { 1327 struct ifnet *ifp; 1328 uint32_t val; 1329 uint16_t pmstat; 1330 struct mii_data *mii; 1331 int pmc; 1332 1333 AE_LOCK_ASSERT(sc); 1334 1335 ifp = sc->ifp; 1336 if ((sc->flags & AE_FLAG_PMG) == 0) { 1337 /* Disable WOL entirely. */ 1338 AE_WRITE_4(sc, AE_WOL_REG, 0); 1339 return; 1340 } 1341 1342 /* 1343 * Configure WOL if enabled. 1344 */ 1345 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1346 mii = device_get_softc(sc->miibus); 1347 mii_pollstat(mii); 1348 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1349 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1350 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1351 AE_WOL_MAGIC_PME); 1352 1353 /* 1354 * Configure MAC. 1355 */ 1356 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1357 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1358 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1359 AE_HALFBUF_MASK) | \ 1360 ((AE_MAC_PREAMBLE_DEFAULT << \ 1361 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1362 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1363 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1364 IFM_FDX) != 0) 1365 val |= AE_MAC_FULL_DUPLEX; 1366 AE_WRITE_4(sc, AE_MAC_REG, val); 1367 1368 } else { /* No link. */ 1369 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1370 AE_WOL_LNKCHG_PME); 1371 AE_WRITE_4(sc, AE_MAC_REG, 0); 1372 } 1373 } else { 1374 ae_powersave_enable(sc); 1375 } 1376 1377 /* 1378 * PCIE hacks. Magic numbers. 1379 */ 1380 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1381 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1382 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1383 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1384 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1385 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1386 1387 /* 1388 * Configure PME. 1389 */ 1390 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1391 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1392 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1393 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1394 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1395 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1396 } 1397 } 1398 1399 static int 1400 ae_suspend(device_t dev) 1401 { 1402 ae_softc_t *sc; 1403 1404 sc = device_get_softc(dev); 1405 1406 AE_LOCK(sc); 1407 ae_stop(sc); 1408 ae_pm_init(sc); 1409 AE_UNLOCK(sc); 1410 1411 return (0); 1412 } 1413 1414 static int 1415 ae_resume(device_t dev) 1416 { 1417 ae_softc_t *sc; 1418 1419 sc = device_get_softc(dev); 1420 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1421 1422 AE_LOCK(sc); 1423 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1424 if ((sc->ifp->if_flags & IFF_UP) != 0) 1425 ae_init_locked(sc); 1426 AE_UNLOCK(sc); 1427 1428 return (0); 1429 } 1430 1431 static unsigned int 1432 ae_tx_avail_size(ae_softc_t *sc) 1433 { 1434 unsigned int avail; 1435 1436 if (sc->txd_cur >= sc->txd_ack) 1437 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1438 else 1439 avail = sc->txd_ack - sc->txd_cur; 1440 1441 return (avail); 1442 } 1443 1444 static int 1445 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1446 { 1447 struct mbuf *m0; 1448 ae_txd_t *hdr; 1449 unsigned int to_end; 1450 uint16_t len; 1451 1452 AE_LOCK_ASSERT(sc); 1453 1454 m0 = *m_head; 1455 len = m0->m_pkthdr.len; 1456 1457 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1458 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1459 #ifdef AE_DEBUG 1460 if_printf(sc->ifp, "No free Tx available.\n"); 1461 #endif 1462 return ENOBUFS; 1463 } 1464 1465 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1466 bzero(hdr, sizeof(*hdr)); 1467 /* Skip header size. */ 1468 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1469 /* Space available to the end of the ring */ 1470 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1471 if (to_end >= len) { 1472 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1473 } else { 1474 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1475 sc->txd_cur)); 1476 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1477 } 1478 1479 /* 1480 * Set TxD flags and parameters. 1481 */ 1482 if ((m0->m_flags & M_VLANTAG) != 0) { 1483 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1484 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1485 } else { 1486 hdr->len = htole16(len); 1487 } 1488 1489 /* 1490 * Set current TxD position and round up to a 4-byte boundary. 1491 */ 1492 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1493 if (sc->txd_cur == sc->txd_ack) 1494 sc->flags &= ~AE_FLAG_TXAVAIL; 1495 #ifdef AE_DEBUG 1496 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1497 #endif 1498 1499 /* 1500 * Update TxS position and check if there are empty TxS available. 1501 */ 1502 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1503 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1504 if (sc->txs_cur == sc->txs_ack) 1505 sc->flags &= ~AE_FLAG_TXAVAIL; 1506 1507 /* 1508 * Synchronize DMA memory. 1509 */ 1510 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1511 BUS_DMASYNC_PREWRITE); 1512 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1513 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1514 1515 return (0); 1516 } 1517 1518 static void 1519 ae_start(struct ifnet *ifp) 1520 { 1521 ae_softc_t *sc; 1522 1523 sc = ifp->if_softc; 1524 AE_LOCK(sc); 1525 ae_start_locked(ifp); 1526 AE_UNLOCK(sc); 1527 } 1528 1529 static void 1530 ae_start_locked(struct ifnet *ifp) 1531 { 1532 ae_softc_t *sc; 1533 unsigned int count; 1534 struct mbuf *m0; 1535 int error; 1536 1537 sc = ifp->if_softc; 1538 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1539 AE_LOCK_ASSERT(sc); 1540 1541 #ifdef AE_DEBUG 1542 if_printf(ifp, "Start called.\n"); 1543 #endif 1544 1545 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1546 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1547 return; 1548 1549 count = 0; 1550 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1551 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1552 if (m0 == NULL) 1553 break; /* Nothing to do. */ 1554 1555 error = ae_encap(sc, &m0); 1556 if (error != 0) { 1557 if (m0 != NULL) { 1558 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1559 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1560 #ifdef AE_DEBUG 1561 if_printf(ifp, "Setting OACTIVE.\n"); 1562 #endif 1563 } 1564 break; 1565 } 1566 count++; 1567 sc->tx_inproc++; 1568 1569 /* Bounce a copy of the frame to BPF. */ 1570 ETHER_BPF_MTAP(ifp, m0); 1571 1572 m_freem(m0); 1573 } 1574 1575 if (count > 0) { /* Something was dequeued. */ 1576 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1577 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1578 #ifdef AE_DEBUG 1579 if_printf(ifp, "%d packets dequeued.\n", count); 1580 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1581 #endif 1582 } 1583 } 1584 1585 static void 1586 ae_link_task(void *arg, int pending) 1587 { 1588 ae_softc_t *sc; 1589 struct mii_data *mii; 1590 struct ifnet *ifp; 1591 uint32_t val; 1592 1593 sc = (ae_softc_t *)arg; 1594 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1595 AE_LOCK(sc); 1596 1597 ifp = sc->ifp; 1598 mii = device_get_softc(sc->miibus); 1599 if (mii == NULL || ifp == NULL || 1600 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1601 AE_UNLOCK(sc); /* XXX: could happen? */ 1602 return; 1603 } 1604 1605 sc->flags &= ~AE_FLAG_LINK; 1606 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1607 (IFM_AVALID | IFM_ACTIVE)) { 1608 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1609 case IFM_10_T: 1610 case IFM_100_TX: 1611 sc->flags |= AE_FLAG_LINK; 1612 break; 1613 default: 1614 break; 1615 } 1616 } 1617 1618 /* 1619 * Stop Rx/Tx MACs. 1620 */ 1621 ae_stop_rxmac(sc); 1622 ae_stop_txmac(sc); 1623 1624 if ((sc->flags & AE_FLAG_LINK) != 0) { 1625 ae_mac_config(sc); 1626 1627 /* 1628 * Restart DMA engines. 1629 */ 1630 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1631 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1632 1633 /* 1634 * Enable Rx and Tx MACs. 1635 */ 1636 val = AE_READ_4(sc, AE_MAC_REG); 1637 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1638 AE_WRITE_4(sc, AE_MAC_REG, val); 1639 } 1640 AE_UNLOCK(sc); 1641 } 1642 1643 static void 1644 ae_stop_rxmac(ae_softc_t *sc) 1645 { 1646 uint32_t val; 1647 int i; 1648 1649 AE_LOCK_ASSERT(sc); 1650 1651 /* 1652 * Stop Rx MAC engine. 1653 */ 1654 val = AE_READ_4(sc, AE_MAC_REG); 1655 if ((val & AE_MAC_RX_EN) != 0) { 1656 val &= ~AE_MAC_RX_EN; 1657 AE_WRITE_4(sc, AE_MAC_REG, val); 1658 } 1659 1660 /* 1661 * Stop Rx DMA engine. 1662 */ 1663 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1664 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1665 1666 /* 1667 * Wait for IDLE state. 1668 */ 1669 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1670 val = AE_READ_4(sc, AE_IDLE_REG); 1671 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1672 break; 1673 DELAY(100); 1674 } 1675 if (i == AE_IDLE_TIMEOUT) 1676 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1677 } 1678 1679 static void 1680 ae_stop_txmac(ae_softc_t *sc) 1681 { 1682 uint32_t val; 1683 int i; 1684 1685 AE_LOCK_ASSERT(sc); 1686 1687 /* 1688 * Stop Tx MAC engine. 1689 */ 1690 val = AE_READ_4(sc, AE_MAC_REG); 1691 if ((val & AE_MAC_TX_EN) != 0) { 1692 val &= ~AE_MAC_TX_EN; 1693 AE_WRITE_4(sc, AE_MAC_REG, val); 1694 } 1695 1696 /* 1697 * Stop Tx DMA engine. 1698 */ 1699 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1700 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1701 1702 /* 1703 * Wait for IDLE state. 1704 */ 1705 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1706 val = AE_READ_4(sc, AE_IDLE_REG); 1707 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1708 break; 1709 DELAY(100); 1710 } 1711 if (i == AE_IDLE_TIMEOUT) 1712 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1713 } 1714 1715 static void 1716 ae_mac_config(ae_softc_t *sc) 1717 { 1718 struct mii_data *mii; 1719 uint32_t val; 1720 1721 AE_LOCK_ASSERT(sc); 1722 1723 mii = device_get_softc(sc->miibus); 1724 val = AE_READ_4(sc, AE_MAC_REG); 1725 val &= ~AE_MAC_FULL_DUPLEX; 1726 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1727 1728 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1729 val |= AE_MAC_FULL_DUPLEX; 1730 1731 AE_WRITE_4(sc, AE_MAC_REG, val); 1732 } 1733 1734 static int 1735 ae_intr(void *arg) 1736 { 1737 ae_softc_t *sc; 1738 uint32_t val; 1739 1740 sc = (ae_softc_t *)arg; 1741 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1742 1743 val = AE_READ_4(sc, AE_ISR_REG); 1744 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1745 return (FILTER_STRAY); 1746 1747 /* Disable interrupts. */ 1748 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1749 1750 /* Schedule interrupt processing. */ 1751 taskqueue_enqueue(sc->tq, &sc->int_task); 1752 1753 return (FILTER_HANDLED); 1754 } 1755 1756 static void 1757 ae_int_task(void *arg, int pending) 1758 { 1759 ae_softc_t *sc; 1760 struct ifnet *ifp; 1761 uint32_t val; 1762 1763 sc = (ae_softc_t *)arg; 1764 1765 AE_LOCK(sc); 1766 1767 ifp = sc->ifp; 1768 1769 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1770 if (val == 0) { 1771 AE_UNLOCK(sc); 1772 return; 1773 } 1774 1775 /* 1776 * Clear interrupts and disable them. 1777 */ 1778 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1779 1780 #ifdef AE_DEBUG 1781 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1782 #endif 1783 1784 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1785 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1786 AE_ISR_PHY_LINKDOWN)) != 0) { 1787 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1788 ae_init_locked(sc); 1789 AE_UNLOCK(sc); 1790 return; 1791 } 1792 if ((val & AE_ISR_TX_EVENT) != 0) 1793 ae_tx_intr(sc); 1794 if ((val & AE_ISR_RX_EVENT) != 0) 1795 ae_rx_intr(sc); 1796 /* 1797 * Re-enable interrupts. 1798 */ 1799 AE_WRITE_4(sc, AE_ISR_REG, 0); 1800 1801 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1803 ae_start_locked(ifp); 1804 } 1805 } 1806 1807 AE_UNLOCK(sc); 1808 } 1809 1810 static void 1811 ae_tx_intr(ae_softc_t *sc) 1812 { 1813 struct ifnet *ifp; 1814 ae_txd_t *txd; 1815 ae_txs_t *txs; 1816 uint16_t flags; 1817 1818 AE_LOCK_ASSERT(sc); 1819 1820 ifp = sc->ifp; 1821 1822 #ifdef AE_DEBUG 1823 if_printf(ifp, "Tx interrupt occuried.\n"); 1824 #endif 1825 1826 /* 1827 * Syncronize DMA buffers. 1828 */ 1829 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1830 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1831 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1832 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1833 1834 for (;;) { 1835 txs = sc->txs_base + sc->txs_ack; 1836 flags = le16toh(txs->flags); 1837 if ((flags & AE_TXS_UPDATE) == 0) 1838 break; 1839 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1840 /* Update stats. */ 1841 ae_update_stats_tx(flags, &sc->stats); 1842 1843 /* 1844 * Update TxS position. 1845 */ 1846 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1847 sc->flags |= AE_FLAG_TXAVAIL; 1848 1849 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1850 if (txs->len != txd->len) 1851 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1852 le16toh(txs->len), le16toh(txd->len)); 1853 1854 /* 1855 * Move txd ack and align on 4-byte boundary. 1856 */ 1857 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1858 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1859 1860 if ((flags & AE_TXS_SUCCESS) != 0) 1861 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1862 else 1863 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1864 1865 sc->tx_inproc--; 1866 } 1867 1868 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1869 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1870 if (sc->tx_inproc < 0) { 1871 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1872 sc->tx_inproc = 0; 1873 } 1874 1875 if (sc->tx_inproc == 0) 1876 sc->wd_timer = 0; /* Unarm watchdog. */ 1877 1878 /* 1879 * Syncronize DMA buffers. 1880 */ 1881 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1883 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1884 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1885 } 1886 1887 static void 1888 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1889 { 1890 struct ifnet *ifp; 1891 struct mbuf *m; 1892 unsigned int size; 1893 uint16_t flags; 1894 1895 AE_LOCK_ASSERT(sc); 1896 1897 ifp = sc->ifp; 1898 flags = le16toh(rxd->flags); 1899 1900 #ifdef AE_DEBUG 1901 if_printf(ifp, "Rx interrupt occuried.\n"); 1902 #endif 1903 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1904 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1905 if_printf(ifp, "Runt frame received."); 1906 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1907 return; 1908 } 1909 1910 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1911 if (m == NULL) { 1912 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1913 return; 1914 } 1915 1916 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1917 (flags & AE_RXD_HAS_VLAN) != 0) { 1918 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1919 m->m_flags |= M_VLANTAG; 1920 } 1921 1922 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1923 /* 1924 * Pass it through. 1925 */ 1926 AE_UNLOCK(sc); 1927 (*ifp->if_input)(ifp, m); 1928 AE_LOCK(sc); 1929 } 1930 1931 static void 1932 ae_rx_intr(ae_softc_t *sc) 1933 { 1934 ae_rxd_t *rxd; 1935 struct ifnet *ifp; 1936 uint16_t flags; 1937 int count; 1938 1939 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1940 1941 AE_LOCK_ASSERT(sc); 1942 1943 ifp = sc->ifp; 1944 1945 /* 1946 * Syncronize DMA buffers. 1947 */ 1948 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1949 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1950 1951 for (count = 0;; count++) { 1952 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1953 flags = le16toh(rxd->flags); 1954 if ((flags & AE_RXD_UPDATE) == 0) 1955 break; 1956 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1957 /* Update stats. */ 1958 ae_update_stats_rx(flags, &sc->stats); 1959 1960 /* 1961 * Update position index. 1962 */ 1963 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1964 1965 if ((flags & AE_RXD_SUCCESS) != 0) 1966 ae_rxeof(sc, rxd); 1967 else 1968 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1969 } 1970 1971 if (count > 0) { 1972 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1973 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1974 /* 1975 * Update Rx index. 1976 */ 1977 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1978 } 1979 } 1980 1981 static void 1982 ae_watchdog(ae_softc_t *sc) 1983 { 1984 struct ifnet *ifp; 1985 1986 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1987 AE_LOCK_ASSERT(sc); 1988 ifp = sc->ifp; 1989 1990 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1991 return; /* Noting to do. */ 1992 1993 if ((sc->flags & AE_FLAG_LINK) == 0) 1994 if_printf(ifp, "watchdog timeout (missed link).\n"); 1995 else 1996 if_printf(ifp, "watchdog timeout - resetting.\n"); 1997 1998 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1999 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2000 ae_init_locked(sc); 2001 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2002 ae_start_locked(ifp); 2003 } 2004 2005 static void 2006 ae_tick(void *arg) 2007 { 2008 ae_softc_t *sc; 2009 struct mii_data *mii; 2010 2011 sc = (ae_softc_t *)arg; 2012 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2013 AE_LOCK_ASSERT(sc); 2014 2015 mii = device_get_softc(sc->miibus); 2016 mii_tick(mii); 2017 ae_watchdog(sc); /* Watchdog check. */ 2018 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2019 } 2020 2021 static void 2022 ae_rxvlan(ae_softc_t *sc) 2023 { 2024 struct ifnet *ifp; 2025 uint32_t val; 2026 2027 AE_LOCK_ASSERT(sc); 2028 ifp = sc->ifp; 2029 val = AE_READ_4(sc, AE_MAC_REG); 2030 val &= ~AE_MAC_RMVLAN_EN; 2031 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2032 val |= AE_MAC_RMVLAN_EN; 2033 AE_WRITE_4(sc, AE_MAC_REG, val); 2034 } 2035 2036 static void 2037 ae_rxfilter(ae_softc_t *sc) 2038 { 2039 struct ifnet *ifp; 2040 struct ifmultiaddr *ifma; 2041 uint32_t crc; 2042 uint32_t mchash[2]; 2043 uint32_t rxcfg; 2044 2045 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2046 2047 AE_LOCK_ASSERT(sc); 2048 2049 ifp = sc->ifp; 2050 2051 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2052 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2053 2054 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2055 rxcfg |= AE_MAC_BCAST_EN; 2056 if ((ifp->if_flags & IFF_PROMISC) != 0) 2057 rxcfg |= AE_MAC_PROMISC_EN; 2058 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2059 rxcfg |= AE_MAC_MCAST_EN; 2060 2061 /* 2062 * Wipe old settings. 2063 */ 2064 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2065 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2066 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2067 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2068 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2069 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2070 return; 2071 } 2072 2073 /* 2074 * Load multicast tables. 2075 */ 2076 bzero(mchash, sizeof(mchash)); 2077 if_maddr_rlock(ifp); 2078 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2079 if (ifma->ifma_addr->sa_family != AF_LINK) 2080 continue; 2081 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2082 ifma->ifma_addr), ETHER_ADDR_LEN); 2083 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2084 } 2085 if_maddr_runlock(ifp); 2086 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2087 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2088 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2089 } 2090 2091 static int 2092 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2093 { 2094 struct ae_softc *sc; 2095 struct ifreq *ifr; 2096 struct mii_data *mii; 2097 int error, mask; 2098 2099 sc = ifp->if_softc; 2100 ifr = (struct ifreq *)data; 2101 error = 0; 2102 2103 switch (cmd) { 2104 case SIOCSIFMTU: 2105 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2106 error = EINVAL; 2107 else if (ifp->if_mtu != ifr->ifr_mtu) { 2108 AE_LOCK(sc); 2109 ifp->if_mtu = ifr->ifr_mtu; 2110 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2111 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2112 ae_init_locked(sc); 2113 } 2114 AE_UNLOCK(sc); 2115 } 2116 break; 2117 case SIOCSIFFLAGS: 2118 AE_LOCK(sc); 2119 if ((ifp->if_flags & IFF_UP) != 0) { 2120 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2121 if (((ifp->if_flags ^ sc->if_flags) 2122 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2123 ae_rxfilter(sc); 2124 } else { 2125 if ((sc->flags & AE_FLAG_DETACH) == 0) 2126 ae_init_locked(sc); 2127 } 2128 } else { 2129 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2130 ae_stop(sc); 2131 } 2132 sc->if_flags = ifp->if_flags; 2133 AE_UNLOCK(sc); 2134 break; 2135 case SIOCADDMULTI: 2136 case SIOCDELMULTI: 2137 AE_LOCK(sc); 2138 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2139 ae_rxfilter(sc); 2140 AE_UNLOCK(sc); 2141 break; 2142 case SIOCSIFMEDIA: 2143 case SIOCGIFMEDIA: 2144 mii = device_get_softc(sc->miibus); 2145 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2146 break; 2147 case SIOCSIFCAP: 2148 AE_LOCK(sc); 2149 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2150 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2151 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2152 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2153 ae_rxvlan(sc); 2154 } 2155 VLAN_CAPABILITIES(ifp); 2156 AE_UNLOCK(sc); 2157 break; 2158 default: 2159 error = ether_ioctl(ifp, cmd, data); 2160 break; 2161 } 2162 return (error); 2163 } 2164 2165 static void 2166 ae_stop(ae_softc_t *sc) 2167 { 2168 struct ifnet *ifp; 2169 int i; 2170 2171 AE_LOCK_ASSERT(sc); 2172 2173 ifp = sc->ifp; 2174 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2175 sc->flags &= ~AE_FLAG_LINK; 2176 sc->wd_timer = 0; /* Cancel watchdog. */ 2177 callout_stop(&sc->tick_ch); 2178 2179 /* 2180 * Clear and disable interrupts. 2181 */ 2182 AE_WRITE_4(sc, AE_IMR_REG, 0); 2183 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2184 2185 /* 2186 * Stop Rx/Tx MACs. 2187 */ 2188 ae_stop_txmac(sc); 2189 ae_stop_rxmac(sc); 2190 2191 /* 2192 * Stop DMA engines. 2193 */ 2194 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2195 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2196 2197 /* 2198 * Wait for everything to enter idle state. 2199 */ 2200 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2201 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2202 break; 2203 DELAY(100); 2204 } 2205 if (i == AE_IDLE_TIMEOUT) 2206 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2207 } 2208 2209 static void 2210 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2211 { 2212 2213 if ((flags & AE_TXS_BCAST) != 0) 2214 stats->tx_bcast++; 2215 if ((flags & AE_TXS_MCAST) != 0) 2216 stats->tx_mcast++; 2217 if ((flags & AE_TXS_PAUSE) != 0) 2218 stats->tx_pause++; 2219 if ((flags & AE_TXS_CTRL) != 0) 2220 stats->tx_ctrl++; 2221 if ((flags & AE_TXS_DEFER) != 0) 2222 stats->tx_defer++; 2223 if ((flags & AE_TXS_EXCDEFER) != 0) 2224 stats->tx_excdefer++; 2225 if ((flags & AE_TXS_SINGLECOL) != 0) 2226 stats->tx_singlecol++; 2227 if ((flags & AE_TXS_MULTICOL) != 0) 2228 stats->tx_multicol++; 2229 if ((flags & AE_TXS_LATECOL) != 0) 2230 stats->tx_latecol++; 2231 if ((flags & AE_TXS_ABORTCOL) != 0) 2232 stats->tx_abortcol++; 2233 if ((flags & AE_TXS_UNDERRUN) != 0) 2234 stats->tx_underrun++; 2235 } 2236 2237 static void 2238 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2239 { 2240 2241 if ((flags & AE_RXD_BCAST) != 0) 2242 stats->rx_bcast++; 2243 if ((flags & AE_RXD_MCAST) != 0) 2244 stats->rx_mcast++; 2245 if ((flags & AE_RXD_PAUSE) != 0) 2246 stats->rx_pause++; 2247 if ((flags & AE_RXD_CTRL) != 0) 2248 stats->rx_ctrl++; 2249 if ((flags & AE_RXD_CRCERR) != 0) 2250 stats->rx_crcerr++; 2251 if ((flags & AE_RXD_CODEERR) != 0) 2252 stats->rx_codeerr++; 2253 if ((flags & AE_RXD_RUNT) != 0) 2254 stats->rx_runt++; 2255 if ((flags & AE_RXD_FRAG) != 0) 2256 stats->rx_frag++; 2257 if ((flags & AE_RXD_TRUNC) != 0) 2258 stats->rx_trunc++; 2259 if ((flags & AE_RXD_ALIGN) != 0) 2260 stats->rx_align++; 2261 } 2262