1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/rman.h>
40 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
56
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
70
71 #include <dev/age/if_agereg.h>
72 #include <dev/age/if_agevar.h>
73
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
76
77 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
78
79 MODULE_DEPEND(age, pci, 1, 1, 1);
80 MODULE_DEPEND(age, ether, 1, 1, 1);
81 MODULE_DEPEND(age, miibus, 1, 1, 1);
82
83 /* Tunables. */
84 static int msi_disable = 0;
85 static int msix_disable = 0;
86 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
87 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
88
89 /*
90 * Devices supported by this driver.
91 */
92 static struct age_dev {
93 uint16_t age_vendorid;
94 uint16_t age_deviceid;
95 const char *age_name;
96 } age_devs[] = {
97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
98 "Attansic Technology Corp, L1 Gigabit Ethernet" },
99 };
100
101 static int age_miibus_readreg(device_t, int, int);
102 static int age_miibus_writereg(device_t, int, int, int);
103 static void age_miibus_statchg(device_t);
104 static void age_mediastatus(if_t, struct ifmediareq *);
105 static int age_mediachange(if_t);
106 static int age_probe(device_t);
107 static void age_get_macaddr(struct age_softc *);
108 static void age_phy_reset(struct age_softc *);
109 static int age_attach(device_t);
110 static int age_detach(device_t);
111 static void age_sysctl_node(struct age_softc *);
112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
113 static int age_check_boundary(struct age_softc *);
114 static int age_dma_alloc(struct age_softc *);
115 static void age_dma_free(struct age_softc *);
116 static int age_shutdown(device_t);
117 static void age_setwol(struct age_softc *);
118 static int age_suspend(device_t);
119 static int age_resume(device_t);
120 static int age_encap(struct age_softc *, struct mbuf **);
121 static void age_start(if_t);
122 static void age_start_locked(if_t);
123 static void age_watchdog(struct age_softc *);
124 static int age_ioctl(if_t, u_long, caddr_t);
125 static void age_mac_config(struct age_softc *);
126 static void age_link_task(void *, int);
127 static void age_stats_update(struct age_softc *);
128 static int age_intr(void *);
129 static void age_int_task(void *, int);
130 static void age_txintr(struct age_softc *, int);
131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
132 static int age_rxintr(struct age_softc *, int, int);
133 static void age_tick(void *);
134 static void age_reset(struct age_softc *);
135 static void age_init(void *);
136 static void age_init_locked(struct age_softc *);
137 static void age_stop(struct age_softc *);
138 static void age_stop_txmac(struct age_softc *);
139 static void age_stop_rxmac(struct age_softc *);
140 static void age_init_tx_ring(struct age_softc *);
141 static int age_init_rx_ring(struct age_softc *);
142 static void age_init_rr_ring(struct age_softc *);
143 static void age_init_cmb_block(struct age_softc *);
144 static void age_init_smb_block(struct age_softc *);
145 #ifndef __NO_STRICT_ALIGNMENT
146 static struct mbuf *age_fixup_rx(if_t, struct mbuf *);
147 #endif
148 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
149 static void age_rxvlan(struct age_softc *);
150 static void age_rxfilter(struct age_softc *);
151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
155
156 static device_method_t age_methods[] = {
157 /* Device interface. */
158 DEVMETHOD(device_probe, age_probe),
159 DEVMETHOD(device_attach, age_attach),
160 DEVMETHOD(device_detach, age_detach),
161 DEVMETHOD(device_shutdown, age_shutdown),
162 DEVMETHOD(device_suspend, age_suspend),
163 DEVMETHOD(device_resume, age_resume),
164
165 /* MII interface. */
166 DEVMETHOD(miibus_readreg, age_miibus_readreg),
167 DEVMETHOD(miibus_writereg, age_miibus_writereg),
168 DEVMETHOD(miibus_statchg, age_miibus_statchg),
169 { NULL, NULL }
170 };
171
172 static driver_t age_driver = {
173 "age",
174 age_methods,
175 sizeof(struct age_softc)
176 };
177
178 DRIVER_MODULE(age, pci, age_driver, 0, 0);
179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs,
180 nitems(age_devs));
181 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0);
182
183 static struct resource_spec age_res_spec_mem[] = {
184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
185 { -1, 0, 0 }
186 };
187
188 static struct resource_spec age_irq_spec_legacy[] = {
189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
190 { -1, 0, 0 }
191 };
192
193 static struct resource_spec age_irq_spec_msi[] = {
194 { SYS_RES_IRQ, 1, RF_ACTIVE },
195 { -1, 0, 0 }
196 };
197
198 static struct resource_spec age_irq_spec_msix[] = {
199 { SYS_RES_IRQ, 1, RF_ACTIVE },
200 { -1, 0, 0 }
201 };
202
203 /*
204 * Read a PHY register on the MII of the L1.
205 */
206 static int
age_miibus_readreg(device_t dev,int phy,int reg)207 age_miibus_readreg(device_t dev, int phy, int reg)
208 {
209 struct age_softc *sc;
210 uint32_t v;
211 int i;
212
213 sc = device_get_softc(dev);
214
215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
218 DELAY(1);
219 v = CSR_READ_4(sc, AGE_MDIO);
220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
221 break;
222 }
223
224 if (i == 0) {
225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
226 return (0);
227 }
228
229 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
230 }
231
232 /*
233 * Write a PHY register on the MII of the L1.
234 */
235 static int
age_miibus_writereg(device_t dev,int phy,int reg,int val)236 age_miibus_writereg(device_t dev, int phy, int reg, int val)
237 {
238 struct age_softc *sc;
239 uint32_t v;
240 int i;
241
242 sc = device_get_softc(dev);
243
244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
245 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
246 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
248 DELAY(1);
249 v = CSR_READ_4(sc, AGE_MDIO);
250 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
251 break;
252 }
253
254 if (i == 0)
255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
256
257 return (0);
258 }
259
260 /*
261 * Callback from MII layer when media changes.
262 */
263 static void
age_miibus_statchg(device_t dev)264 age_miibus_statchg(device_t dev)
265 {
266 struct age_softc *sc;
267
268 sc = device_get_softc(dev);
269 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
270 }
271
272 /*
273 * Get the current interface media status.
274 */
275 static void
age_mediastatus(if_t ifp,struct ifmediareq * ifmr)276 age_mediastatus(if_t ifp, struct ifmediareq *ifmr)
277 {
278 struct age_softc *sc;
279 struct mii_data *mii;
280
281 sc = if_getsoftc(ifp);
282 AGE_LOCK(sc);
283 mii = device_get_softc(sc->age_miibus);
284
285 mii_pollstat(mii);
286 ifmr->ifm_status = mii->mii_media_status;
287 ifmr->ifm_active = mii->mii_media_active;
288 AGE_UNLOCK(sc);
289 }
290
291 /*
292 * Set hardware to newly-selected media.
293 */
294 static int
age_mediachange(if_t ifp)295 age_mediachange(if_t ifp)
296 {
297 struct age_softc *sc;
298 struct mii_data *mii;
299 struct mii_softc *miisc;
300 int error;
301
302 sc = if_getsoftc(ifp);
303 AGE_LOCK(sc);
304 mii = device_get_softc(sc->age_miibus);
305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
306 PHY_RESET(miisc);
307 error = mii_mediachg(mii);
308 AGE_UNLOCK(sc);
309
310 return (error);
311 }
312
313 static int
age_probe(device_t dev)314 age_probe(device_t dev)
315 {
316 struct age_dev *sp;
317 int i;
318 uint16_t vendor, devid;
319
320 vendor = pci_get_vendor(dev);
321 devid = pci_get_device(dev);
322 sp = age_devs;
323 for (i = 0; i < nitems(age_devs); i++, sp++) {
324 if (vendor == sp->age_vendorid &&
325 devid == sp->age_deviceid) {
326 device_set_desc(dev, sp->age_name);
327 return (BUS_PROBE_DEFAULT);
328 }
329 }
330
331 return (ENXIO);
332 }
333
334 static void
age_get_macaddr(struct age_softc * sc)335 age_get_macaddr(struct age_softc *sc)
336 {
337 uint32_t ea[2], reg;
338 int i, vpdc;
339
340 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
341 if ((reg & SPI_VPD_ENB) != 0) {
342 /* Get VPD stored in TWSI EEPROM. */
343 reg &= ~SPI_VPD_ENB;
344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
345 }
346
347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
348 /*
349 * PCI VPD capability found, let TWSI reload EEPROM.
350 * This will set ethernet address of controller.
351 */
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
353 TWSI_CTRL_SW_LD_START);
354 for (i = 100; i > 0; i--) {
355 DELAY(1000);
356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
357 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
358 break;
359 }
360 if (i == 0)
361 device_printf(sc->age_dev,
362 "reloading EEPROM timeout!\n");
363 } else {
364 if (bootverbose)
365 device_printf(sc->age_dev,
366 "PCI VPD capability not found!\n");
367 }
368
369 ea[0] = CSR_READ_4(sc, AGE_PAR0);
370 ea[1] = CSR_READ_4(sc, AGE_PAR1);
371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
377 }
378
379 static void
age_phy_reset(struct age_softc * sc)380 age_phy_reset(struct age_softc *sc)
381 {
382 uint16_t reg, pn;
383 int i, linkup;
384
385 /* Reset PHY. */
386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
387 DELAY(2000);
388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
389 DELAY(2000);
390
391 #define ATPHY_DBG_ADDR 0x1D
392 #define ATPHY_DBG_DATA 0x1E
393 #define ATPHY_CDTC 0x16
394 #define PHY_CDTC_ENB 0x0001
395 #define PHY_CDTC_POFF 8
396 #define ATPHY_CDTS 0x1C
397 #define PHY_CDTS_STAT_OK 0x0000
398 #define PHY_CDTS_STAT_SHORT 0x0100
399 #define PHY_CDTS_STAT_OPEN 0x0200
400 #define PHY_CDTS_STAT_INVAL 0x0300
401 #define PHY_CDTS_STAT_MASK 0x0300
402
403 /* Check power saving mode. Magic from Linux. */
404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
405 for (linkup = 0, pn = 0; pn < 4; pn++) {
406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
407 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
408 for (i = 200; i > 0; i--) {
409 DELAY(1000);
410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
411 ATPHY_CDTC);
412 if ((reg & PHY_CDTC_ENB) == 0)
413 break;
414 }
415 DELAY(1000);
416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
417 ATPHY_CDTS);
418 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
419 linkup++;
420 break;
421 }
422 }
423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
424 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
425 if (linkup == 0) {
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
427 ATPHY_DBG_ADDR, 0);
428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
429 ATPHY_DBG_DATA, 0x124E);
430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
431 ATPHY_DBG_ADDR, 1);
432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
433 ATPHY_DBG_DATA);
434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
435 ATPHY_DBG_DATA, reg | 0x03);
436 /* XXX */
437 DELAY(1500 * 1000);
438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
439 ATPHY_DBG_ADDR, 0);
440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
441 ATPHY_DBG_DATA, 0x024E);
442 }
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 #undef ATPHY_CDTC
447 #undef PHY_CDTC_ENB
448 #undef PHY_CDTC_POFF
449 #undef ATPHY_CDTS
450 #undef PHY_CDTS_STAT_OK
451 #undef PHY_CDTS_STAT_SHORT
452 #undef PHY_CDTS_STAT_OPEN
453 #undef PHY_CDTS_STAT_INVAL
454 #undef PHY_CDTS_STAT_MASK
455 }
456
457 static int
age_attach(device_t dev)458 age_attach(device_t dev)
459 {
460 struct age_softc *sc;
461 if_t ifp;
462 uint16_t burst;
463 int error, i, msic, msixc, pmc;
464
465 error = 0;
466 sc = device_get_softc(dev);
467 sc->age_dev = dev;
468
469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
470 MTX_DEF);
471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
474
475 /* Map the device. */
476 pci_enable_busmaster(dev);
477 sc->age_res_spec = age_res_spec_mem;
478 sc->age_irq_spec = age_irq_spec_legacy;
479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
480 if (error != 0) {
481 device_printf(dev, "cannot allocate memory resources.\n");
482 goto fail;
483 }
484
485 /* Set PHY address. */
486 sc->age_phyaddr = AGE_PHY_ADDR;
487
488 /* Reset PHY. */
489 age_phy_reset(sc);
490
491 /* Reset the ethernet controller. */
492 age_reset(sc);
493
494 /* Get PCI and chip id/revision. */
495 sc->age_rev = pci_get_revid(dev);
496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
497 MASTER_CHIP_REV_SHIFT;
498 if (bootverbose) {
499 device_printf(dev, "PCI device revision : 0x%04x\n",
500 sc->age_rev);
501 device_printf(dev, "Chip id/revision : 0x%04x\n",
502 sc->age_chip_rev);
503 }
504
505 /*
506 * XXX
507 * Unintialized hardware returns an invalid chip id/revision
508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
509 * unplugged cable results in putting hardware into automatic
510 * power down mode which in turn returns invalld chip revision.
511 */
512 if (sc->age_chip_rev == 0xFFFF) {
513 device_printf(dev,"invalid chip revision : 0x%04x -- "
514 "not initialized?\n", sc->age_chip_rev);
515 error = ENXIO;
516 goto fail;
517 }
518
519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
522
523 /* Allocate IRQ resources. */
524 msixc = pci_msix_count(dev);
525 msic = pci_msi_count(dev);
526 if (bootverbose) {
527 device_printf(dev, "MSIX count : %d\n", msixc);
528 device_printf(dev, "MSI count : %d\n", msic);
529 }
530
531 /* Prefer MSIX over MSI. */
532 if (msix_disable == 0 || msi_disable == 0) {
533 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
534 pci_alloc_msix(dev, &msixc) == 0) {
535 if (msic == AGE_MSIX_MESSAGES) {
536 device_printf(dev, "Using %d MSIX messages.\n",
537 msixc);
538 sc->age_flags |= AGE_FLAG_MSIX;
539 sc->age_irq_spec = age_irq_spec_msix;
540 } else
541 pci_release_msi(dev);
542 }
543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
544 msic == AGE_MSI_MESSAGES &&
545 pci_alloc_msi(dev, &msic) == 0) {
546 if (msic == AGE_MSI_MESSAGES) {
547 device_printf(dev, "Using %d MSI messages.\n",
548 msic);
549 sc->age_flags |= AGE_FLAG_MSI;
550 sc->age_irq_spec = age_irq_spec_msi;
551 } else
552 pci_release_msi(dev);
553 }
554 }
555
556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
557 if (error != 0) {
558 device_printf(dev, "cannot allocate IRQ resources.\n");
559 goto fail;
560 }
561
562 /* Get DMA parameters from PCIe device control register. */
563 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
564 sc->age_flags |= AGE_FLAG_PCIE;
565 burst = pci_read_config(dev, i + 0x08, 2);
566 /* Max read request size. */
567 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
568 DMA_CFG_RD_BURST_SHIFT;
569 /* Max payload size. */
570 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
571 DMA_CFG_WR_BURST_SHIFT;
572 if (bootverbose) {
573 device_printf(dev, "Read request size : %d bytes.\n",
574 128 << ((burst >> 12) & 0x07));
575 device_printf(dev, "TLP payload size : %d bytes.\n",
576 128 << ((burst >> 5) & 0x07));
577 }
578 } else {
579 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
580 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
581 }
582
583 /* Create device sysctl node. */
584 age_sysctl_node(sc);
585
586 if ((error = age_dma_alloc(sc)) != 0)
587 goto fail;
588
589 /* Load station address. */
590 age_get_macaddr(sc);
591
592 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
593 if (ifp == NULL) {
594 device_printf(dev, "cannot allocate ifnet structure.\n");
595 error = ENXIO;
596 goto fail;
597 }
598
599 if_setsoftc(ifp, sc);
600 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
601 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
602 if_setioctlfn(ifp, age_ioctl);
603 if_setstartfn(ifp, age_start);
604 if_setinitfn(ifp, age_init);
605 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1);
606 if_setsendqready(ifp);
607 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4);
608 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO);
609 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
610 sc->age_flags |= AGE_FLAG_PMCAP;
611 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
612 }
613 if_setcapenable(ifp, if_getcapabilities(ifp));
614
615 /* Set up MII bus. */
616 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
617 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
618 0);
619 if (error != 0) {
620 device_printf(dev, "attaching PHYs failed\n");
621 goto fail;
622 }
623
624 ether_ifattach(ifp, sc->age_eaddr);
625
626 /* VLAN capability setup. */
627 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
628 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
629 if_setcapenable(ifp, if_getcapabilities(ifp));
630
631 /* Tell the upper layer(s) we support long frames. */
632 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
633
634 /* Create local taskq. */
635 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
636 taskqueue_thread_enqueue, &sc->age_tq);
637 if (sc->age_tq == NULL) {
638 device_printf(dev, "could not create taskqueue.\n");
639 ether_ifdetach(ifp);
640 error = ENXIO;
641 goto fail;
642 }
643 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
644 device_get_nameunit(sc->age_dev));
645
646 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
647 msic = AGE_MSIX_MESSAGES;
648 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
649 msic = AGE_MSI_MESSAGES;
650 else
651 msic = 1;
652 for (i = 0; i < msic; i++) {
653 error = bus_setup_intr(dev, sc->age_irq[i],
654 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
655 &sc->age_intrhand[i]);
656 if (error != 0)
657 break;
658 }
659 if (error != 0) {
660 device_printf(dev, "could not set up interrupt handler.\n");
661 taskqueue_free(sc->age_tq);
662 sc->age_tq = NULL;
663 ether_ifdetach(ifp);
664 goto fail;
665 }
666
667 fail:
668 if (error != 0)
669 age_detach(dev);
670
671 return (error);
672 }
673
674 static int
age_detach(device_t dev)675 age_detach(device_t dev)
676 {
677 struct age_softc *sc;
678 if_t ifp;
679 int i, msic;
680
681 sc = device_get_softc(dev);
682
683 ifp = sc->age_ifp;
684 if (device_is_attached(dev)) {
685 AGE_LOCK(sc);
686 sc->age_flags |= AGE_FLAG_DETACH;
687 age_stop(sc);
688 AGE_UNLOCK(sc);
689 callout_drain(&sc->age_tick_ch);
690 taskqueue_drain(sc->age_tq, &sc->age_int_task);
691 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
692 ether_ifdetach(ifp);
693 }
694
695 if (sc->age_tq != NULL) {
696 taskqueue_drain(sc->age_tq, &sc->age_int_task);
697 taskqueue_free(sc->age_tq);
698 sc->age_tq = NULL;
699 }
700
701 if (sc->age_miibus != NULL) {
702 device_delete_child(dev, sc->age_miibus);
703 sc->age_miibus = NULL;
704 }
705 bus_generic_detach(dev);
706 age_dma_free(sc);
707
708 if (ifp != NULL) {
709 if_free(ifp);
710 sc->age_ifp = NULL;
711 }
712
713 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
714 msic = AGE_MSIX_MESSAGES;
715 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
716 msic = AGE_MSI_MESSAGES;
717 else
718 msic = 1;
719 for (i = 0; i < msic; i++) {
720 if (sc->age_intrhand[i] != NULL) {
721 bus_teardown_intr(dev, sc->age_irq[i],
722 sc->age_intrhand[i]);
723 sc->age_intrhand[i] = NULL;
724 }
725 }
726
727 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
728 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
729 pci_release_msi(dev);
730 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
731 mtx_destroy(&sc->age_mtx);
732
733 return (0);
734 }
735
736 static void
age_sysctl_node(struct age_softc * sc)737 age_sysctl_node(struct age_softc *sc)
738 {
739 int error;
740
741 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
742 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
743 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
744 sc, 0, sysctl_age_stats, "I", "Statistics");
745
746 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
747 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
748 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
749 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I",
750 "age interrupt moderation");
751
752 /* Pull in device tunables. */
753 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
754 error = resource_int_value(device_get_name(sc->age_dev),
755 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
756 if (error == 0) {
757 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
758 sc->age_int_mod > AGE_IM_TIMER_MAX) {
759 device_printf(sc->age_dev,
760 "int_mod value out of range; using default: %d\n",
761 AGE_IM_TIMER_DEFAULT);
762 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
763 }
764 }
765
766 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
767 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
768 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
769 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I",
770 "max number of Rx events to process");
771
772 /* Pull in device tunables. */
773 sc->age_process_limit = AGE_PROC_DEFAULT;
774 error = resource_int_value(device_get_name(sc->age_dev),
775 device_get_unit(sc->age_dev), "process_limit",
776 &sc->age_process_limit);
777 if (error == 0) {
778 if (sc->age_process_limit < AGE_PROC_MIN ||
779 sc->age_process_limit > AGE_PROC_MAX) {
780 device_printf(sc->age_dev,
781 "process_limit value out of range; "
782 "using default: %d\n", AGE_PROC_DEFAULT);
783 sc->age_process_limit = AGE_PROC_DEFAULT;
784 }
785 }
786 }
787
788 struct age_dmamap_arg {
789 bus_addr_t age_busaddr;
790 };
791
792 static void
age_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)793 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
794 {
795 struct age_dmamap_arg *ctx;
796
797 if (error != 0)
798 return;
799
800 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
801
802 ctx = (struct age_dmamap_arg *)arg;
803 ctx->age_busaddr = segs[0].ds_addr;
804 }
805
806 /*
807 * Attansic L1 controller have single register to specify high
808 * address part of DMA blocks. So all descriptor structures and
809 * DMA memory blocks should have the same high address of given
810 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
811 */
812 static int
age_check_boundary(struct age_softc * sc)813 age_check_boundary(struct age_softc *sc)
814 {
815 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
816 bus_addr_t cmb_block_end, smb_block_end;
817
818 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
819 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
820 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
821 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
822 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
823 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
824
825 if ((AGE_ADDR_HI(tx_ring_end) !=
826 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
827 (AGE_ADDR_HI(rx_ring_end) !=
828 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
829 (AGE_ADDR_HI(rr_ring_end) !=
830 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
831 (AGE_ADDR_HI(cmb_block_end) !=
832 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
833 (AGE_ADDR_HI(smb_block_end) !=
834 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
835 return (EFBIG);
836
837 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
838 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
839 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
840 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
841 return (EFBIG);
842
843 return (0);
844 }
845
846 static int
age_dma_alloc(struct age_softc * sc)847 age_dma_alloc(struct age_softc *sc)
848 {
849 struct age_txdesc *txd;
850 struct age_rxdesc *rxd;
851 bus_addr_t lowaddr;
852 struct age_dmamap_arg ctx;
853 int error, i;
854
855 lowaddr = BUS_SPACE_MAXADDR;
856
857 again:
858 /* Create parent ring/DMA block tag. */
859 error = bus_dma_tag_create(
860 bus_get_dma_tag(sc->age_dev), /* parent */
861 1, 0, /* alignment, boundary */
862 lowaddr, /* lowaddr */
863 BUS_SPACE_MAXADDR, /* highaddr */
864 NULL, NULL, /* filter, filterarg */
865 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
866 0, /* nsegments */
867 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
868 0, /* flags */
869 NULL, NULL, /* lockfunc, lockarg */
870 &sc->age_cdata.age_parent_tag);
871 if (error != 0) {
872 device_printf(sc->age_dev,
873 "could not create parent DMA tag.\n");
874 goto fail;
875 }
876
877 /* Create tag for Tx ring. */
878 error = bus_dma_tag_create(
879 sc->age_cdata.age_parent_tag, /* parent */
880 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */
881 BUS_SPACE_MAXADDR, /* lowaddr */
882 BUS_SPACE_MAXADDR, /* highaddr */
883 NULL, NULL, /* filter, filterarg */
884 AGE_TX_RING_SZ, /* maxsize */
885 1, /* nsegments */
886 AGE_TX_RING_SZ, /* maxsegsize */
887 0, /* flags */
888 NULL, NULL, /* lockfunc, lockarg */
889 &sc->age_cdata.age_tx_ring_tag);
890 if (error != 0) {
891 device_printf(sc->age_dev,
892 "could not create Tx ring DMA tag.\n");
893 goto fail;
894 }
895
896 /* Create tag for Rx ring. */
897 error = bus_dma_tag_create(
898 sc->age_cdata.age_parent_tag, /* parent */
899 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */
900 BUS_SPACE_MAXADDR, /* lowaddr */
901 BUS_SPACE_MAXADDR, /* highaddr */
902 NULL, NULL, /* filter, filterarg */
903 AGE_RX_RING_SZ, /* maxsize */
904 1, /* nsegments */
905 AGE_RX_RING_SZ, /* maxsegsize */
906 0, /* flags */
907 NULL, NULL, /* lockfunc, lockarg */
908 &sc->age_cdata.age_rx_ring_tag);
909 if (error != 0) {
910 device_printf(sc->age_dev,
911 "could not create Rx ring DMA tag.\n");
912 goto fail;
913 }
914
915 /* Create tag for Rx return ring. */
916 error = bus_dma_tag_create(
917 sc->age_cdata.age_parent_tag, /* parent */
918 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */
919 BUS_SPACE_MAXADDR, /* lowaddr */
920 BUS_SPACE_MAXADDR, /* highaddr */
921 NULL, NULL, /* filter, filterarg */
922 AGE_RR_RING_SZ, /* maxsize */
923 1, /* nsegments */
924 AGE_RR_RING_SZ, /* maxsegsize */
925 0, /* flags */
926 NULL, NULL, /* lockfunc, lockarg */
927 &sc->age_cdata.age_rr_ring_tag);
928 if (error != 0) {
929 device_printf(sc->age_dev,
930 "could not create Rx return ring DMA tag.\n");
931 goto fail;
932 }
933
934 /* Create tag for coalesing message block. */
935 error = bus_dma_tag_create(
936 sc->age_cdata.age_parent_tag, /* parent */
937 AGE_CMB_ALIGN, 0, /* alignment, boundary */
938 BUS_SPACE_MAXADDR, /* lowaddr */
939 BUS_SPACE_MAXADDR, /* highaddr */
940 NULL, NULL, /* filter, filterarg */
941 AGE_CMB_BLOCK_SZ, /* maxsize */
942 1, /* nsegments */
943 AGE_CMB_BLOCK_SZ, /* maxsegsize */
944 0, /* flags */
945 NULL, NULL, /* lockfunc, lockarg */
946 &sc->age_cdata.age_cmb_block_tag);
947 if (error != 0) {
948 device_printf(sc->age_dev,
949 "could not create CMB DMA tag.\n");
950 goto fail;
951 }
952
953 /* Create tag for statistics message block. */
954 error = bus_dma_tag_create(
955 sc->age_cdata.age_parent_tag, /* parent */
956 AGE_SMB_ALIGN, 0, /* alignment, boundary */
957 BUS_SPACE_MAXADDR, /* lowaddr */
958 BUS_SPACE_MAXADDR, /* highaddr */
959 NULL, NULL, /* filter, filterarg */
960 AGE_SMB_BLOCK_SZ, /* maxsize */
961 1, /* nsegments */
962 AGE_SMB_BLOCK_SZ, /* maxsegsize */
963 0, /* flags */
964 NULL, NULL, /* lockfunc, lockarg */
965 &sc->age_cdata.age_smb_block_tag);
966 if (error != 0) {
967 device_printf(sc->age_dev,
968 "could not create SMB DMA tag.\n");
969 goto fail;
970 }
971
972 /* Allocate DMA'able memory and load the DMA map. */
973 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
974 (void **)&sc->age_rdata.age_tx_ring,
975 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
976 &sc->age_cdata.age_tx_ring_map);
977 if (error != 0) {
978 device_printf(sc->age_dev,
979 "could not allocate DMA'able memory for Tx ring.\n");
980 goto fail;
981 }
982 ctx.age_busaddr = 0;
983 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
984 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
985 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
986 if (error != 0 || ctx.age_busaddr == 0) {
987 device_printf(sc->age_dev,
988 "could not load DMA'able memory for Tx ring.\n");
989 goto fail;
990 }
991 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
992 /* Rx ring */
993 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
994 (void **)&sc->age_rdata.age_rx_ring,
995 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
996 &sc->age_cdata.age_rx_ring_map);
997 if (error != 0) {
998 device_printf(sc->age_dev,
999 "could not allocate DMA'able memory for Rx ring.\n");
1000 goto fail;
1001 }
1002 ctx.age_busaddr = 0;
1003 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1004 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1005 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1006 if (error != 0 || ctx.age_busaddr == 0) {
1007 device_printf(sc->age_dev,
1008 "could not load DMA'able memory for Rx ring.\n");
1009 goto fail;
1010 }
1011 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1012 /* Rx return ring */
1013 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1014 (void **)&sc->age_rdata.age_rr_ring,
1015 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1016 &sc->age_cdata.age_rr_ring_map);
1017 if (error != 0) {
1018 device_printf(sc->age_dev,
1019 "could not allocate DMA'able memory for Rx return ring.\n");
1020 goto fail;
1021 }
1022 ctx.age_busaddr = 0;
1023 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1024 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1025 AGE_RR_RING_SZ, age_dmamap_cb,
1026 &ctx, 0);
1027 if (error != 0 || ctx.age_busaddr == 0) {
1028 device_printf(sc->age_dev,
1029 "could not load DMA'able memory for Rx return ring.\n");
1030 goto fail;
1031 }
1032 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1033 /* CMB block */
1034 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1035 (void **)&sc->age_rdata.age_cmb_block,
1036 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1037 &sc->age_cdata.age_cmb_block_map);
1038 if (error != 0) {
1039 device_printf(sc->age_dev,
1040 "could not allocate DMA'able memory for CMB block.\n");
1041 goto fail;
1042 }
1043 ctx.age_busaddr = 0;
1044 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1045 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1046 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1047 if (error != 0 || ctx.age_busaddr == 0) {
1048 device_printf(sc->age_dev,
1049 "could not load DMA'able memory for CMB block.\n");
1050 goto fail;
1051 }
1052 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1053 /* SMB block */
1054 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1055 (void **)&sc->age_rdata.age_smb_block,
1056 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1057 &sc->age_cdata.age_smb_block_map);
1058 if (error != 0) {
1059 device_printf(sc->age_dev,
1060 "could not allocate DMA'able memory for SMB block.\n");
1061 goto fail;
1062 }
1063 ctx.age_busaddr = 0;
1064 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1065 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1066 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1067 if (error != 0 || ctx.age_busaddr == 0) {
1068 device_printf(sc->age_dev,
1069 "could not load DMA'able memory for SMB block.\n");
1070 goto fail;
1071 }
1072 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1073
1074 /*
1075 * All ring buffer and DMA blocks should have the same
1076 * high address part of 64bit DMA address space.
1077 */
1078 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1079 (error = age_check_boundary(sc)) != 0) {
1080 device_printf(sc->age_dev, "4GB boundary crossed, "
1081 "switching to 32bit DMA addressing mode.\n");
1082 age_dma_free(sc);
1083 /* Limit DMA address space to 32bit and try again. */
1084 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1085 goto again;
1086 }
1087
1088 /*
1089 * Create Tx/Rx buffer parent tag.
1090 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1091 * so it needs separate parent DMA tag.
1092 * XXX
1093 * It seems enabling 64bit DMA causes data corruption. Limit
1094 * DMA address space to 32bit.
1095 */
1096 error = bus_dma_tag_create(
1097 bus_get_dma_tag(sc->age_dev), /* parent */
1098 1, 0, /* alignment, boundary */
1099 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1100 BUS_SPACE_MAXADDR, /* highaddr */
1101 NULL, NULL, /* filter, filterarg */
1102 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1103 0, /* nsegments */
1104 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1105 0, /* flags */
1106 NULL, NULL, /* lockfunc, lockarg */
1107 &sc->age_cdata.age_buffer_tag);
1108 if (error != 0) {
1109 device_printf(sc->age_dev,
1110 "could not create parent buffer DMA tag.\n");
1111 goto fail;
1112 }
1113
1114 /* Create tag for Tx buffers. */
1115 error = bus_dma_tag_create(
1116 sc->age_cdata.age_buffer_tag, /* parent */
1117 1, 0, /* alignment, boundary */
1118 BUS_SPACE_MAXADDR, /* lowaddr */
1119 BUS_SPACE_MAXADDR, /* highaddr */
1120 NULL, NULL, /* filter, filterarg */
1121 AGE_TSO_MAXSIZE, /* maxsize */
1122 AGE_MAXTXSEGS, /* nsegments */
1123 AGE_TSO_MAXSEGSIZE, /* maxsegsize */
1124 0, /* flags */
1125 NULL, NULL, /* lockfunc, lockarg */
1126 &sc->age_cdata.age_tx_tag);
1127 if (error != 0) {
1128 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1129 goto fail;
1130 }
1131
1132 /* Create tag for Rx buffers. */
1133 error = bus_dma_tag_create(
1134 sc->age_cdata.age_buffer_tag, /* parent */
1135 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */
1136 BUS_SPACE_MAXADDR, /* lowaddr */
1137 BUS_SPACE_MAXADDR, /* highaddr */
1138 NULL, NULL, /* filter, filterarg */
1139 MCLBYTES, /* maxsize */
1140 1, /* nsegments */
1141 MCLBYTES, /* maxsegsize */
1142 0, /* flags */
1143 NULL, NULL, /* lockfunc, lockarg */
1144 &sc->age_cdata.age_rx_tag);
1145 if (error != 0) {
1146 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1147 goto fail;
1148 }
1149
1150 /* Create DMA maps for Tx buffers. */
1151 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1152 txd = &sc->age_cdata.age_txdesc[i];
1153 txd->tx_m = NULL;
1154 txd->tx_dmamap = NULL;
1155 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1156 &txd->tx_dmamap);
1157 if (error != 0) {
1158 device_printf(sc->age_dev,
1159 "could not create Tx dmamap.\n");
1160 goto fail;
1161 }
1162 }
1163 /* Create DMA maps for Rx buffers. */
1164 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1165 &sc->age_cdata.age_rx_sparemap)) != 0) {
1166 device_printf(sc->age_dev,
1167 "could not create spare Rx dmamap.\n");
1168 goto fail;
1169 }
1170 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1171 rxd = &sc->age_cdata.age_rxdesc[i];
1172 rxd->rx_m = NULL;
1173 rxd->rx_dmamap = NULL;
1174 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1175 &rxd->rx_dmamap);
1176 if (error != 0) {
1177 device_printf(sc->age_dev,
1178 "could not create Rx dmamap.\n");
1179 goto fail;
1180 }
1181 }
1182
1183 fail:
1184 return (error);
1185 }
1186
1187 static void
age_dma_free(struct age_softc * sc)1188 age_dma_free(struct age_softc *sc)
1189 {
1190 struct age_txdesc *txd;
1191 struct age_rxdesc *rxd;
1192 int i;
1193
1194 /* Tx buffers */
1195 if (sc->age_cdata.age_tx_tag != NULL) {
1196 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1197 txd = &sc->age_cdata.age_txdesc[i];
1198 if (txd->tx_dmamap != NULL) {
1199 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1200 txd->tx_dmamap);
1201 txd->tx_dmamap = NULL;
1202 }
1203 }
1204 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1205 sc->age_cdata.age_tx_tag = NULL;
1206 }
1207 /* Rx buffers */
1208 if (sc->age_cdata.age_rx_tag != NULL) {
1209 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1210 rxd = &sc->age_cdata.age_rxdesc[i];
1211 if (rxd->rx_dmamap != NULL) {
1212 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1213 rxd->rx_dmamap);
1214 rxd->rx_dmamap = NULL;
1215 }
1216 }
1217 if (sc->age_cdata.age_rx_sparemap != NULL) {
1218 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1219 sc->age_cdata.age_rx_sparemap);
1220 sc->age_cdata.age_rx_sparemap = NULL;
1221 }
1222 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1223 sc->age_cdata.age_rx_tag = NULL;
1224 }
1225 /* Tx ring. */
1226 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1227 if (sc->age_rdata.age_tx_ring_paddr != 0)
1228 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1229 sc->age_cdata.age_tx_ring_map);
1230 if (sc->age_rdata.age_tx_ring != NULL)
1231 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1232 sc->age_rdata.age_tx_ring,
1233 sc->age_cdata.age_tx_ring_map);
1234 sc->age_rdata.age_tx_ring_paddr = 0;
1235 sc->age_rdata.age_tx_ring = NULL;
1236 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1237 sc->age_cdata.age_tx_ring_tag = NULL;
1238 }
1239 /* Rx ring. */
1240 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1241 if (sc->age_rdata.age_rx_ring_paddr != 0)
1242 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1243 sc->age_cdata.age_rx_ring_map);
1244 if (sc->age_rdata.age_rx_ring != NULL)
1245 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1246 sc->age_rdata.age_rx_ring,
1247 sc->age_cdata.age_rx_ring_map);
1248 sc->age_rdata.age_rx_ring_paddr = 0;
1249 sc->age_rdata.age_rx_ring = NULL;
1250 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1251 sc->age_cdata.age_rx_ring_tag = NULL;
1252 }
1253 /* Rx return ring. */
1254 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1255 if (sc->age_rdata.age_rr_ring_paddr != 0)
1256 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1257 sc->age_cdata.age_rr_ring_map);
1258 if (sc->age_rdata.age_rr_ring != NULL)
1259 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1260 sc->age_rdata.age_rr_ring,
1261 sc->age_cdata.age_rr_ring_map);
1262 sc->age_rdata.age_rr_ring_paddr = 0;
1263 sc->age_rdata.age_rr_ring = NULL;
1264 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1265 sc->age_cdata.age_rr_ring_tag = NULL;
1266 }
1267 /* CMB block */
1268 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1269 if (sc->age_rdata.age_cmb_block_paddr != 0)
1270 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1271 sc->age_cdata.age_cmb_block_map);
1272 if (sc->age_rdata.age_cmb_block != NULL)
1273 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1274 sc->age_rdata.age_cmb_block,
1275 sc->age_cdata.age_cmb_block_map);
1276 sc->age_rdata.age_cmb_block_paddr = 0;
1277 sc->age_rdata.age_cmb_block = NULL;
1278 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1279 sc->age_cdata.age_cmb_block_tag = NULL;
1280 }
1281 /* SMB block */
1282 if (sc->age_cdata.age_smb_block_tag != NULL) {
1283 if (sc->age_rdata.age_smb_block_paddr != 0)
1284 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1285 sc->age_cdata.age_smb_block_map);
1286 if (sc->age_rdata.age_smb_block != NULL)
1287 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1288 sc->age_rdata.age_smb_block,
1289 sc->age_cdata.age_smb_block_map);
1290 sc->age_rdata.age_smb_block_paddr = 0;
1291 sc->age_rdata.age_smb_block = NULL;
1292 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1293 sc->age_cdata.age_smb_block_tag = NULL;
1294 }
1295
1296 if (sc->age_cdata.age_buffer_tag != NULL) {
1297 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1298 sc->age_cdata.age_buffer_tag = NULL;
1299 }
1300 if (sc->age_cdata.age_parent_tag != NULL) {
1301 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1302 sc->age_cdata.age_parent_tag = NULL;
1303 }
1304 }
1305
1306 /*
1307 * Make sure the interface is stopped at reboot time.
1308 */
1309 static int
age_shutdown(device_t dev)1310 age_shutdown(device_t dev)
1311 {
1312
1313 return (age_suspend(dev));
1314 }
1315
1316 static void
age_setwol(struct age_softc * sc)1317 age_setwol(struct age_softc *sc)
1318 {
1319 if_t ifp;
1320 struct mii_data *mii;
1321 uint32_t reg, pmcs;
1322 uint16_t pmstat;
1323 int aneg, i, pmc;
1324
1325 AGE_LOCK_ASSERT(sc);
1326
1327 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1328 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1329 /*
1330 * No PME capability, PHY power down.
1331 * XXX
1332 * Due to an unknown reason powering down PHY resulted
1333 * in unexpected results such as inaccessbility of
1334 * hardware of freshly rebooted system. Disable
1335 * powering down PHY until I got more information for
1336 * Attansic/Atheros PHY hardwares.
1337 */
1338 #ifdef notyet
1339 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1340 MII_BMCR, BMCR_PDOWN);
1341 #endif
1342 return;
1343 }
1344
1345 ifp = sc->age_ifp;
1346 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1347 /*
1348 * Note, this driver resets the link speed to 10/100Mbps with
1349 * auto-negotiation but we don't know whether that operation
1350 * would succeed or not as it have no control after powering
1351 * off. If the renegotiation fail WOL may not work. Running
1352 * at 1Gbps will draw more power than 375mA at 3.3V which is
1353 * specified in PCI specification and that would result in
1354 * complete shutdowning power to ethernet controller.
1355 *
1356 * TODO
1357 * Save current negotiated media speed/duplex/flow-control
1358 * to softc and restore the same link again after resuming.
1359 * PHY handling such as power down/resetting to 100Mbps
1360 * may be better handled in suspend method in phy driver.
1361 */
1362 mii = device_get_softc(sc->age_miibus);
1363 mii_pollstat(mii);
1364 aneg = 0;
1365 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1366 switch IFM_SUBTYPE(mii->mii_media_active) {
1367 case IFM_10_T:
1368 case IFM_100_TX:
1369 goto got_link;
1370 case IFM_1000_T:
1371 aneg++;
1372 default:
1373 break;
1374 }
1375 }
1376 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1377 MII_100T2CR, 0);
1378 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1379 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1380 ANAR_10 | ANAR_CSMA);
1381 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1382 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1383 DELAY(1000);
1384 if (aneg != 0) {
1385 /* Poll link state until age(4) get a 10/100 link. */
1386 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1387 mii_pollstat(mii);
1388 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1389 switch (IFM_SUBTYPE(
1390 mii->mii_media_active)) {
1391 case IFM_10_T:
1392 case IFM_100_TX:
1393 age_mac_config(sc);
1394 goto got_link;
1395 default:
1396 break;
1397 }
1398 }
1399 AGE_UNLOCK(sc);
1400 pause("agelnk", hz);
1401 AGE_LOCK(sc);
1402 }
1403 if (i == MII_ANEGTICKS_GIGE)
1404 device_printf(sc->age_dev,
1405 "establishing link failed, "
1406 "WOL may not work!");
1407 }
1408 /*
1409 * No link, force MAC to have 100Mbps, full-duplex link.
1410 * This is the last resort and may/may not work.
1411 */
1412 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1413 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1414 age_mac_config(sc);
1415 }
1416
1417 got_link:
1418 pmcs = 0;
1419 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1420 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1421 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1422 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1423 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1424 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1425 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1426 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1427 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1428 reg |= MAC_CFG_RX_ENB;
1429 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1430 }
1431
1432 /* Request PME. */
1433 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1434 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1435 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1436 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1437 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1438 #ifdef notyet
1439 /* See above for powering down PHY issues. */
1440 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1441 /* No WOL, PHY power down. */
1442 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1443 MII_BMCR, BMCR_PDOWN);
1444 }
1445 #endif
1446 }
1447
1448 static int
age_suspend(device_t dev)1449 age_suspend(device_t dev)
1450 {
1451 struct age_softc *sc;
1452
1453 sc = device_get_softc(dev);
1454
1455 AGE_LOCK(sc);
1456 age_stop(sc);
1457 age_setwol(sc);
1458 AGE_UNLOCK(sc);
1459
1460 return (0);
1461 }
1462
1463 static int
age_resume(device_t dev)1464 age_resume(device_t dev)
1465 {
1466 struct age_softc *sc;
1467 if_t ifp;
1468
1469 sc = device_get_softc(dev);
1470
1471 AGE_LOCK(sc);
1472 age_phy_reset(sc);
1473 ifp = sc->age_ifp;
1474 if ((if_getflags(ifp) & IFF_UP) != 0)
1475 age_init_locked(sc);
1476
1477 AGE_UNLOCK(sc);
1478
1479 return (0);
1480 }
1481
1482 static int
age_encap(struct age_softc * sc,struct mbuf ** m_head)1483 age_encap(struct age_softc *sc, struct mbuf **m_head)
1484 {
1485 struct age_txdesc *txd, *txd_last;
1486 struct tx_desc *desc;
1487 struct mbuf *m;
1488 struct ip *ip;
1489 struct tcphdr *tcp;
1490 bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1491 bus_dmamap_t map;
1492 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1493 int error, i, nsegs, prod, si;
1494
1495 AGE_LOCK_ASSERT(sc);
1496
1497 M_ASSERTPKTHDR((*m_head));
1498
1499 m = *m_head;
1500 ip = NULL;
1501 tcp = NULL;
1502 cflags = vtag = 0;
1503 ip_off = poff = 0;
1504 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1505 /*
1506 * L1 requires offset of TCP/UDP payload in its Tx
1507 * descriptor to perform hardware Tx checksum offload.
1508 * Additionally, TSO requires IP/TCP header size and
1509 * modification of IP/TCP header in order to make TSO
1510 * engine work. This kind of operation takes many CPU
1511 * cycles on FreeBSD so fast host CPU is needed to get
1512 * smooth TSO performance.
1513 */
1514 struct ether_header *eh;
1515
1516 if (M_WRITABLE(m) == 0) {
1517 /* Get a writable copy. */
1518 m = m_dup(*m_head, M_NOWAIT);
1519 /* Release original mbufs. */
1520 m_freem(*m_head);
1521 if (m == NULL) {
1522 *m_head = NULL;
1523 return (ENOBUFS);
1524 }
1525 *m_head = m;
1526 }
1527 ip_off = sizeof(struct ether_header);
1528 m = m_pullup(m, ip_off);
1529 if (m == NULL) {
1530 *m_head = NULL;
1531 return (ENOBUFS);
1532 }
1533 eh = mtod(m, struct ether_header *);
1534 /*
1535 * Check if hardware VLAN insertion is off.
1536 * Additional check for LLC/SNAP frame?
1537 */
1538 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1539 ip_off = sizeof(struct ether_vlan_header);
1540 m = m_pullup(m, ip_off);
1541 if (m == NULL) {
1542 *m_head = NULL;
1543 return (ENOBUFS);
1544 }
1545 }
1546 m = m_pullup(m, ip_off + sizeof(struct ip));
1547 if (m == NULL) {
1548 *m_head = NULL;
1549 return (ENOBUFS);
1550 }
1551 ip = (struct ip *)(mtod(m, char *) + ip_off);
1552 poff = ip_off + (ip->ip_hl << 2);
1553 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1554 m = m_pullup(m, poff + sizeof(struct tcphdr));
1555 if (m == NULL) {
1556 *m_head = NULL;
1557 return (ENOBUFS);
1558 }
1559 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1560 m = m_pullup(m, poff + (tcp->th_off << 2));
1561 if (m == NULL) {
1562 *m_head = NULL;
1563 return (ENOBUFS);
1564 }
1565 /*
1566 * L1 requires IP/TCP header size and offset as
1567 * well as TCP pseudo checksum which complicates
1568 * TSO configuration. I guess this comes from the
1569 * adherence to Microsoft NDIS Large Send
1570 * specification which requires insertion of
1571 * pseudo checksum by upper stack. The pseudo
1572 * checksum that NDIS refers to doesn't include
1573 * TCP payload length so age(4) should recompute
1574 * the pseudo checksum here. Hopefully this wouldn't
1575 * be much burden on modern CPUs.
1576 * Reset IP checksum and recompute TCP pseudo
1577 * checksum as NDIS specification said.
1578 */
1579 ip = (struct ip *)(mtod(m, char *) + ip_off);
1580 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1581 ip->ip_sum = 0;
1582 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1583 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1584 }
1585 *m_head = m;
1586 }
1587
1588 si = prod = sc->age_cdata.age_tx_prod;
1589 txd = &sc->age_cdata.age_txdesc[prod];
1590 txd_last = txd;
1591 map = txd->tx_dmamap;
1592
1593 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1594 *m_head, txsegs, &nsegs, 0);
1595 if (error == EFBIG) {
1596 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1597 if (m == NULL) {
1598 m_freem(*m_head);
1599 *m_head = NULL;
1600 return (ENOMEM);
1601 }
1602 *m_head = m;
1603 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1604 *m_head, txsegs, &nsegs, 0);
1605 if (error != 0) {
1606 m_freem(*m_head);
1607 *m_head = NULL;
1608 return (error);
1609 }
1610 } else if (error != 0)
1611 return (error);
1612 if (nsegs == 0) {
1613 m_freem(*m_head);
1614 *m_head = NULL;
1615 return (EIO);
1616 }
1617
1618 /* Check descriptor overrun. */
1619 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1620 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1621 return (ENOBUFS);
1622 }
1623
1624 m = *m_head;
1625 /* Configure VLAN hardware tag insertion. */
1626 if ((m->m_flags & M_VLANTAG) != 0) {
1627 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1628 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1629 cflags |= AGE_TD_INSERT_VLAN_TAG;
1630 }
1631
1632 desc = NULL;
1633 i = 0;
1634 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1635 /* Request TSO and set MSS. */
1636 cflags |= AGE_TD_TSO_IPV4;
1637 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1638 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1639 AGE_TD_TSO_MSS_SHIFT);
1640 /* Set IP/TCP header size. */
1641 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1642 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1643 /*
1644 * L1 requires the first buffer should only hold IP/TCP
1645 * header data. TCP payload should be handled in other
1646 * descriptors.
1647 */
1648 hdrlen = poff + (tcp->th_off << 2);
1649 desc = &sc->age_rdata.age_tx_ring[prod];
1650 desc->addr = htole64(txsegs[0].ds_addr);
1651 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1652 desc->flags = htole32(cflags);
1653 sc->age_cdata.age_tx_cnt++;
1654 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1655 if (m->m_len - hdrlen > 0) {
1656 /* Handle remaining payload of the 1st fragment. */
1657 desc = &sc->age_rdata.age_tx_ring[prod];
1658 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1659 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1660 vtag);
1661 desc->flags = htole32(cflags);
1662 sc->age_cdata.age_tx_cnt++;
1663 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1664 }
1665 /* Handle remaining fragments. */
1666 i = 1;
1667 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1668 /* Configure Tx IP/TCP/UDP checksum offload. */
1669 cflags |= AGE_TD_CSUM;
1670 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1671 cflags |= AGE_TD_TCPCSUM;
1672 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1673 cflags |= AGE_TD_UDPCSUM;
1674 /* Set checksum start offset. */
1675 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1676 /* Set checksum insertion position of TCP/UDP. */
1677 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1678 AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1679 }
1680 for (; i < nsegs; i++) {
1681 desc = &sc->age_rdata.age_tx_ring[prod];
1682 desc->addr = htole64(txsegs[i].ds_addr);
1683 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1684 desc->flags = htole32(cflags);
1685 sc->age_cdata.age_tx_cnt++;
1686 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1687 }
1688 /* Update producer index. */
1689 sc->age_cdata.age_tx_prod = prod;
1690
1691 /* Set EOP on the last descriptor. */
1692 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1693 desc = &sc->age_rdata.age_tx_ring[prod];
1694 desc->flags |= htole32(AGE_TD_EOP);
1695
1696 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1697 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1698 desc = &sc->age_rdata.age_tx_ring[si];
1699 desc->flags |= htole32(AGE_TD_TSO_HDR);
1700 }
1701
1702 /* Swap dmamap of the first and the last. */
1703 txd = &sc->age_cdata.age_txdesc[prod];
1704 map = txd_last->tx_dmamap;
1705 txd_last->tx_dmamap = txd->tx_dmamap;
1706 txd->tx_dmamap = map;
1707 txd->tx_m = m;
1708
1709 /* Sync descriptors. */
1710 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1711 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1712 sc->age_cdata.age_tx_ring_map,
1713 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1714
1715 return (0);
1716 }
1717
1718 static void
age_start(if_t ifp)1719 age_start(if_t ifp)
1720 {
1721 struct age_softc *sc;
1722
1723 sc = if_getsoftc(ifp);
1724 AGE_LOCK(sc);
1725 age_start_locked(ifp);
1726 AGE_UNLOCK(sc);
1727 }
1728
1729 static void
age_start_locked(if_t ifp)1730 age_start_locked(if_t ifp)
1731 {
1732 struct age_softc *sc;
1733 struct mbuf *m_head;
1734 int enq;
1735
1736 sc = if_getsoftc(ifp);
1737
1738 AGE_LOCK_ASSERT(sc);
1739
1740 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1741 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1742 return;
1743
1744 for (enq = 0; !if_sendq_empty(ifp); ) {
1745 m_head = if_dequeue(ifp);
1746 if (m_head == NULL)
1747 break;
1748 /*
1749 * Pack the data into the transmit ring. If we
1750 * don't have room, set the OACTIVE flag and wait
1751 * for the NIC to drain the ring.
1752 */
1753 if (age_encap(sc, &m_head)) {
1754 if (m_head == NULL)
1755 break;
1756 if_sendq_prepend(ifp, m_head);
1757 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1758 break;
1759 }
1760
1761 enq++;
1762 /*
1763 * If there's a BPF listener, bounce a copy of this frame
1764 * to him.
1765 */
1766 ETHER_BPF_MTAP(ifp, m_head);
1767 }
1768
1769 if (enq > 0) {
1770 /* Update mbox. */
1771 AGE_COMMIT_MBOX(sc);
1772 /* Set a timeout in case the chip goes out to lunch. */
1773 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1774 }
1775 }
1776
1777 static void
age_watchdog(struct age_softc * sc)1778 age_watchdog(struct age_softc *sc)
1779 {
1780 if_t ifp;
1781
1782 AGE_LOCK_ASSERT(sc);
1783
1784 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1785 return;
1786
1787 ifp = sc->age_ifp;
1788 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1789 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1790 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1791 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1792 age_init_locked(sc);
1793 return;
1794 }
1795 if (sc->age_cdata.age_tx_cnt == 0) {
1796 if_printf(sc->age_ifp,
1797 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1798 if (!if_sendq_empty(ifp))
1799 age_start_locked(ifp);
1800 return;
1801 }
1802 if_printf(sc->age_ifp, "watchdog timeout\n");
1803 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1804 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1805 age_init_locked(sc);
1806 if (!if_sendq_empty(ifp))
1807 age_start_locked(ifp);
1808 }
1809
1810 static int
age_ioctl(if_t ifp,u_long cmd,caddr_t data)1811 age_ioctl(if_t ifp, u_long cmd, caddr_t data)
1812 {
1813 struct age_softc *sc;
1814 struct ifreq *ifr;
1815 struct mii_data *mii;
1816 uint32_t reg;
1817 int error, mask;
1818
1819 sc = if_getsoftc(ifp);
1820 ifr = (struct ifreq *)data;
1821 error = 0;
1822 switch (cmd) {
1823 case SIOCSIFMTU:
1824 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1825 error = EINVAL;
1826 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1827 AGE_LOCK(sc);
1828 if_setmtu(ifp, ifr->ifr_mtu);
1829 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1830 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1831 age_init_locked(sc);
1832 }
1833 AGE_UNLOCK(sc);
1834 }
1835 break;
1836 case SIOCSIFFLAGS:
1837 AGE_LOCK(sc);
1838 if ((if_getflags(ifp) & IFF_UP) != 0) {
1839 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1840 if (((if_getflags(ifp) ^ sc->age_if_flags)
1841 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1842 age_rxfilter(sc);
1843 } else {
1844 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1845 age_init_locked(sc);
1846 }
1847 } else {
1848 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1849 age_stop(sc);
1850 }
1851 sc->age_if_flags = if_getflags(ifp);
1852 AGE_UNLOCK(sc);
1853 break;
1854 case SIOCADDMULTI:
1855 case SIOCDELMULTI:
1856 AGE_LOCK(sc);
1857 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1858 age_rxfilter(sc);
1859 AGE_UNLOCK(sc);
1860 break;
1861 case SIOCSIFMEDIA:
1862 case SIOCGIFMEDIA:
1863 mii = device_get_softc(sc->age_miibus);
1864 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1865 break;
1866 case SIOCSIFCAP:
1867 AGE_LOCK(sc);
1868 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1869 if ((mask & IFCAP_TXCSUM) != 0 &&
1870 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1871 if_togglecapenable(ifp, IFCAP_TXCSUM);
1872 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1873 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0);
1874 else
1875 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES);
1876 }
1877 if ((mask & IFCAP_RXCSUM) != 0 &&
1878 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1879 if_togglecapenable(ifp, IFCAP_RXCSUM);
1880 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1881 reg &= ~MAC_CFG_RXCSUM_ENB;
1882 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1883 reg |= MAC_CFG_RXCSUM_ENB;
1884 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1885 }
1886 if ((mask & IFCAP_TSO4) != 0 &&
1887 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
1888 if_togglecapenable(ifp, IFCAP_TSO4);
1889 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
1890 if_sethwassistbits(ifp, CSUM_TSO, 0);
1891 else
1892 if_sethwassistbits(ifp, 0, CSUM_TSO);
1893 }
1894
1895 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1896 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
1897 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
1898 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1899 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
1900 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1901 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1902 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
1903 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1904 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1905 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
1906 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1907 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1908 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1909 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1910 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
1911 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
1912 age_rxvlan(sc);
1913 }
1914 AGE_UNLOCK(sc);
1915 VLAN_CAPABILITIES(ifp);
1916 break;
1917 default:
1918 error = ether_ioctl(ifp, cmd, data);
1919 break;
1920 }
1921
1922 return (error);
1923 }
1924
1925 static void
age_mac_config(struct age_softc * sc)1926 age_mac_config(struct age_softc *sc)
1927 {
1928 struct mii_data *mii;
1929 uint32_t reg;
1930
1931 AGE_LOCK_ASSERT(sc);
1932
1933 mii = device_get_softc(sc->age_miibus);
1934 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1935 reg &= ~MAC_CFG_FULL_DUPLEX;
1936 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1937 reg &= ~MAC_CFG_SPEED_MASK;
1938 /* Reprogram MAC with resolved speed/duplex. */
1939 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1940 case IFM_10_T:
1941 case IFM_100_TX:
1942 reg |= MAC_CFG_SPEED_10_100;
1943 break;
1944 case IFM_1000_T:
1945 reg |= MAC_CFG_SPEED_1000;
1946 break;
1947 }
1948 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1949 reg |= MAC_CFG_FULL_DUPLEX;
1950 #ifdef notyet
1951 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1952 reg |= MAC_CFG_TX_FC;
1953 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1954 reg |= MAC_CFG_RX_FC;
1955 #endif
1956 }
1957
1958 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1959 }
1960
1961 static void
age_link_task(void * arg,int pending)1962 age_link_task(void *arg, int pending)
1963 {
1964 struct age_softc *sc;
1965 struct mii_data *mii;
1966 if_t ifp;
1967 uint32_t reg;
1968
1969 sc = (struct age_softc *)arg;
1970
1971 AGE_LOCK(sc);
1972 mii = device_get_softc(sc->age_miibus);
1973 ifp = sc->age_ifp;
1974 if (mii == NULL || ifp == NULL ||
1975 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1976 AGE_UNLOCK(sc);
1977 return;
1978 }
1979
1980 sc->age_flags &= ~AGE_FLAG_LINK;
1981 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1982 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1983 case IFM_10_T:
1984 case IFM_100_TX:
1985 case IFM_1000_T:
1986 sc->age_flags |= AGE_FLAG_LINK;
1987 break;
1988 default:
1989 break;
1990 }
1991 }
1992
1993 /* Stop Rx/Tx MACs. */
1994 age_stop_rxmac(sc);
1995 age_stop_txmac(sc);
1996
1997 /* Program MACs with resolved speed/duplex/flow-control. */
1998 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1999 age_mac_config(sc);
2000 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2001 /* Restart DMA engine and Tx/Rx MAC. */
2002 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2003 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
2004 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2005 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2006 }
2007
2008 AGE_UNLOCK(sc);
2009 }
2010
2011 static void
age_stats_update(struct age_softc * sc)2012 age_stats_update(struct age_softc *sc)
2013 {
2014 struct age_stats *stat;
2015 struct smb *smb;
2016 if_t ifp;
2017
2018 AGE_LOCK_ASSERT(sc);
2019
2020 stat = &sc->age_stat;
2021
2022 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2023 sc->age_cdata.age_smb_block_map,
2024 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2025
2026 smb = sc->age_rdata.age_smb_block;
2027 if (smb->updated == 0)
2028 return;
2029
2030 ifp = sc->age_ifp;
2031 /* Rx stats. */
2032 stat->rx_frames += smb->rx_frames;
2033 stat->rx_bcast_frames += smb->rx_bcast_frames;
2034 stat->rx_mcast_frames += smb->rx_mcast_frames;
2035 stat->rx_pause_frames += smb->rx_pause_frames;
2036 stat->rx_control_frames += smb->rx_control_frames;
2037 stat->rx_crcerrs += smb->rx_crcerrs;
2038 stat->rx_lenerrs += smb->rx_lenerrs;
2039 stat->rx_bytes += smb->rx_bytes;
2040 stat->rx_runts += smb->rx_runts;
2041 stat->rx_fragments += smb->rx_fragments;
2042 stat->rx_pkts_64 += smb->rx_pkts_64;
2043 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2044 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2045 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2046 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2047 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2048 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2049 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2050 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2051 stat->rx_desc_oflows += smb->rx_desc_oflows;
2052 stat->rx_alignerrs += smb->rx_alignerrs;
2053 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2054 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2055 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2056
2057 /* Tx stats. */
2058 stat->tx_frames += smb->tx_frames;
2059 stat->tx_bcast_frames += smb->tx_bcast_frames;
2060 stat->tx_mcast_frames += smb->tx_mcast_frames;
2061 stat->tx_pause_frames += smb->tx_pause_frames;
2062 stat->tx_excess_defer += smb->tx_excess_defer;
2063 stat->tx_control_frames += smb->tx_control_frames;
2064 stat->tx_deferred += smb->tx_deferred;
2065 stat->tx_bytes += smb->tx_bytes;
2066 stat->tx_pkts_64 += smb->tx_pkts_64;
2067 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2068 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2069 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2070 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2071 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2072 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2073 stat->tx_single_colls += smb->tx_single_colls;
2074 stat->tx_multi_colls += smb->tx_multi_colls;
2075 stat->tx_late_colls += smb->tx_late_colls;
2076 stat->tx_excess_colls += smb->tx_excess_colls;
2077 stat->tx_underrun += smb->tx_underrun;
2078 stat->tx_desc_underrun += smb->tx_desc_underrun;
2079 stat->tx_lenerrs += smb->tx_lenerrs;
2080 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2081 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2082 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2083
2084 /* Update counters in ifnet. */
2085 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2086
2087 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2088 smb->tx_multi_colls + smb->tx_late_colls +
2089 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2090
2091 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2092 smb->tx_late_colls + smb->tx_underrun +
2093 smb->tx_pkts_truncated);
2094
2095 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2096
2097 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2098 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2099 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2100 smb->rx_alignerrs);
2101
2102 /* Update done, clear. */
2103 smb->updated = 0;
2104
2105 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2106 sc->age_cdata.age_smb_block_map,
2107 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2108 }
2109
2110 static int
age_intr(void * arg)2111 age_intr(void *arg)
2112 {
2113 struct age_softc *sc;
2114 uint32_t status;
2115
2116 sc = (struct age_softc *)arg;
2117
2118 status = CSR_READ_4(sc, AGE_INTR_STATUS);
2119 if (status == 0 || (status & AGE_INTRS) == 0)
2120 return (FILTER_STRAY);
2121 /* Disable interrupts. */
2122 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2123 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2124
2125 return (FILTER_HANDLED);
2126 }
2127
2128 static void
age_int_task(void * arg,int pending)2129 age_int_task(void *arg, int pending)
2130 {
2131 struct age_softc *sc;
2132 if_t ifp;
2133 struct cmb *cmb;
2134 uint32_t status;
2135
2136 sc = (struct age_softc *)arg;
2137
2138 AGE_LOCK(sc);
2139
2140 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2141 sc->age_cdata.age_cmb_block_map,
2142 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2143 cmb = sc->age_rdata.age_cmb_block;
2144 status = le32toh(cmb->intr_status);
2145 if (sc->age_morework != 0)
2146 status |= INTR_CMB_RX;
2147 if ((status & AGE_INTRS) == 0)
2148 goto done;
2149
2150 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2151 TPD_CONS_SHIFT;
2152 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2153 RRD_PROD_SHIFT;
2154 /* Let hardware know CMB was served. */
2155 cmb->intr_status = 0;
2156 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2157 sc->age_cdata.age_cmb_block_map,
2158 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2159
2160 ifp = sc->age_ifp;
2161 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2162 if ((status & INTR_CMB_RX) != 0)
2163 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2164 sc->age_process_limit);
2165 if ((status & INTR_CMB_TX) != 0)
2166 age_txintr(sc, sc->age_tpd_cons);
2167 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2168 if ((status & INTR_DMA_RD_TO_RST) != 0)
2169 device_printf(sc->age_dev,
2170 "DMA read error! -- resetting\n");
2171 if ((status & INTR_DMA_WR_TO_RST) != 0)
2172 device_printf(sc->age_dev,
2173 "DMA write error! -- resetting\n");
2174 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2175 age_init_locked(sc);
2176 }
2177 if (!if_sendq_empty(ifp))
2178 age_start_locked(ifp);
2179 if ((status & INTR_SMB) != 0)
2180 age_stats_update(sc);
2181 }
2182
2183 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2184 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2185 sc->age_cdata.age_cmb_block_map,
2186 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2187 status = le32toh(cmb->intr_status);
2188 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2189 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2190 AGE_UNLOCK(sc);
2191 return;
2192 }
2193
2194 done:
2195 /* Re-enable interrupts. */
2196 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2197 AGE_UNLOCK(sc);
2198 }
2199
2200 static void
age_txintr(struct age_softc * sc,int tpd_cons)2201 age_txintr(struct age_softc *sc, int tpd_cons)
2202 {
2203 if_t ifp;
2204 struct age_txdesc *txd;
2205 int cons, prog;
2206
2207 AGE_LOCK_ASSERT(sc);
2208
2209 ifp = sc->age_ifp;
2210
2211 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2212 sc->age_cdata.age_tx_ring_map,
2213 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2214
2215 /*
2216 * Go through our Tx list and free mbufs for those
2217 * frames which have been transmitted.
2218 */
2219 cons = sc->age_cdata.age_tx_cons;
2220 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2221 if (sc->age_cdata.age_tx_cnt <= 0)
2222 break;
2223 prog++;
2224 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2225 sc->age_cdata.age_tx_cnt--;
2226 txd = &sc->age_cdata.age_txdesc[cons];
2227 /*
2228 * Clear Tx descriptors, it's not required but would
2229 * help debugging in case of Tx issues.
2230 */
2231 txd->tx_desc->addr = 0;
2232 txd->tx_desc->len = 0;
2233 txd->tx_desc->flags = 0;
2234
2235 if (txd->tx_m == NULL)
2236 continue;
2237 /* Reclaim transmitted mbufs. */
2238 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2239 BUS_DMASYNC_POSTWRITE);
2240 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2241 m_freem(txd->tx_m);
2242 txd->tx_m = NULL;
2243 }
2244
2245 if (prog > 0) {
2246 sc->age_cdata.age_tx_cons = cons;
2247
2248 /*
2249 * Unarm watchdog timer only when there are no pending
2250 * Tx descriptors in queue.
2251 */
2252 if (sc->age_cdata.age_tx_cnt == 0)
2253 sc->age_watchdog_timer = 0;
2254 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2255 sc->age_cdata.age_tx_ring_map,
2256 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2257 }
2258 }
2259
2260 #ifndef __NO_STRICT_ALIGNMENT
2261 static struct mbuf *
age_fixup_rx(if_t ifp,struct mbuf * m)2262 age_fixup_rx(if_t ifp, struct mbuf *m)
2263 {
2264 struct mbuf *n;
2265 int i;
2266 uint16_t *src, *dst;
2267
2268 src = mtod(m, uint16_t *);
2269 dst = src - 3;
2270
2271 if (m->m_next == NULL) {
2272 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2273 *dst++ = *src++;
2274 m->m_data -= 6;
2275 return (m);
2276 }
2277 /*
2278 * Append a new mbuf to received mbuf chain and copy ethernet
2279 * header from the mbuf chain. This can save lots of CPU
2280 * cycles for jumbo frame.
2281 */
2282 MGETHDR(n, M_NOWAIT, MT_DATA);
2283 if (n == NULL) {
2284 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2285 m_freem(m);
2286 return (NULL);
2287 }
2288 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2289 m->m_data += ETHER_HDR_LEN;
2290 m->m_len -= ETHER_HDR_LEN;
2291 n->m_len = ETHER_HDR_LEN;
2292 M_MOVE_PKTHDR(n, m);
2293 n->m_next = m;
2294 return (n);
2295 }
2296 #endif
2297
2298 /* Receive a frame. */
2299 static void
age_rxeof(struct age_softc * sc,struct rx_rdesc * rxrd)2300 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2301 {
2302 struct age_rxdesc *rxd;
2303 if_t ifp;
2304 struct mbuf *mp, *m;
2305 uint32_t status, index, vtag;
2306 int count, nsegs;
2307 int rx_cons;
2308
2309 AGE_LOCK_ASSERT(sc);
2310
2311 ifp = sc->age_ifp;
2312 status = le32toh(rxrd->flags);
2313 index = le32toh(rxrd->index);
2314 rx_cons = AGE_RX_CONS(index);
2315 nsegs = AGE_RX_NSEGS(index);
2316
2317 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2318 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2319 /*
2320 * We want to pass the following frames to upper
2321 * layer regardless of error status of Rx return
2322 * ring.
2323 *
2324 * o IP/TCP/UDP checksum is bad.
2325 * o frame length and protocol specific length
2326 * does not match.
2327 */
2328 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2329 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2330 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2331 return;
2332 }
2333
2334 for (count = 0; count < nsegs; count++,
2335 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2336 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2337 mp = rxd->rx_m;
2338 /* Add a new receive buffer to the ring. */
2339 if (age_newbuf(sc, rxd) != 0) {
2340 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2341 /* Reuse Rx buffers. */
2342 if (sc->age_cdata.age_rxhead != NULL)
2343 m_freem(sc->age_cdata.age_rxhead);
2344 break;
2345 }
2346
2347 /*
2348 * Assume we've received a full sized frame.
2349 * Actual size is fixed when we encounter the end of
2350 * multi-segmented frame.
2351 */
2352 mp->m_len = AGE_RX_BUF_SIZE;
2353
2354 /* Chain received mbufs. */
2355 if (sc->age_cdata.age_rxhead == NULL) {
2356 sc->age_cdata.age_rxhead = mp;
2357 sc->age_cdata.age_rxtail = mp;
2358 } else {
2359 mp->m_flags &= ~M_PKTHDR;
2360 sc->age_cdata.age_rxprev_tail =
2361 sc->age_cdata.age_rxtail;
2362 sc->age_cdata.age_rxtail->m_next = mp;
2363 sc->age_cdata.age_rxtail = mp;
2364 }
2365
2366 if (count == nsegs - 1) {
2367 /* Last desc. for this frame. */
2368 m = sc->age_cdata.age_rxhead;
2369 m->m_flags |= M_PKTHDR;
2370 /*
2371 * It seems that L1 controller has no way
2372 * to tell hardware to strip CRC bytes.
2373 */
2374 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2375 ETHER_CRC_LEN;
2376 if (nsegs > 1) {
2377 /* Set last mbuf size. */
2378 mp->m_len = sc->age_cdata.age_rxlen -
2379 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2380 /* Remove the CRC bytes in chained mbufs. */
2381 if (mp->m_len <= ETHER_CRC_LEN) {
2382 sc->age_cdata.age_rxtail =
2383 sc->age_cdata.age_rxprev_tail;
2384 sc->age_cdata.age_rxtail->m_len -=
2385 (ETHER_CRC_LEN - mp->m_len);
2386 sc->age_cdata.age_rxtail->m_next = NULL;
2387 m_freem(mp);
2388 } else {
2389 mp->m_len -= ETHER_CRC_LEN;
2390 }
2391 } else
2392 m->m_len = m->m_pkthdr.len;
2393 m->m_pkthdr.rcvif = ifp;
2394 /*
2395 * Set checksum information.
2396 * It seems that L1 controller can compute partial
2397 * checksum. The partial checksum value can be used
2398 * to accelerate checksum computation for fragmented
2399 * TCP/UDP packets. Upper network stack already
2400 * takes advantage of the partial checksum value in
2401 * IP reassembly stage. But I'm not sure the
2402 * correctness of the partial hardware checksum
2403 * assistance due to lack of data sheet. If it is
2404 * proven to work on L1 I'll enable it.
2405 */
2406 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2407 (status & AGE_RRD_IPV4) != 0) {
2408 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2409 m->m_pkthdr.csum_flags |=
2410 CSUM_IP_CHECKED | CSUM_IP_VALID;
2411 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2412 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2413 m->m_pkthdr.csum_flags |=
2414 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2415 m->m_pkthdr.csum_data = 0xffff;
2416 }
2417 /*
2418 * Don't mark bad checksum for TCP/UDP frames
2419 * as fragmented frames may always have set
2420 * bad checksummed bit of descriptor status.
2421 */
2422 }
2423
2424 /* Check for VLAN tagged frames. */
2425 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2426 (status & AGE_RRD_VLAN) != 0) {
2427 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2428 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2429 m->m_flags |= M_VLANTAG;
2430 }
2431 #ifndef __NO_STRICT_ALIGNMENT
2432 m = age_fixup_rx(ifp, m);
2433 if (m != NULL)
2434 #endif
2435 {
2436 /* Pass it on. */
2437 AGE_UNLOCK(sc);
2438 if_input(ifp, m);
2439 AGE_LOCK(sc);
2440 }
2441 }
2442 }
2443
2444 /* Reset mbuf chains. */
2445 AGE_RXCHAIN_RESET(sc);
2446 }
2447
2448 static int
age_rxintr(struct age_softc * sc,int rr_prod,int count)2449 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2450 {
2451 struct rx_rdesc *rxrd;
2452 int rr_cons, nsegs, pktlen, prog;
2453
2454 AGE_LOCK_ASSERT(sc);
2455
2456 rr_cons = sc->age_cdata.age_rr_cons;
2457 if (rr_cons == rr_prod)
2458 return (0);
2459
2460 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2461 sc->age_cdata.age_rr_ring_map,
2462 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2463 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2464 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2465
2466 for (prog = 0; rr_cons != rr_prod; prog++) {
2467 if (count-- <= 0)
2468 break;
2469 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2470 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2471 if (nsegs == 0)
2472 break;
2473 /*
2474 * Check number of segments against received bytes.
2475 * Non-matching value would indicate that hardware
2476 * is still trying to update Rx return descriptors.
2477 * I'm not sure whether this check is really needed.
2478 */
2479 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2480 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2481 break;
2482
2483 /* Received a frame. */
2484 age_rxeof(sc, rxrd);
2485 /* Clear return ring. */
2486 rxrd->index = 0;
2487 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2488 sc->age_cdata.age_rx_cons += nsegs;
2489 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2490 }
2491
2492 if (prog > 0) {
2493 /* Update the consumer index. */
2494 sc->age_cdata.age_rr_cons = rr_cons;
2495
2496 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2497 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2498 /* Sync descriptors. */
2499 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2500 sc->age_cdata.age_rr_ring_map,
2501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2502
2503 /* Notify hardware availability of new Rx buffers. */
2504 AGE_COMMIT_MBOX(sc);
2505 }
2506
2507 return (count > 0 ? 0 : EAGAIN);
2508 }
2509
2510 static void
age_tick(void * arg)2511 age_tick(void *arg)
2512 {
2513 struct age_softc *sc;
2514 struct mii_data *mii;
2515
2516 sc = (struct age_softc *)arg;
2517
2518 AGE_LOCK_ASSERT(sc);
2519
2520 mii = device_get_softc(sc->age_miibus);
2521 mii_tick(mii);
2522 age_watchdog(sc);
2523 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2524 }
2525
2526 static void
age_reset(struct age_softc * sc)2527 age_reset(struct age_softc *sc)
2528 {
2529 uint32_t reg;
2530 int i;
2531
2532 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2533 CSR_READ_4(sc, AGE_MASTER_CFG);
2534 DELAY(1000);
2535 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2536 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2537 break;
2538 DELAY(10);
2539 }
2540
2541 if (i == 0)
2542 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2543 /* Initialize PCIe module. From Linux. */
2544 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2545 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2546 }
2547
2548 static void
age_init(void * xsc)2549 age_init(void *xsc)
2550 {
2551 struct age_softc *sc;
2552
2553 sc = (struct age_softc *)xsc;
2554 AGE_LOCK(sc);
2555 age_init_locked(sc);
2556 AGE_UNLOCK(sc);
2557 }
2558
2559 static void
age_init_locked(struct age_softc * sc)2560 age_init_locked(struct age_softc *sc)
2561 {
2562 if_t ifp;
2563 struct mii_data *mii;
2564 uint8_t eaddr[ETHER_ADDR_LEN];
2565 bus_addr_t paddr;
2566 uint32_t reg, fsize;
2567 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2568 int error;
2569
2570 AGE_LOCK_ASSERT(sc);
2571
2572 ifp = sc->age_ifp;
2573 mii = device_get_softc(sc->age_miibus);
2574
2575 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2576 return;
2577
2578 /*
2579 * Cancel any pending I/O.
2580 */
2581 age_stop(sc);
2582
2583 /*
2584 * Reset the chip to a known state.
2585 */
2586 age_reset(sc);
2587
2588 /* Initialize descriptors. */
2589 error = age_init_rx_ring(sc);
2590 if (error != 0) {
2591 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2592 age_stop(sc);
2593 return;
2594 }
2595 age_init_rr_ring(sc);
2596 age_init_tx_ring(sc);
2597 age_init_cmb_block(sc);
2598 age_init_smb_block(sc);
2599
2600 /* Reprogram the station address. */
2601 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2602 CSR_WRITE_4(sc, AGE_PAR0,
2603 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2604 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2605
2606 /* Set descriptor base addresses. */
2607 paddr = sc->age_rdata.age_tx_ring_paddr;
2608 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2609 paddr = sc->age_rdata.age_rx_ring_paddr;
2610 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2611 paddr = sc->age_rdata.age_rr_ring_paddr;
2612 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2613 paddr = sc->age_rdata.age_tx_ring_paddr;
2614 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2615 paddr = sc->age_rdata.age_cmb_block_paddr;
2616 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2617 paddr = sc->age_rdata.age_smb_block_paddr;
2618 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2619 /* Set Rx/Rx return descriptor counter. */
2620 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2621 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2622 DESC_RRD_CNT_MASK) |
2623 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2624 /* Set Tx descriptor counter. */
2625 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2626 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2627
2628 /* Tell hardware that we're ready to load descriptors. */
2629 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2630
2631 /*
2632 * Initialize mailbox register.
2633 * Updated producer/consumer index information is exchanged
2634 * through this mailbox register. However Tx producer and
2635 * Rx return consumer/Rx producer are all shared such that
2636 * it's hard to separate code path between Tx and Rx without
2637 * locking. If L1 hardware have a separate mail box register
2638 * for Tx and Rx consumer/producer management we could have
2639 * independent Tx/Rx handler which in turn Rx handler could have
2640 * been run without any locking.
2641 */
2642 AGE_COMMIT_MBOX(sc);
2643
2644 /* Configure IPG/IFG parameters. */
2645 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2646 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2647 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2648 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2649 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2650
2651 /* Set parameters for half-duplex media. */
2652 CSR_WRITE_4(sc, AGE_HDPX_CFG,
2653 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2654 HDPX_CFG_LCOL_MASK) |
2655 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2656 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2657 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2658 HDPX_CFG_ABEBT_MASK) |
2659 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2660 HDPX_CFG_JAMIPG_MASK));
2661
2662 /* Configure interrupt moderation timer. */
2663 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2664 reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2665 reg &= ~MASTER_MTIMER_ENB;
2666 if (AGE_USECS(sc->age_int_mod) == 0)
2667 reg &= ~MASTER_ITIMER_ENB;
2668 else
2669 reg |= MASTER_ITIMER_ENB;
2670 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2671 if (bootverbose)
2672 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2673 sc->age_int_mod);
2674 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2675
2676 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2677 if (if_getmtu(ifp) < ETHERMTU)
2678 sc->age_max_frame_size = ETHERMTU;
2679 else
2680 sc->age_max_frame_size = if_getmtu(ifp);
2681 sc->age_max_frame_size += ETHER_HDR_LEN +
2682 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2683 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2684 /* Configure jumbo frame. */
2685 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2686 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2687 (((fsize / sizeof(uint64_t)) <<
2688 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2689 ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2690 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2691 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2692 RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2693
2694 /* Configure flow-control parameters. From Linux. */
2695 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2696 /*
2697 * Magic workaround for old-L1.
2698 * Don't know which hw revision requires this magic.
2699 */
2700 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2701 /*
2702 * Another magic workaround for flow-control mode
2703 * change. From Linux.
2704 */
2705 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2706 }
2707 /*
2708 * TODO
2709 * Should understand pause parameter relationships between FIFO
2710 * size and number of Rx descriptors and Rx return descriptors.
2711 *
2712 * Magic parameters came from Linux.
2713 */
2714 switch (sc->age_chip_rev) {
2715 case 0x8001:
2716 case 0x9001:
2717 case 0x9002:
2718 case 0x9003:
2719 rxf_hi = AGE_RX_RING_CNT / 16;
2720 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2721 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2722 rrd_lo = AGE_RR_RING_CNT / 16;
2723 break;
2724 default:
2725 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2726 rxf_lo = reg / 16;
2727 if (rxf_lo < 192)
2728 rxf_lo = 192;
2729 rxf_hi = (reg * 7) / 8;
2730 if (rxf_hi < rxf_lo)
2731 rxf_hi = rxf_lo + 16;
2732 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2733 rrd_lo = reg / 8;
2734 rrd_hi = (reg * 7) / 8;
2735 if (rrd_lo < 2)
2736 rrd_lo = 2;
2737 if (rrd_hi < rrd_lo)
2738 rrd_hi = rrd_lo + 3;
2739 break;
2740 }
2741 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2742 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2743 RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2744 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2745 RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2746 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2747 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2748 RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2749 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2750 RXQ_RRD_PAUSE_THRESH_HI_MASK));
2751
2752 /* Configure RxQ. */
2753 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2754 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2755 RXQ_CFG_RD_BURST_MASK) |
2756 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2757 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2758 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2759 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2760 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2761
2762 /* Configure TxQ. */
2763 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2764 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2765 TXQ_CFG_TPD_BURST_MASK) |
2766 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2767 TXQ_CFG_TX_FIFO_BURST_MASK) |
2768 ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2769 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2770 TXQ_CFG_ENB);
2771
2772 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2773 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2774 TX_JUMBO_TPD_TH_MASK) |
2775 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2776 TX_JUMBO_TPD_IPG_MASK));
2777 /* Configure DMA parameters. */
2778 CSR_WRITE_4(sc, AGE_DMA_CFG,
2779 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2780 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2781 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2782
2783 /* Configure CMB DMA write threshold. */
2784 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2785 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2786 CMB_WR_THRESH_RRD_MASK) |
2787 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2788 CMB_WR_THRESH_TPD_MASK));
2789
2790 /* Set CMB/SMB timer and enable them. */
2791 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2792 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2793 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2794 /* Request SMB updates for every seconds. */
2795 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2796 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2797
2798 /*
2799 * Disable all WOL bits as WOL can interfere normal Rx
2800 * operation.
2801 */
2802 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2803
2804 /*
2805 * Configure Tx/Rx MACs.
2806 * - Auto-padding for short frames.
2807 * - Enable CRC generation.
2808 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2809 * of MAC is followed after link establishment.
2810 */
2811 CSR_WRITE_4(sc, AGE_MAC_CFG,
2812 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2813 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2814 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2815 MAC_CFG_PREAMBLE_MASK));
2816 /* Set up the receive filter. */
2817 age_rxfilter(sc);
2818 age_rxvlan(sc);
2819
2820 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2821 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2822 reg |= MAC_CFG_RXCSUM_ENB;
2823
2824 /* Ack all pending interrupts and clear it. */
2825 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2826 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2827
2828 /* Finally enable Tx/Rx MAC. */
2829 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2830
2831 sc->age_flags &= ~AGE_FLAG_LINK;
2832 /* Switch to the current media. */
2833 mii_mediachg(mii);
2834
2835 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2836
2837 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2838 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2839 }
2840
2841 static void
age_stop(struct age_softc * sc)2842 age_stop(struct age_softc *sc)
2843 {
2844 if_t ifp;
2845 struct age_txdesc *txd;
2846 struct age_rxdesc *rxd;
2847 uint32_t reg;
2848 int i;
2849
2850 AGE_LOCK_ASSERT(sc);
2851 /*
2852 * Mark the interface down and cancel the watchdog timer.
2853 */
2854 ifp = sc->age_ifp;
2855 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2856 sc->age_flags &= ~AGE_FLAG_LINK;
2857 callout_stop(&sc->age_tick_ch);
2858 sc->age_watchdog_timer = 0;
2859
2860 /*
2861 * Disable interrupts.
2862 */
2863 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2864 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2865 /* Stop CMB/SMB updates. */
2866 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2867 /* Stop Rx/Tx MAC. */
2868 age_stop_rxmac(sc);
2869 age_stop_txmac(sc);
2870 /* Stop DMA. */
2871 CSR_WRITE_4(sc, AGE_DMA_CFG,
2872 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2873 /* Stop TxQ/RxQ. */
2874 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2875 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2876 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2877 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2878 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2879 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2880 break;
2881 DELAY(10);
2882 }
2883 if (i == 0)
2884 device_printf(sc->age_dev,
2885 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2886
2887 /* Reclaim Rx buffers that have been processed. */
2888 if (sc->age_cdata.age_rxhead != NULL)
2889 m_freem(sc->age_cdata.age_rxhead);
2890 AGE_RXCHAIN_RESET(sc);
2891 /*
2892 * Free RX and TX mbufs still in the queues.
2893 */
2894 for (i = 0; i < AGE_RX_RING_CNT; i++) {
2895 rxd = &sc->age_cdata.age_rxdesc[i];
2896 if (rxd->rx_m != NULL) {
2897 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2898 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2899 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2900 rxd->rx_dmamap);
2901 m_freem(rxd->rx_m);
2902 rxd->rx_m = NULL;
2903 }
2904 }
2905 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2906 txd = &sc->age_cdata.age_txdesc[i];
2907 if (txd->tx_m != NULL) {
2908 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2909 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2910 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2911 txd->tx_dmamap);
2912 m_freem(txd->tx_m);
2913 txd->tx_m = NULL;
2914 }
2915 }
2916 }
2917
2918 static void
age_stop_txmac(struct age_softc * sc)2919 age_stop_txmac(struct age_softc *sc)
2920 {
2921 uint32_t reg;
2922 int i;
2923
2924 AGE_LOCK_ASSERT(sc);
2925
2926 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2927 if ((reg & MAC_CFG_TX_ENB) != 0) {
2928 reg &= ~MAC_CFG_TX_ENB;
2929 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2930 }
2931 /* Stop Tx DMA engine. */
2932 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2933 if ((reg & DMA_CFG_RD_ENB) != 0) {
2934 reg &= ~DMA_CFG_RD_ENB;
2935 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2936 }
2937 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2938 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2939 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2940 break;
2941 DELAY(10);
2942 }
2943 if (i == 0)
2944 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2945 }
2946
2947 static void
age_stop_rxmac(struct age_softc * sc)2948 age_stop_rxmac(struct age_softc *sc)
2949 {
2950 uint32_t reg;
2951 int i;
2952
2953 AGE_LOCK_ASSERT(sc);
2954
2955 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2956 if ((reg & MAC_CFG_RX_ENB) != 0) {
2957 reg &= ~MAC_CFG_RX_ENB;
2958 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2959 }
2960 /* Stop Rx DMA engine. */
2961 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2962 if ((reg & DMA_CFG_WR_ENB) != 0) {
2963 reg &= ~DMA_CFG_WR_ENB;
2964 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2965 }
2966 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2967 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2968 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2969 break;
2970 DELAY(10);
2971 }
2972 if (i == 0)
2973 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2974 }
2975
2976 static void
age_init_tx_ring(struct age_softc * sc)2977 age_init_tx_ring(struct age_softc *sc)
2978 {
2979 struct age_ring_data *rd;
2980 struct age_txdesc *txd;
2981 int i;
2982
2983 AGE_LOCK_ASSERT(sc);
2984
2985 sc->age_cdata.age_tx_prod = 0;
2986 sc->age_cdata.age_tx_cons = 0;
2987 sc->age_cdata.age_tx_cnt = 0;
2988
2989 rd = &sc->age_rdata;
2990 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2991 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2992 txd = &sc->age_cdata.age_txdesc[i];
2993 txd->tx_desc = &rd->age_tx_ring[i];
2994 txd->tx_m = NULL;
2995 }
2996
2997 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2998 sc->age_cdata.age_tx_ring_map,
2999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3000 }
3001
3002 static int
age_init_rx_ring(struct age_softc * sc)3003 age_init_rx_ring(struct age_softc *sc)
3004 {
3005 struct age_ring_data *rd;
3006 struct age_rxdesc *rxd;
3007 int i;
3008
3009 AGE_LOCK_ASSERT(sc);
3010
3011 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
3012 sc->age_morework = 0;
3013 rd = &sc->age_rdata;
3014 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3015 for (i = 0; i < AGE_RX_RING_CNT; i++) {
3016 rxd = &sc->age_cdata.age_rxdesc[i];
3017 rxd->rx_m = NULL;
3018 rxd->rx_desc = &rd->age_rx_ring[i];
3019 if (age_newbuf(sc, rxd) != 0)
3020 return (ENOBUFS);
3021 }
3022
3023 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3024 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3025
3026 return (0);
3027 }
3028
3029 static void
age_init_rr_ring(struct age_softc * sc)3030 age_init_rr_ring(struct age_softc *sc)
3031 {
3032 struct age_ring_data *rd;
3033
3034 AGE_LOCK_ASSERT(sc);
3035
3036 sc->age_cdata.age_rr_cons = 0;
3037 AGE_RXCHAIN_RESET(sc);
3038
3039 rd = &sc->age_rdata;
3040 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3041 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3042 sc->age_cdata.age_rr_ring_map,
3043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3044 }
3045
3046 static void
age_init_cmb_block(struct age_softc * sc)3047 age_init_cmb_block(struct age_softc *sc)
3048 {
3049 struct age_ring_data *rd;
3050
3051 AGE_LOCK_ASSERT(sc);
3052
3053 rd = &sc->age_rdata;
3054 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3055 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3056 sc->age_cdata.age_cmb_block_map,
3057 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3058 }
3059
3060 static void
age_init_smb_block(struct age_softc * sc)3061 age_init_smb_block(struct age_softc *sc)
3062 {
3063 struct age_ring_data *rd;
3064
3065 AGE_LOCK_ASSERT(sc);
3066
3067 rd = &sc->age_rdata;
3068 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3069 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3070 sc->age_cdata.age_smb_block_map,
3071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3072 }
3073
3074 static int
age_newbuf(struct age_softc * sc,struct age_rxdesc * rxd)3075 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3076 {
3077 struct rx_desc *desc;
3078 struct mbuf *m;
3079 bus_dma_segment_t segs[1];
3080 bus_dmamap_t map;
3081 int nsegs;
3082
3083 AGE_LOCK_ASSERT(sc);
3084
3085 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3086 if (m == NULL)
3087 return (ENOBUFS);
3088 m->m_len = m->m_pkthdr.len = MCLBYTES;
3089 #ifndef __NO_STRICT_ALIGNMENT
3090 m_adj(m, AGE_RX_BUF_ALIGN);
3091 #endif
3092
3093 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3094 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3095 m_freem(m);
3096 return (ENOBUFS);
3097 }
3098 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3099
3100 if (rxd->rx_m != NULL) {
3101 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3102 BUS_DMASYNC_POSTREAD);
3103 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3104 }
3105 map = rxd->rx_dmamap;
3106 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3107 sc->age_cdata.age_rx_sparemap = map;
3108 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3109 BUS_DMASYNC_PREREAD);
3110 rxd->rx_m = m;
3111
3112 desc = rxd->rx_desc;
3113 desc->addr = htole64(segs[0].ds_addr);
3114 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3115 AGE_RD_LEN_SHIFT);
3116 return (0);
3117 }
3118
3119 static void
age_rxvlan(struct age_softc * sc)3120 age_rxvlan(struct age_softc *sc)
3121 {
3122 if_t ifp;
3123 uint32_t reg;
3124
3125 AGE_LOCK_ASSERT(sc);
3126
3127 ifp = sc->age_ifp;
3128 reg = CSR_READ_4(sc, AGE_MAC_CFG);
3129 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3130 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3131 reg |= MAC_CFG_VLAN_TAG_STRIP;
3132 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3133 }
3134
3135 static u_int
age_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)3136 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3137 {
3138 uint32_t *mchash = arg;
3139 uint32_t crc;
3140
3141 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3142 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3143
3144 return (1);
3145 }
3146
3147 static void
age_rxfilter(struct age_softc * sc)3148 age_rxfilter(struct age_softc *sc)
3149 {
3150 if_t ifp;
3151 uint32_t mchash[2];
3152 uint32_t rxcfg;
3153
3154 AGE_LOCK_ASSERT(sc);
3155
3156 ifp = sc->age_ifp;
3157
3158 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3159 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3160 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3161 rxcfg |= MAC_CFG_BCAST;
3162 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3163 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3164 rxcfg |= MAC_CFG_PROMISC;
3165 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3166 rxcfg |= MAC_CFG_ALLMULTI;
3167 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3168 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3169 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3170 return;
3171 }
3172
3173 /* Program new filter. */
3174 bzero(mchash, sizeof(mchash));
3175 if_foreach_llmaddr(ifp, age_hash_maddr, mchash);
3176
3177 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3178 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3179 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3180 }
3181
3182 static int
sysctl_age_stats(SYSCTL_HANDLER_ARGS)3183 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3184 {
3185 struct age_softc *sc;
3186 struct age_stats *stats;
3187 int error, result;
3188
3189 result = -1;
3190 error = sysctl_handle_int(oidp, &result, 0, req);
3191
3192 if (error != 0 || req->newptr == NULL)
3193 return (error);
3194
3195 if (result != 1)
3196 return (error);
3197
3198 sc = (struct age_softc *)arg1;
3199 stats = &sc->age_stat;
3200 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3201 printf("Transmit good frames : %ju\n",
3202 (uintmax_t)stats->tx_frames);
3203 printf("Transmit good broadcast frames : %ju\n",
3204 (uintmax_t)stats->tx_bcast_frames);
3205 printf("Transmit good multicast frames : %ju\n",
3206 (uintmax_t)stats->tx_mcast_frames);
3207 printf("Transmit pause control frames : %u\n",
3208 stats->tx_pause_frames);
3209 printf("Transmit control frames : %u\n",
3210 stats->tx_control_frames);
3211 printf("Transmit frames with excessive deferrals : %u\n",
3212 stats->tx_excess_defer);
3213 printf("Transmit deferrals : %u\n",
3214 stats->tx_deferred);
3215 printf("Transmit good octets : %ju\n",
3216 (uintmax_t)stats->tx_bytes);
3217 printf("Transmit good broadcast octets : %ju\n",
3218 (uintmax_t)stats->tx_bcast_bytes);
3219 printf("Transmit good multicast octets : %ju\n",
3220 (uintmax_t)stats->tx_mcast_bytes);
3221 printf("Transmit frames 64 bytes : %ju\n",
3222 (uintmax_t)stats->tx_pkts_64);
3223 printf("Transmit frames 65 to 127 bytes : %ju\n",
3224 (uintmax_t)stats->tx_pkts_65_127);
3225 printf("Transmit frames 128 to 255 bytes : %ju\n",
3226 (uintmax_t)stats->tx_pkts_128_255);
3227 printf("Transmit frames 256 to 511 bytes : %ju\n",
3228 (uintmax_t)stats->tx_pkts_256_511);
3229 printf("Transmit frames 512 to 1024 bytes : %ju\n",
3230 (uintmax_t)stats->tx_pkts_512_1023);
3231 printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3232 (uintmax_t)stats->tx_pkts_1024_1518);
3233 printf("Transmit frames 1519 to MTU bytes : %ju\n",
3234 (uintmax_t)stats->tx_pkts_1519_max);
3235 printf("Transmit single collisions : %u\n",
3236 stats->tx_single_colls);
3237 printf("Transmit multiple collisions : %u\n",
3238 stats->tx_multi_colls);
3239 printf("Transmit late collisions : %u\n",
3240 stats->tx_late_colls);
3241 printf("Transmit abort due to excessive collisions : %u\n",
3242 stats->tx_excess_colls);
3243 printf("Transmit underruns due to FIFO underruns : %u\n",
3244 stats->tx_underrun);
3245 printf("Transmit descriptor write-back errors : %u\n",
3246 stats->tx_desc_underrun);
3247 printf("Transmit frames with length mismatched frame size : %u\n",
3248 stats->tx_lenerrs);
3249 printf("Transmit frames with truncated due to MTU size : %u\n",
3250 stats->tx_lenerrs);
3251
3252 printf("Receive good frames : %ju\n",
3253 (uintmax_t)stats->rx_frames);
3254 printf("Receive good broadcast frames : %ju\n",
3255 (uintmax_t)stats->rx_bcast_frames);
3256 printf("Receive good multicast frames : %ju\n",
3257 (uintmax_t)stats->rx_mcast_frames);
3258 printf("Receive pause control frames : %u\n",
3259 stats->rx_pause_frames);
3260 printf("Receive control frames : %u\n",
3261 stats->rx_control_frames);
3262 printf("Receive CRC errors : %u\n",
3263 stats->rx_crcerrs);
3264 printf("Receive frames with length errors : %u\n",
3265 stats->rx_lenerrs);
3266 printf("Receive good octets : %ju\n",
3267 (uintmax_t)stats->rx_bytes);
3268 printf("Receive good broadcast octets : %ju\n",
3269 (uintmax_t)stats->rx_bcast_bytes);
3270 printf("Receive good multicast octets : %ju\n",
3271 (uintmax_t)stats->rx_mcast_bytes);
3272 printf("Receive frames too short : %u\n",
3273 stats->rx_runts);
3274 printf("Receive fragmented frames : %ju\n",
3275 (uintmax_t)stats->rx_fragments);
3276 printf("Receive frames 64 bytes : %ju\n",
3277 (uintmax_t)stats->rx_pkts_64);
3278 printf("Receive frames 65 to 127 bytes : %ju\n",
3279 (uintmax_t)stats->rx_pkts_65_127);
3280 printf("Receive frames 128 to 255 bytes : %ju\n",
3281 (uintmax_t)stats->rx_pkts_128_255);
3282 printf("Receive frames 256 to 511 bytes : %ju\n",
3283 (uintmax_t)stats->rx_pkts_256_511);
3284 printf("Receive frames 512 to 1024 bytes : %ju\n",
3285 (uintmax_t)stats->rx_pkts_512_1023);
3286 printf("Receive frames 1024 to 1518 bytes : %ju\n",
3287 (uintmax_t)stats->rx_pkts_1024_1518);
3288 printf("Receive frames 1519 to MTU bytes : %ju\n",
3289 (uintmax_t)stats->rx_pkts_1519_max);
3290 printf("Receive frames too long : %ju\n",
3291 (uint64_t)stats->rx_pkts_truncated);
3292 printf("Receive frames with FIFO overflow : %u\n",
3293 stats->rx_fifo_oflows);
3294 printf("Receive frames with return descriptor overflow : %u\n",
3295 stats->rx_desc_oflows);
3296 printf("Receive frames with alignment errors : %u\n",
3297 stats->rx_alignerrs);
3298 printf("Receive frames dropped due to address filtering : %ju\n",
3299 (uint64_t)stats->rx_pkts_filtered);
3300
3301 return (error);
3302 }
3303
3304 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3305 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3306 {
3307 int error, value;
3308
3309 if (arg1 == NULL)
3310 return (EINVAL);
3311 value = *(int *)arg1;
3312 error = sysctl_handle_int(oidp, &value, 0, req);
3313 if (error || req->newptr == NULL)
3314 return (error);
3315 if (value < low || value > high)
3316 return (EINVAL);
3317 *(int *)arg1 = value;
3318
3319 return (0);
3320 }
3321
3322 static int
sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)3323 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3324 {
3325 return (sysctl_int_range(oidp, arg1, arg2, req,
3326 AGE_PROC_MIN, AGE_PROC_MAX));
3327 }
3328
3329 static int
sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)3330 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3331 {
3332
3333 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3334 AGE_IM_TIMER_MAX));
3335 }
3336