1 /*-
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $
43 */
44
45 #ifndef _AIC79XX_H_
46 #define _AIC79XX_H_
47
48 /* Register Definitions */
49 #include "aic79xx_reg.h"
50
51 /************************* Forward Declarations *******************************/
52 struct ahd_platform_data;
53 struct scb_platform_data;
54
55 /****************************** Useful Macros *********************************/
56 #ifndef MAX
57 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
58 #endif
59
60 #ifndef MIN
61 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
62 #endif
63
64 #ifndef TRUE
65 #define TRUE 1
66 #endif
67 #ifndef FALSE
68 #define FALSE 0
69 #endif
70
71 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
72
73 #define ALL_CHANNELS '\0'
74 #define ALL_TARGETS_MASK 0xFFFF
75 #define INITIATOR_WILDCARD (~0)
76 #define SCB_LIST_NULL 0xFF00
77 #define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL))
78 #define QOUTFIFO_ENTRY_VALID 0x80
79 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
80
81 #define SCSIID_TARGET(ahd, scsiid) \
82 (((scsiid) & TID) >> TID_SHIFT)
83 #define SCSIID_OUR_ID(scsiid) \
84 ((scsiid) & OID)
85 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
86 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
87 #define SCB_GET_OUR_ID(scb) \
88 SCSIID_OUR_ID((scb)->hscb->scsiid)
89 #define SCB_GET_TARGET(ahd, scb) \
90 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
91 #define SCB_GET_CHANNEL(ahd, scb) \
92 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
93 #define SCB_GET_LUN(scb) \
94 ((scb)->hscb->lun)
95 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
96 SCB_GET_TARGET(ahd, scb)
97 #define SCB_GET_TARGET_MASK(ahd, scb) \
98 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
99 #ifdef AHD_DEBUG
100 #define SCB_IS_SILENT(scb) \
101 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
102 && (((scb)->flags & SCB_SILENT) != 0))
103 #else
104 #define SCB_IS_SILENT(scb) \
105 (((scb)->flags & SCB_SILENT) != 0)
106 #endif
107 /*
108 * TCLs have the following format: TTTTLLLLLLLL
109 */
110 #define TCL_TARGET_OFFSET(tcl) \
111 ((((tcl) >> 4) & TID) >> 4)
112 #define TCL_LUN(tcl) \
113 (tcl & (AHD_NUM_LUNS - 1))
114 #define BUILD_TCL(scsiid, lun) \
115 ((lun) | (((scsiid) & TID) << 4))
116 #define BUILD_TCL_RAW(target, channel, lun) \
117 ((lun) | ((target) << 8))
118
119 #define SCB_GET_TAG(scb) \
120 aic_le16toh(scb->hscb->tag)
121
122 #ifndef AHD_TARGET_MODE
123 #undef AHD_TMODE_ENABLE
124 #define AHD_TMODE_ENABLE 0
125 #endif
126
127 #define AHD_BUILD_COL_IDX(target, lun) \
128 (((lun) << 4) | target)
129
130 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
131 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
132
133 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
134 do { \
135 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
136 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
137 } while (0)
138
139 #define AHD_COPY_SCB_COL_IDX(dst, src) \
140 do { \
141 dst->hscb->scsiid = src->hscb->scsiid; \
142 dst->hscb->lun = src->hscb->lun; \
143 } while (0)
144
145 #define AHD_NEVER_COL_IDX 0xFFFF
146
147 /**************************** Driver Constants ********************************/
148 /*
149 * The maximum number of supported targets.
150 */
151 #define AHD_NUM_TARGETS 16
152
153 /*
154 * The maximum number of supported luns.
155 * The identify message only supports 64 luns in non-packetized transfers.
156 * You can have 2^64 luns when information unit transfers are enabled,
157 * but until we see a need to support that many, we support 256.
158 */
159 #define AHD_NUM_LUNS_NONPKT 64
160 #define AHD_NUM_LUNS 256
161
162 /*
163 * The maximum transfer per S/G segment.
164 */
165 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
166
167 /*
168 * The maximum amount of SCB storage in hardware on a controller.
169 * This value represents an upper bound. Due to software design,
170 * we may not be able to use this number.
171 */
172 #define AHD_SCB_MAX 512
173
174 /*
175 * The maximum number of concurrent transactions supported per driver instance.
176 * Sequencer Control Blocks (SCBs) store per-transaction information.
177 */
178 #define AHD_MAX_QUEUE AHD_SCB_MAX
179
180 /*
181 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
182 * in size and accommodate as many transactions as can be queued concurrently.
183 */
184 #define AHD_QIN_SIZE AHD_MAX_QUEUE
185 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
186
187 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
188 /*
189 * The maximum amount of SCB storage we allocate in host memory.
190 */
191 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
192
193 /*
194 * Ring Buffer of incoming target commands.
195 * We allocate 256 to simplify the logic in the sequencer
196 * by using the natural wrap point of an 8bit counter.
197 */
198 #define AHD_TMODE_CMDS 256
199
200 /* Reset line assertion time in us */
201 #define AHD_BUSRESET_DELAY 25
202
203 /******************* Chip Characteristics/Operating Settings *****************/
204 extern uint32_t ahd_attach_to_HostRAID_controllers;
205
206 /*
207 * Chip Type
208 * The chip order is from least sophisticated to most sophisticated.
209 */
210 typedef enum {
211 AHD_NONE = 0x0000,
212 AHD_CHIPID_MASK = 0x00FF,
213 AHD_AIC7901 = 0x0001,
214 AHD_AIC7902 = 0x0002,
215 AHD_AIC7901A = 0x0003,
216 AHD_PCI = 0x0100, /* Bus type PCI */
217 AHD_PCIX = 0x0200, /* Bus type PCIX */
218 AHD_BUS_MASK = 0x0F00
219 } ahd_chip;
220
221 /*
222 * Features available in each chip type.
223 */
224 typedef enum {
225 AHD_FENONE = 0x00000,
226 AHD_WIDE = 0x00001,/* Wide Channel */
227 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
228 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
229 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
230 AHD_RTI = 0x04000,/* Retained Training Support */
231 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
232 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
233 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
234 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
235 AHD_AIC7901_FE = AHD_FENONE,
236 AHD_AIC7901A_FE = AHD_FENONE,
237 AHD_AIC7902_FE = AHD_MULTI_FUNC
238 } ahd_feature;
239
240 /*
241 * Bugs in the silicon that we work around in software.
242 */
243 typedef enum {
244 AHD_BUGNONE = 0x0000,
245 /*
246 * Rev A hardware fails to update LAST/CURR/NEXTSCB
247 * correctly in certain packetized selection cases.
248 */
249 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
250 /* The wrong SCB is accessed to check the abort pending bit. */
251 AHD_ABORT_LQI_BUG = 0x0002,
252 /* Packetized bitbucket crosses packet boundaries. */
253 AHD_PKT_BITBUCKET_BUG = 0x0004,
254 /* The selection timer runs twice as long as its setting. */
255 AHD_LONG_SETIMO_BUG = 0x0008,
256 /* The Non-LQ CRC error status is delayed until phase change. */
257 AHD_NLQICRC_DELAYED_BUG = 0x0010,
258 /* The chip must be reset for all outgoing bus resets. */
259 AHD_SCSIRST_BUG = 0x0020,
260 /* Some PCIX fields must be saved and restored across chip reset. */
261 AHD_PCIX_CHIPRST_BUG = 0x0040,
262 /* MMAPIO is not functional in PCI-X mode. */
263 AHD_PCIX_MMAPIO_BUG = 0x0080,
264 /* Reads to SCBRAM fail to reset the discard timer. */
265 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
266 /* Bug workarounds that can be disabled on non-PCIX busses. */
267 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
268 | AHD_PCIX_MMAPIO_BUG
269 | AHD_PCIX_SCBRAM_RD_BUG,
270 /*
271 * LQOSTOP0 status set even for forced selections with ATN
272 * to perform non-packetized message delivery.
273 */
274 AHD_LQO_ATNO_BUG = 0x0200,
275 /* FIFO auto-flush does not always trigger. */
276 AHD_AUTOFLUSH_BUG = 0x0400,
277 /* The CLRLQO registers are not self-clearing. */
278 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
279 /* The PACKETIZED status bit refers to the previous connection. */
280 AHD_PKTIZED_STATUS_BUG = 0x1000,
281 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
282 AHD_PKT_LUN_BUG = 0x2000,
283 /*
284 * Only the FIFO allocated to the non-packetized connection may
285 * be in use during a non-packetzied connection.
286 */
287 AHD_NONPACKFIFO_BUG = 0x4000,
288 /*
289 * Writing to a DFF SCBPTR register may fail if concurrent with
290 * a hardware write to the other DFF SCBPTR register. This is
291 * not currently a concern in our sequencer since all chips with
292 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
293 * occur in non-packetized connections.
294 */
295 AHD_MDFF_WSCBPTR_BUG = 0x8000,
296 /* SGHADDR updates are slow. */
297 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
298 /*
299 * Changing the MODE_PTR coincident with an interrupt that
300 * switches to a different mode will cause the interrupt to
301 * be in the mode written outside of interrupt context.
302 */
303 AHD_SET_MODE_BUG = 0x20000,
304 /* Non-packetized busfree revision does not work. */
305 AHD_BUSFREEREV_BUG = 0x40000,
306 /*
307 * Paced transfers are indicated with a non-standard PPR
308 * option bit in the neg table, 160MHz is indicated by
309 * sync factor 0x7, and the offset if off by a factor of 2.
310 */
311 AHD_PACED_NEGTABLE_BUG = 0x80000,
312 /* LQOOVERRUN false positives. */
313 AHD_LQOOVERRUN_BUG = 0x100000,
314 /*
315 * Controller write to INTSTAT will lose to a host
316 * write to CLRINT.
317 */
318 AHD_INTCOLLISION_BUG = 0x200000,
319 /*
320 * The GEM318 violates the SCSI spec by not waiting
321 * the mandated bus settle delay between phase changes
322 * in some situations. Some aic79xx chip revs. are more
323 * strict in this regard and will treat REQ assertions
324 * that fall within the bus settle delay window as
325 * glitches. This flag tells the firmware to tolerate
326 * early REQ assertions.
327 */
328 AHD_EARLY_REQ_BUG = 0x400000,
329 /*
330 * The LED does not stay on long enough in packetized modes.
331 */
332 AHD_FAINT_LED_BUG = 0x800000
333 } ahd_bug;
334
335 /*
336 * Configuration specific settings.
337 * The driver determines these settings by probing the
338 * chip/controller's configuration.
339 */
340 typedef enum {
341 AHD_FNONE = 0x00000,
342 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
343 AHD_USEDEFAULTS = 0x00004,/*
344 * For cards without an seeprom
345 * or a BIOS to initialize the chip's
346 * SRAM, we use the default target
347 * settings.
348 */
349 AHD_SEQUENCER_DEBUG = 0x00008,
350 AHD_RESET_BUS_A = 0x00010,
351 AHD_EXTENDED_TRANS_A = 0x00020,
352 AHD_TERM_ENB_A = 0x00040,
353 AHD_SPCHK_ENB_A = 0x00080,
354 AHD_STPWLEVEL_A = 0x00100,
355 AHD_INITIATORROLE = 0x00200,/*
356 * Allow initiator operations on
357 * this controller.
358 */
359 AHD_TARGETROLE = 0x00400,/*
360 * Allow target operations on this
361 * controller.
362 */
363 AHD_RESOURCE_SHORTAGE = 0x00800,
364 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
365 AHD_INT50_SPEEDFLEX = 0x02000,/*
366 * Internal 50pin connector
367 * sits behind an aic3860
368 */
369 AHD_BIOS_ENABLED = 0x04000,
370 AHD_ALL_INTERRUPTS = 0x08000,
371 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
372 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
373 AHD_CURRENT_SENSING = 0x40000,
374 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
375 AHD_HP_BOARD = 0x100000,
376 AHD_RESET_POLL_ACTIVE = 0x200000,
377 AHD_UPDATE_PEND_CMDS = 0x400000,
378 AHD_RUNNING_QOUTFIFO = 0x800000,
379 AHD_HAD_FIRST_SEL = 0x1000000,
380 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */
381 AHD_HOSTRAID_BOARD = 0x4000000
382 } ahd_flag;
383
384 /************************* Hardware SCB Definition ***************************/
385
386 /*
387 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
388 * consists of a "hardware SCB" mirroring the fields available on the card
389 * and additional information the kernel stores for each transaction.
390 *
391 * To minimize space utilization, a portion of the hardware scb stores
392 * different data during different portions of a SCSI transaction.
393 * As initialized by the host driver for the initiator role, this area
394 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
395 * the cdb has been presented to the target, this area serves to store
396 * residual transfer information and the SCSI status byte.
397 * For the target role, the contents of this area do not change, but
398 * still serve a different purpose than for the initiator role. See
399 * struct target_data for details.
400 */
401
402 /*
403 * Status information embedded in the shared poriton of
404 * an SCB after passing the cdb to the target. The kernel
405 * driver will only read this data for transactions that
406 * complete abnormally.
407 */
408 struct initiator_status {
409 uint32_t residual_datacnt; /* Residual in the current S/G seg */
410 uint32_t residual_sgptr; /* The next S/G for this transfer */
411 uint8_t scsi_status; /* Standard SCSI status byte */
412 };
413
414 struct target_status {
415 uint32_t residual_datacnt; /* Residual in the current S/G seg */
416 uint32_t residual_sgptr; /* The next S/G for this transfer */
417 uint8_t scsi_status; /* SCSI status to give to initiator */
418 uint8_t target_phases; /* Bitmap of phases to execute */
419 uint8_t data_phase; /* Data-In or Data-Out */
420 uint8_t initiator_tag; /* Initiator's transaction tag */
421 };
422
423 /*
424 * Initiator mode SCB shared data area.
425 * If the embedded CDB is 12 bytes or less, we embed
426 * the sense buffer address in the SCB. This allows
427 * us to retrieve sense information without interrupting
428 * the host in packetized mode.
429 */
430 typedef uint32_t sense_addr_t;
431 #define MAX_CDB_LEN 16
432 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
433 union initiator_data {
434 struct {
435 uint64_t cdbptr;
436 uint8_t cdblen;
437 } cdb_from_host;
438 uint8_t cdb[MAX_CDB_LEN];
439 struct {
440 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
441 sense_addr_t sense_addr;
442 } cdb_plus_saddr;
443 };
444
445 /*
446 * Target mode version of the shared data SCB segment.
447 */
448 struct target_data {
449 uint32_t spare[2];
450 uint8_t scsi_status; /* SCSI status to give to initiator */
451 uint8_t target_phases; /* Bitmap of phases to execute */
452 uint8_t data_phase; /* Data-In or Data-Out */
453 uint8_t initiator_tag; /* Initiator's transaction tag */
454 };
455
456 struct hardware_scb {
457 /*0*/ union {
458 union initiator_data idata;
459 struct target_data tdata;
460 struct initiator_status istatus;
461 struct target_status tstatus;
462 } shared_data;
463 /*
464 * A word about residuals.
465 * The scb is presented to the sequencer with the dataptr and datacnt
466 * fields initialized to the contents of the first S/G element to
467 * transfer. The sgptr field is initialized to the bus address for
468 * the S/G element that follows the first in the in core S/G array
469 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
470 * S/G entry for this transfer (single S/G element transfer with the
471 * first elements address and length preloaded in the dataptr/datacnt
472 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
473 * The SG_FULL_RESID flag ensures that the residual will be correctly
474 * noted even if no data transfers occur. Once the data phase is entered,
475 * the residual sgptr and datacnt are loaded from the sgptr and the
476 * datacnt fields. After each S/G element's dataptr and length are
477 * loaded into the hardware, the residual sgptr is advanced. After
478 * each S/G element is expired, its datacnt field is checked to see
479 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
480 * residual sg ptr and the transfer is considered complete. If the
481 * sequencer determines that there is a residual in the transfer, or
482 * there is non-zero status, it will set the SG_STATUS_VALID flag in
483 * sgptr and dma the scb back into host memory. To sumarize:
484 *
485 * Sequencer:
486 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
487 * or residual_sgptr does not have SG_LIST_NULL set.
488 *
489 * o We are transferring the last segment if residual_datacnt has
490 * the SG_LAST_SEG flag set.
491 *
492 * Host:
493 * o A residual can only have occurred if a completed scb has the
494 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
495 * the residual_datacnt, and the residual_sgptr field will tell
496 * for sure.
497 *
498 * o residual_sgptr and sgptr refer to the "next" sg entry
499 * and so may point beyond the last valid sg entry for the
500 * transfer.
501 */
502 #define SG_PTR_MASK 0xFFFFFFF8
503 /*16*/ uint16_t tag; /* Reused by Sequencer. */
504 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
505 /*19*/ uint8_t scsiid; /*
506 * Selection out Id
507 * Our Id (bits 0-3) Their ID (bits 4-7)
508 */
509 /*20*/ uint8_t lun;
510 /*21*/ uint8_t task_attribute;
511 /*22*/ uint8_t cdb_len;
512 /*23*/ uint8_t task_management;
513 /*24*/ uint64_t dataptr;
514 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
515 /*36*/ uint32_t sgptr;
516 /*40*/ uint32_t hscb_busaddr;
517 /*44*/ uint32_t next_hscb_busaddr;
518 /********** Long lun field only downloaded for full 8 byte lun support ********/
519 /*48*/ uint8_t pkt_long_lun[8];
520 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
521 /*56*/ uint8_t spare[8];
522 };
523
524 /************************ Kernel SCB Definitions ******************************/
525 /*
526 * Some fields of the SCB are OS dependent. Here we collect the
527 * definitions for elements that all OS platforms need to include
528 * in there SCB definition.
529 */
530
531 /*
532 * Definition of a scatter/gather element as transferred to the controller.
533 * The aic7xxx chips only support a 24bit length. We use the top byte of
534 * the length to store additional address bits and a flag to indicate
535 * that a given segment terminates the transfer. This gives us an
536 * addressable range of 512GB on machines with 64bit PCI or with chips
537 * that can support dual address cycles on 32bit PCI busses.
538 */
539 struct ahd_dma_seg {
540 uint32_t addr;
541 uint32_t len;
542 #define AHD_DMA_LAST_SEG 0x80000000
543 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
544 #define AHD_SG_LEN_MASK 0x00FFFFFF
545 };
546
547 struct ahd_dma64_seg {
548 uint64_t addr;
549 uint32_t len;
550 uint32_t pad;
551 };
552
553 struct map_node {
554 bus_dmamap_t dmamap;
555 bus_addr_t busaddr;
556 uint8_t *vaddr;
557 SLIST_ENTRY(map_node) links;
558 };
559
560 /*
561 * The current state of this SCB.
562 */
563 typedef enum {
564 SCB_FLAG_NONE = 0x00000,
565 SCB_TRANSMISSION_ERROR = 0x00001,/*
566 * We detected a parity or CRC
567 * error that has effected the
568 * payload of the command. This
569 * flag is checked when normal
570 * status is returned to catch
571 * the case of a target not
572 * responding to our attempt
573 * to report the error.
574 */
575 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
576 * Another device was active
577 * during the first timeout for
578 * this SCB so we gave ourselves
579 * an additional timeout period
580 * in case it was hogging the
581 * bus.
582 */
583 SCB_DEVICE_RESET = 0x00004,
584 SCB_SENSE = 0x00008,
585 SCB_CDB32_PTR = 0x00010,
586 SCB_RECOVERY_SCB = 0x00020,
587 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
588 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
589 SCB_ABORT = 0x00100,
590 SCB_ACTIVE = 0x00200,
591 SCB_TARGET_IMMEDIATE = 0x00400,
592 SCB_PACKETIZED = 0x00800,
593 SCB_EXPECT_PPR_BUSFREE = 0x01000,
594 SCB_PKT_SENSE = 0x02000,
595 SCB_CMDPHASE_ABORT = 0x04000,
596 SCB_ON_COL_LIST = 0x08000,
597 SCB_SILENT = 0x10000,/*
598 * Be quiet about transmission type
599 * errors. They are expected and we
600 * don't want to upset the user. This
601 * flag is typically used during DV.
602 */
603 SCB_TIMEDOUT = 0x20000/*
604 * SCB has timed out and is on the
605 * timedout list.
606 */
607 } scb_flag;
608
609 struct scb {
610 struct hardware_scb *hscb;
611 union {
612 SLIST_ENTRY(scb) sle;
613 LIST_ENTRY(scb) le;
614 TAILQ_ENTRY(scb) tqe;
615 } links;
616 union {
617 SLIST_ENTRY(scb) sle;
618 LIST_ENTRY(scb) le;
619 TAILQ_ENTRY(scb) tqe;
620 } links2;
621 #define pending_links links2.le
622 #define collision_links links2.le
623 LIST_ENTRY(scb) timedout_links;
624 struct scb *col_scb;
625 aic_io_ctx_t io_ctx;
626 struct ahd_softc *ahd_softc;
627 scb_flag flags;
628 bus_dmamap_t dmamap;
629 struct scb_platform_data *platform_data;
630 struct map_node *hscb_map;
631 struct map_node *sg_map;
632 struct map_node *sense_map;
633 void *sg_list;
634 uint8_t *sense_data;
635 bus_addr_t sg_list_busaddr;
636 bus_addr_t sense_busaddr;
637 u_int sg_count;/* How full ahd_dma_seg is */
638 #define AHD_MAX_LQ_CRC_ERRORS 5
639 u_int crc_retry_count;
640 aic_timer_t io_timer;
641 };
642
643 TAILQ_HEAD(scb_tailq, scb);
644 LIST_HEAD(scb_list, scb);
645
646 struct scb_data {
647 /*
648 * TAILQ of lists of free SCBs grouped by device
649 * collision domains.
650 */
651 struct scb_tailq free_scbs;
652
653 /*
654 * Per-device lists of SCBs whose tag ID would collide
655 * with an already active tag on the device.
656 */
657 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
658
659 /*
660 * SCBs that will not collide with any active device.
661 */
662 struct scb_list any_dev_free_scb_list;
663
664 /*
665 * Mapping from tag to SCB.
666 */
667 struct scb *scbindex[AHD_SCB_MAX];
668
669 u_int recovery_scbs; /* Transactions currently in recovery */
670
671 /*
672 * "Bus" addresses of our data structures.
673 */
674 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
675 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
676 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
677
678 SLIST_HEAD(, map_node) hscb_maps;
679 SLIST_HEAD(, map_node) sg_maps;
680 SLIST_HEAD(, map_node) sense_maps;
681 int scbs_left; /* unallocated scbs in head map_node */
682 int sgs_left; /* unallocated sgs in head map_node */
683 int sense_left; /* unallocated sense in head map_node */
684 uint16_t numscbs;
685 uint16_t maxhscbs; /* Number of SCBs on the card */
686 uint8_t init_level; /*
687 * How far we've initialized
688 * this structure.
689 */
690 };
691
692 /************************ Target Mode Definitions *****************************/
693
694 /*
695 * Connection descriptor for select-in requests in target mode.
696 */
697 struct target_cmd {
698 uint8_t scsiid; /* Our ID and the initiator's ID */
699 uint8_t identify; /* Identify message */
700 uint8_t bytes[22]; /*
701 * Bytes contains any additional message
702 * bytes terminated by 0xFF. The remainder
703 * is the cdb to execute.
704 */
705 uint8_t cmd_valid; /*
706 * When a command is complete, the firmware
707 * will set cmd_valid to all bits set.
708 * After the host has seen the command,
709 * the bits are cleared. This allows us
710 * to just peek at host memory to determine
711 * if more work is complete. cmd_valid is on
712 * an 8 byte boundary to simplify setting
713 * it on aic7880 hardware which only has
714 * limited direct access to the DMA FIFO.
715 */
716 uint8_t pad[7];
717 };
718
719 /*
720 * Number of events we can buffer up if we run out
721 * of immediate notify ccbs.
722 */
723 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
724 struct ahd_tmode_event {
725 uint8_t initiator_id;
726 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
727 #define EVENT_TYPE_BUS_RESET 0xFF
728 uint8_t event_arg;
729 };
730
731 /*
732 * Per enabled lun target mode state.
733 * As this state is directly influenced by the host OS'es target mode
734 * environment, we let the OS module define it. Forward declare the
735 * structure here so we can store arrays of them, etc. in OS neutral
736 * data structures.
737 */
738 #ifdef AHD_TARGET_MODE
739 struct ahd_tmode_lstate {
740 struct cam_path *path;
741 struct ccb_hdr_slist accept_tios;
742 struct ccb_hdr_slist immed_notifies;
743 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
744 uint8_t event_r_idx;
745 uint8_t event_w_idx;
746 };
747 #else
748 struct ahd_tmode_lstate;
749 #endif
750
751 /******************** Transfer Negotiation Datastructures *********************/
752 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
753 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
754 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
755 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
756 #define AHD_PERIOD_10MHz 0x19
757
758 #define AHD_WIDTH_UNKNOWN 0xFF
759 #define AHD_PERIOD_UNKNOWN 0xFF
760 #define AHD_OFFSET_UNKNOWN 0xFF
761 #define AHD_PPR_OPTS_UNKNOWN 0xFF
762
763 /*
764 * Transfer Negotiation Information.
765 */
766 struct ahd_transinfo {
767 uint8_t protocol_version; /* SCSI Revision level */
768 uint8_t transport_version; /* SPI Revision level */
769 uint8_t width; /* Bus width */
770 uint8_t period; /* Sync rate factor */
771 uint8_t offset; /* Sync offset */
772 uint8_t ppr_options; /* Parallel Protocol Request options */
773 };
774
775 /*
776 * Per-initiator current, goal and user transfer negotiation information. */
777 struct ahd_initiator_tinfo {
778 struct ahd_transinfo curr;
779 struct ahd_transinfo goal;
780 struct ahd_transinfo user;
781 };
782
783 /*
784 * Per enabled target ID state.
785 * Pointers to lun target state as well as sync/wide negotiation information
786 * for each initiator<->target mapping. For the initiator role we pretend
787 * that we are the target and the targets are the initiators since the
788 * negotiation is the same regardless of role.
789 */
790 struct ahd_tmode_tstate {
791 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
792 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
793
794 /*
795 * Per initiator state bitmasks.
796 */
797 uint16_t auto_negotiate;/* Auto Negotiation Required */
798 uint16_t discenable; /* Disconnection allowed */
799 uint16_t tagenable; /* Tagged Queuing allowed */
800 };
801
802 /*
803 * Points of interest along the negotiated transfer scale.
804 */
805 #define AHD_SYNCRATE_160 0x8
806 #define AHD_SYNCRATE_PACED 0x8
807 #define AHD_SYNCRATE_DT 0x9
808 #define AHD_SYNCRATE_ULTRA2 0xa
809 #define AHD_SYNCRATE_ULTRA 0xc
810 #define AHD_SYNCRATE_FAST 0x19
811 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
812 #define AHD_SYNCRATE_SYNC 0x32
813 #define AHD_SYNCRATE_MIN 0x60
814 #define AHD_SYNCRATE_ASYNC 0xFF
815 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
816
817 /* Safe and valid period for async negotiations. */
818 #define AHD_ASYNC_XFER_PERIOD 0x44
819
820 /*
821 * In RevA, the synctable uses a 120MHz rate for the period
822 * factor 8 and 160MHz for the period factor 7. The 120MHz
823 * rate never made it into the official SCSI spec, so we must
824 * compensate when setting the negotiation table for Rev A
825 * parts.
826 */
827 #define AHD_SYNCRATE_REVA_120 0x8
828 #define AHD_SYNCRATE_REVA_160 0x7
829
830 /***************************** Lookup Tables **********************************/
831 /*
832 * Phase -> name and message out response
833 * to parity errors in each phase table.
834 */
835 struct ahd_phase_table_entry {
836 uint8_t phase;
837 uint8_t mesg_out; /* Message response to parity errors */
838 char *phasemsg;
839 };
840
841 /************************** Serial EEPROM Format ******************************/
842
843 struct seeprom_config {
844 /*
845 * Per SCSI ID Configuration Flags
846 */
847 uint16_t device_flags[16]; /* words 0-15 */
848 #define CFXFER 0x003F /* synchronous transfer rate */
849 #define CFXFER_ASYNC 0x3F
850 #define CFQAS 0x0040 /* Negotiate QAS */
851 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
852 #define CFSTART 0x0100 /* send start unit SCSI command */
853 #define CFINCBIOS 0x0200 /* include in BIOS scan */
854 #define CFDISC 0x0400 /* enable disconnection */
855 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
856 #define CFWIDEB 0x1000 /* wide bus device */
857 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
858
859 /*
860 * BIOS Control Bits
861 */
862 uint16_t bios_control; /* word 16 */
863 #define CFSUPREM 0x0001 /* support all removeable drives */
864 #define CFSUPREMB 0x0002 /* support removeable boot drives */
865 #define CFBIOSSTATE 0x000C /* BIOS Action State */
866 #define CFBS_DISABLED 0x00
867 #define CFBS_ENABLED 0x04
868 #define CFBS_DISABLED_SCAN 0x08
869 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
870 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
871 #define CFSPARITY 0x0040 /* SCSI parity */
872 #define CFEXTEND 0x0080 /* extended translation enabled */
873 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
874 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
875 #define CFMSG_VERBOSE 0x0000
876 #define CFMSG_SILENT 0x0200
877 #define CFMSG_DIAG 0x0400
878 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
879 /* UNUSED 0xf000 */
880
881 /*
882 * Host Adapter Control Bits
883 */
884 uint16_t adapter_control; /* word 17 */
885 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
886 #define CFSTERM 0x0002 /* SCSI low byte termination */
887 #define CFWSTERM 0x0004 /* SCSI high byte termination */
888 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
889 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
890 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
891 #define CFSTPWLEVEL 0x0040 /* Termination level control */
892 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
893 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
894 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
895
896 /*
897 * Bus Release Time, Host Adapter ID
898 */
899 uint16_t brtime_id; /* word 18 */
900 #define CFSCSIID 0x000f /* host adapter SCSI ID */
901 /* UNUSED 0x00f0 */
902 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
903
904 /*
905 * Maximum targets
906 */
907 uint16_t max_targets; /* word 19 */
908 #define CFMAXTARG 0x00ff /* maximum targets */
909 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
910 #define CFBOOTID 0xf000 /* Target to boot from */
911 uint16_t res_1[10]; /* words 20-29 */
912 uint16_t signature; /* BIOS Signature */
913 #define CFSIGNATURE 0x400
914 uint16_t checksum; /* word 31 */
915 };
916
917 /*
918 * Vital Product Data used during POST and by the BIOS.
919 */
920 struct vpd_config {
921 uint8_t bios_flags;
922 #define VPDMASTERBIOS 0x0001
923 #define VPDBOOTHOST 0x0002
924 uint8_t reserved_1[21];
925 uint8_t resource_type;
926 uint8_t resource_len[2];
927 uint8_t resource_data[8];
928 uint8_t vpd_tag;
929 uint16_t vpd_len;
930 uint8_t vpd_keyword[2];
931 uint8_t length;
932 uint8_t revision;
933 uint8_t device_flags;
934 uint8_t termnation_menus[2];
935 uint8_t fifo_threshold;
936 uint8_t end_tag;
937 uint8_t vpd_checksum;
938 uint16_t default_target_flags;
939 uint16_t default_bios_flags;
940 uint16_t default_ctrl_flags;
941 uint8_t default_irq;
942 uint8_t pci_lattime;
943 uint8_t max_target;
944 uint8_t boot_lun;
945 uint16_t signature;
946 uint8_t reserved_2;
947 uint8_t checksum;
948 uint8_t reserved_3[4];
949 };
950
951 /****************************** Flexport Logic ********************************/
952 #define FLXADDR_TERMCTL 0x0
953 #define FLX_TERMCTL_ENSECHIGH 0x8
954 #define FLX_TERMCTL_ENSECLOW 0x4
955 #define FLX_TERMCTL_ENPRIHIGH 0x2
956 #define FLX_TERMCTL_ENPRILOW 0x1
957 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
958 #define FLX_ROMSTAT_SEECFG 0xF0
959 #define FLX_ROMSTAT_EECFG 0x0F
960 #define FLX_ROMSTAT_SEE_93C66 0x00
961 #define FLX_ROMSTAT_SEE_NONE 0xF0
962 #define FLX_ROMSTAT_EE_512x8 0x0
963 #define FLX_ROMSTAT_EE_1MBx8 0x1
964 #define FLX_ROMSTAT_EE_2MBx8 0x2
965 #define FLX_ROMSTAT_EE_4MBx8 0x3
966 #define FLX_ROMSTAT_EE_16MBx8 0x4
967 #define CURSENSE_ENB 0x1
968 #define FLXADDR_FLEXSTAT 0x2
969 #define FLX_FSTAT_BUSY 0x1
970 #define FLXADDR_CURRENT_STAT 0x4
971 #define FLX_CSTAT_SEC_HIGH 0xC0
972 #define FLX_CSTAT_SEC_LOW 0x30
973 #define FLX_CSTAT_PRI_HIGH 0x0C
974 #define FLX_CSTAT_PRI_LOW 0x03
975 #define FLX_CSTAT_MASK 0x03
976 #define FLX_CSTAT_SHIFT 2
977 #define FLX_CSTAT_OKAY 0x0
978 #define FLX_CSTAT_OVER 0x1
979 #define FLX_CSTAT_UNDER 0x2
980 #define FLX_CSTAT_INVALID 0x3
981
982 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
983 u_int start_addr, u_int count, int bstream);
984
985 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
986 u_int start_addr, u_int count);
987 int ahd_wait_seeprom(struct ahd_softc *ahd);
988 int ahd_verify_vpd_cksum(struct vpd_config *vpd);
989 int ahd_verify_cksum(struct seeprom_config *sc);
990 int ahd_acquire_seeprom(struct ahd_softc *ahd);
991 void ahd_release_seeprom(struct ahd_softc *ahd);
992
993 /**************************** Message Buffer *********************************/
994 typedef enum {
995 MSG_FLAG_NONE = 0x00,
996 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
997 MSG_FLAG_IU_REQ_CHANGED = 0x02,
998 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
999 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
1000 MSG_FLAG_PACKETIZED = 0x10
1001 } ahd_msg_flags;
1002
1003 typedef enum {
1004 MSG_TYPE_NONE = 0x00,
1005 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
1006 MSG_TYPE_INITIATOR_MSGIN = 0x02,
1007 MSG_TYPE_TARGET_MSGOUT = 0x03,
1008 MSG_TYPE_TARGET_MSGIN = 0x04
1009 } ahd_msg_type;
1010
1011 typedef enum {
1012 MSGLOOP_IN_PROG,
1013 MSGLOOP_MSGCOMPLETE,
1014 MSGLOOP_TERMINATED
1015 } msg_loop_stat;
1016
1017 /*********************** Software Configuration Structure *********************/
1018 struct ahd_suspend_channel_state {
1019 uint8_t scsiseq;
1020 uint8_t sxfrctl0;
1021 uint8_t sxfrctl1;
1022 uint8_t simode0;
1023 uint8_t simode1;
1024 uint8_t seltimer;
1025 uint8_t seqctl;
1026 };
1027
1028 struct ahd_suspend_state {
1029 struct ahd_suspend_channel_state channel[2];
1030 uint8_t optionmode;
1031 uint8_t dscommand0;
1032 uint8_t dspcistatus;
1033 /* hsmailbox */
1034 uint8_t crccontrol1;
1035 uint8_t scbbaddr;
1036 /* Host and sequencer SCB counts */
1037 uint8_t dff_thrsh;
1038 uint8_t *scratch_ram;
1039 uint8_t *btt;
1040 };
1041
1042 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1043
1044 typedef enum {
1045 AHD_MODE_DFF0,
1046 AHD_MODE_DFF1,
1047 AHD_MODE_CCHAN,
1048 AHD_MODE_SCSI,
1049 AHD_MODE_CFG,
1050 AHD_MODE_UNKNOWN
1051 } ahd_mode;
1052
1053 #define AHD_MK_MSK(x) (0x01 << (x))
1054 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1055 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1056 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1057 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1058 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1059 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1060 #define AHD_MODE_ANY_MSK (~0)
1061
1062 typedef enum {
1063 AHD_SYSCTL_ROOT,
1064 AHD_SYSCTL_SUMMARY,
1065 AHD_SYSCTL_DEBUG,
1066 AHD_SYSCTL_NUMBER
1067 } ahd_sysctl_types_t;
1068
1069 typedef enum {
1070 AHD_ERRORS_CORRECTABLE,
1071 AHD_ERRORS_UNCORRECTABLE,
1072 AHD_ERRORS_FATAL,
1073 AHD_ERRORS_NUMBER
1074 } ahd_sysctl_errors_t;
1075
1076 #define AHD_CORRECTABLE_ERROR(sc) \
1077 (((sc)->summerr[AHD_ERRORS_CORRECTABLE])++)
1078 #define AHD_UNCORRECTABLE_ERROR(sc) \
1079 (((sc)->summerr[AHD_ERRORS_UNCORRECTABLE])++)
1080 #define AHD_FATAL_ERROR(sc) \
1081 (((sc)->summerr[AHD_ERRORS_FATAL])++)
1082
1083 typedef uint8_t ahd_mode_state;
1084
1085 typedef void ahd_callback_t (void *);
1086
1087 struct ahd_completion
1088 {
1089 uint16_t tag;
1090 uint8_t sg_status;
1091 uint8_t valid_tag;
1092 };
1093
1094 #define AIC_SCB_DATA(softc) (&(softc)->scb_data)
1095
1096 struct ahd_softc {
1097 bus_space_tag_t tags[2];
1098 bus_space_handle_t bshs[2];
1099 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1100 struct scb_data scb_data;
1101
1102 struct hardware_scb *next_queued_hscb;
1103 struct map_node *next_queued_hscb_map;
1104
1105 /*
1106 * SCBs that have been sent to the controller
1107 */
1108 LIST_HEAD(, scb) pending_scbs;
1109
1110 /*
1111 * SCBs whose timeout routine has been called.
1112 */
1113 LIST_HEAD(, scb) timedout_scbs;
1114
1115 /*
1116 * Current register window mode information.
1117 */
1118 ahd_mode dst_mode;
1119 ahd_mode src_mode;
1120
1121 /*
1122 * Saved register window mode information
1123 * used for restore on next unpause.
1124 */
1125 ahd_mode saved_dst_mode;
1126 ahd_mode saved_src_mode;
1127
1128 /*
1129 * Platform specific data.
1130 */
1131 struct ahd_platform_data *platform_data;
1132
1133 /*
1134 * Platform specific device information.
1135 */
1136 aic_dev_softc_t dev_softc;
1137
1138 /*
1139 * Bus specific device information.
1140 */
1141 ahd_bus_intr_t bus_intr;
1142
1143 /*
1144 * Target mode related state kept on a per enabled lun basis.
1145 * Targets that are not enabled will have null entries.
1146 * As an initiator, we keep one target entry for our initiator
1147 * ID to store our sync/wide transfer settings.
1148 */
1149 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1150
1151 /*
1152 * The black hole device responsible for handling requests for
1153 * disabled luns on enabled targets.
1154 */
1155 struct ahd_tmode_lstate *black_hole;
1156
1157 /*
1158 * Device instance currently on the bus awaiting a continue TIO
1159 * for a command that was not given the disconnect priveledge.
1160 */
1161 struct ahd_tmode_lstate *pending_device;
1162
1163 /*
1164 * Timer handles for timer driven callbacks.
1165 */
1166 aic_timer_t reset_timer;
1167 aic_timer_t stat_timer;
1168
1169 /*
1170 * Statistics.
1171 */
1172 #define AHD_STAT_UPDATE_MS 250
1173 #define AHD_STAT_BUCKETS 4
1174 u_int cmdcmplt_bucket;
1175 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1176 uint32_t cmdcmplt_total;
1177
1178 /*
1179 * Errors statistics and printouts.
1180 */
1181 struct sysctl_ctx_list sysctl_ctx[AHD_SYSCTL_NUMBER];
1182 struct sysctl_oid *sysctl_tree[AHD_SYSCTL_NUMBER];
1183 u_int summerr[AHD_ERRORS_NUMBER];
1184
1185 /*
1186 * Card characteristics
1187 */
1188 ahd_chip chip;
1189 ahd_feature features;
1190 ahd_bug bugs;
1191 ahd_flag flags;
1192 struct seeprom_config *seep_config;
1193
1194 /* Command Queues */
1195 struct ahd_completion *qoutfifo;
1196 uint16_t qoutfifonext;
1197 uint16_t qoutfifonext_valid_tag;
1198 uint16_t qinfifonext;
1199 uint16_t qinfifo[AHD_SCB_MAX];
1200
1201 /*
1202 * Our qfreeze count. The sequencer compares
1203 * this value with its own counter to determine
1204 * whether to allow selections to occur.
1205 */
1206 uint16_t qfreeze_cnt;
1207
1208 /* Values to store in the SEQCTL register for pause and unpause */
1209 uint8_t unpause;
1210 uint8_t pause;
1211
1212 /* Critical Section Data */
1213 struct cs *critical_sections;
1214 u_int num_critical_sections;
1215
1216 /* Buffer for handling packetized bitbucket. */
1217 uint8_t *overrun_buf;
1218
1219 /* Links for chaining softcs */
1220 TAILQ_ENTRY(ahd_softc) links;
1221
1222 /* Channel Names ('A', 'B', etc.) */
1223 char channel;
1224
1225 /* Initiator Bus ID */
1226 uint8_t our_id;
1227
1228 /*
1229 * Target incoming command FIFO.
1230 */
1231 struct target_cmd *targetcmds;
1232 uint8_t tqinfifonext;
1233
1234 /*
1235 * Cached verson of the hs_mailbox so we can avoid
1236 * pausing the sequencer during mailbox updates.
1237 */
1238 uint8_t hs_mailbox;
1239
1240 /*
1241 * Incoming and outgoing message handling.
1242 */
1243 uint8_t send_msg_perror;
1244 ahd_msg_flags msg_flags;
1245 ahd_msg_type msg_type;
1246 uint8_t msgout_buf[12];/* Message we are sending */
1247 uint8_t msgin_buf[12];/* Message we are receiving */
1248 u_int msgout_len; /* Length of message to send */
1249 u_int msgout_index; /* Current index in msgout */
1250 u_int msgin_index; /* Current index in msgin */
1251
1252 /*
1253 * Mapping information for data structures shared
1254 * between the sequencer and kernel.
1255 */
1256 bus_dma_tag_t parent_dmat;
1257 bus_dma_tag_t shared_data_dmat;
1258 struct map_node shared_data_map;
1259
1260 /* Information saved through suspend/resume cycles */
1261 struct ahd_suspend_state suspend_state;
1262
1263 /* Number of enabled target mode device on this card */
1264 u_int enabled_luns;
1265
1266 /* Initialization level of this data structure */
1267 u_int init_level;
1268
1269 /* PCI cacheline size. */
1270 u_int pci_cachesize;
1271
1272 /* PCI-X capability offset. */
1273 int pcix_ptr;
1274
1275 /* IO Cell Parameters */
1276 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1277
1278 u_int stack_size;
1279 uint16_t *saved_stack;
1280
1281 /* Per-Unit descriptive information */
1282 const char *description;
1283 const char *bus_description;
1284 char *name;
1285 int unit;
1286
1287 /* Selection Timer settings */
1288 int seltime;
1289
1290 /*
1291 * Interrupt coalescing settings.
1292 */
1293 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1294 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1295 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1296 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1297 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1298 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1299 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1300 u_int int_coalescing_timer;
1301 u_int int_coalescing_maxcmds;
1302 u_int int_coalescing_mincmds;
1303 u_int int_coalescing_threshold;
1304 u_int int_coalescing_stop_threshold;
1305
1306 uint16_t user_discenable;/* Disconnection allowed */
1307 uint16_t user_tagenable;/* Tagged Queuing allowed */
1308 };
1309
1310 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1311 extern struct ahd_softc_tailq ahd_tailq;
1312
1313 /*************************** IO Cell Configuration ****************************/
1314 #define AHD_PRECOMP_SLEW_INDEX \
1315 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1316
1317 #define AHD_AMPLITUDE_INDEX \
1318 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1319
1320 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1321 do { \
1322 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1323 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1324 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1325 } while (0)
1326
1327 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1328 do { \
1329 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1330 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1331 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1332 } while (0)
1333
1334 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1335 do { \
1336 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1337 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1338 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1339 } while (0)
1340
1341 /************************ Active Device Information ***************************/
1342 typedef enum {
1343 ROLE_UNKNOWN,
1344 ROLE_INITIATOR,
1345 ROLE_TARGET
1346 } role_t;
1347
1348 struct ahd_devinfo {
1349 int our_scsiid;
1350 int target_offset;
1351 uint16_t target_mask;
1352 u_int target;
1353 u_int lun;
1354 char channel;
1355 role_t role; /*
1356 * Only guaranteed to be correct if not
1357 * in the busfree state.
1358 */
1359 };
1360
1361 /****************************** PCI Structures ********************************/
1362 #define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
1363 #define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
1364 #define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
1365
1366 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1367
1368 struct ahd_pci_identity {
1369 uint64_t full_id;
1370 uint64_t id_mask;
1371 char *name;
1372 ahd_device_setup_t *setup;
1373 };
1374 extern struct ahd_pci_identity ahd_pci_ident_table [];
1375 extern const u_int ahd_num_pci_devs;
1376
1377 /*************************** Function Declarations ****************************/
1378 /******************************************************************************/
1379 void ahd_reset_cmds_pending(struct ahd_softc *ahd);
1380 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1381 void ahd_busy_tcl(struct ahd_softc *ahd,
1382 u_int tcl, u_int busyid);
1383 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1384 static __inline void
ahd_unbusy_tcl(struct ahd_softc * ahd,u_int tcl)1385 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1386 {
1387 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1388 }
1389
1390 /***************************** PCI Front End *********************************/
1391 struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t);
1392 int ahd_pci_config(struct ahd_softc *,
1393 struct ahd_pci_identity *);
1394 int ahd_pci_test_register_access(struct ahd_softc *);
1395
1396 /************************** SCB and SCB queue management **********************/
1397 int ahd_probe_scbs(struct ahd_softc *);
1398 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1399 struct scb *scb);
1400 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1401 int target, char channel, int lun,
1402 u_int tag, role_t role);
1403
1404 /****************************** Initialization ********************************/
1405 struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1406 int ahd_softc_init(struct ahd_softc *);
1407 void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1408 int ahd_init(struct ahd_softc *ahd);
1409 int ahd_default_config(struct ahd_softc *ahd);
1410 int ahd_parse_vpddata(struct ahd_softc *ahd,
1411 struct vpd_config *vpd);
1412 int ahd_parse_cfgdata(struct ahd_softc *ahd,
1413 struct seeprom_config *sc);
1414 void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1415 void ahd_update_coalescing_values(struct ahd_softc *ahd,
1416 u_int timer,
1417 u_int maxcmds,
1418 u_int mincmds);
1419 void ahd_enable_coalescing(struct ahd_softc *ahd,
1420 int enable);
1421 void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1422 int ahd_suspend(struct ahd_softc *ahd);
1423 int ahd_resume(struct ahd_softc *ahd);
1424 void ahd_softc_insert(struct ahd_softc *);
1425 void ahd_set_unit(struct ahd_softc *, int);
1426 void ahd_set_name(struct ahd_softc *, char *);
1427 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1428 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1429 int ahd_alloc_scbs(struct ahd_softc *ahd);
1430 void ahd_free(struct ahd_softc *ahd);
1431 int ahd_reset(struct ahd_softc *ahd, int reinit);
1432 void ahd_shutdown(void *arg);
1433 int ahd_write_flexport(struct ahd_softc *ahd,
1434 u_int addr, u_int value);
1435 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1436 uint8_t *value);
1437 int ahd_wait_flexport(struct ahd_softc *ahd);
1438
1439 /*************************** Interrupt Services *******************************/
1440 void ahd_pci_intr(struct ahd_softc *ahd);
1441 void ahd_clear_intstat(struct ahd_softc *ahd);
1442 void ahd_flush_qoutfifo(struct ahd_softc *ahd);
1443 void ahd_run_qoutfifo(struct ahd_softc *ahd);
1444 #ifdef AHD_TARGET_MODE
1445 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1446 #endif
1447 void ahd_handle_hwerrint(struct ahd_softc *ahd);
1448 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1449 void ahd_handle_scsiint(struct ahd_softc *ahd,
1450 u_int intstat);
1451 void ahd_clear_critical_section(struct ahd_softc *ahd);
1452
1453 /***************************** Error Recovery *********************************/
1454 typedef enum {
1455 SEARCH_COMPLETE,
1456 SEARCH_COUNT,
1457 SEARCH_REMOVE,
1458 SEARCH_PRINT
1459 } ahd_search_action;
1460 void ahd_done_with_status(struct ahd_softc *ahd,
1461 struct scb *scb, uint32_t status);
1462 int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1463 char channel, int lun, u_int tag,
1464 role_t role, uint32_t status,
1465 ahd_search_action action);
1466 int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1467 char channel, int lun, u_int tag,
1468 int stop_on_first, int remove,
1469 int save_state);
1470 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1471 int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1472 int initiate_reset);
1473 int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1474 char channel, int lun, u_int tag,
1475 role_t role, uint32_t status);
1476 void ahd_restart(struct ahd_softc *ahd);
1477 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1478 void ahd_handle_scb_status(struct ahd_softc *ahd,
1479 struct scb *scb);
1480 void ahd_handle_scsi_status(struct ahd_softc *ahd,
1481 struct scb *scb);
1482 void ahd_calc_residual(struct ahd_softc *ahd,
1483 struct scb *scb);
1484 void ahd_timeout(struct scb *scb);
1485 void ahd_recover_commands(struct ahd_softc *ahd);
1486 /*************************** Utility Functions ********************************/
1487 struct ahd_phase_table_entry*
1488 ahd_lookup_phase_entry(int phase);
1489 void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1490 u_int our_id, u_int target,
1491 u_int lun, char channel,
1492 role_t role);
1493 /************************** Transfer Negotiation ******************************/
1494 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1495 u_int *ppr_options, u_int maxsync);
1496 void ahd_validate_offset(struct ahd_softc *ahd,
1497 struct ahd_initiator_tinfo *tinfo,
1498 u_int period, u_int *offset,
1499 int wide, role_t role);
1500 void ahd_validate_width(struct ahd_softc *ahd,
1501 struct ahd_initiator_tinfo *tinfo,
1502 u_int *bus_width,
1503 role_t role);
1504 /*
1505 * Negotiation types. These are used to qualify if we should renegotiate
1506 * even if our goal and current transport parameters are identical.
1507 */
1508 typedef enum {
1509 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1510 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1511 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1512 } ahd_neg_type;
1513 int ahd_update_neg_request(struct ahd_softc*,
1514 struct ahd_devinfo*,
1515 struct ahd_tmode_tstate*,
1516 struct ahd_initiator_tinfo*,
1517 ahd_neg_type);
1518 void ahd_set_width(struct ahd_softc *ahd,
1519 struct ahd_devinfo *devinfo,
1520 u_int width, u_int type, int paused);
1521 void ahd_set_syncrate(struct ahd_softc *ahd,
1522 struct ahd_devinfo *devinfo,
1523 u_int period, u_int offset,
1524 u_int ppr_options,
1525 u_int type, int paused);
1526 typedef enum {
1527 AHD_QUEUE_NONE,
1528 AHD_QUEUE_BASIC,
1529 AHD_QUEUE_TAGGED
1530 } ahd_queue_alg;
1531
1532 void ahd_set_tags(struct ahd_softc *ahd,
1533 struct ahd_devinfo *devinfo,
1534 ahd_queue_alg alg);
1535
1536 /**************************** Target Mode *************************************/
1537 #ifdef AHD_TARGET_MODE
1538 void ahd_send_lstate_events(struct ahd_softc *,
1539 struct ahd_tmode_lstate *);
1540 void ahd_handle_en_lun(struct ahd_softc *ahd,
1541 struct cam_sim *sim, union ccb *ccb);
1542 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1543 struct cam_sim *sim, union ccb *ccb,
1544 struct ahd_tmode_tstate **tstate,
1545 struct ahd_tmode_lstate **lstate,
1546 int notfound_failure);
1547 #ifndef AHD_TMODE_ENABLE
1548 #define AHD_TMODE_ENABLE 0
1549 #endif
1550 #endif
1551 /******************************* Debug ***************************************/
1552 #ifdef AHD_DEBUG
1553 extern uint32_t ahd_debug;
1554 #define AHD_SHOW_MISC 0x00001
1555 #define AHD_SHOW_SENSE 0x00002
1556 #define AHD_SHOW_RECOVERY 0x00004
1557 #define AHD_DUMP_SEEPROM 0x00008
1558 #define AHD_SHOW_TERMCTL 0x00010
1559 #define AHD_SHOW_MEMORY 0x00020
1560 #define AHD_SHOW_MESSAGES 0x00040
1561 #define AHD_SHOW_MODEPTR 0x00080
1562 #define AHD_SHOW_SELTO 0x00100
1563 #define AHD_SHOW_FIFOS 0x00200
1564 #define AHD_SHOW_QFULL 0x00400
1565 #define AHD_SHOW_DV 0x00800
1566 #define AHD_SHOW_MASKED_ERRORS 0x01000
1567 #define AHD_SHOW_QUEUE 0x02000
1568 #define AHD_SHOW_TQIN 0x04000
1569 #define AHD_SHOW_SG 0x08000
1570 #define AHD_SHOW_INT_COALESCING 0x10000
1571 #define AHD_DEBUG_SEQUENCER 0x20000
1572 #endif
1573 void ahd_print_scb(struct scb *scb);
1574 void ahd_print_devinfo(struct ahd_softc *ahd,
1575 struct ahd_devinfo *devinfo);
1576 void ahd_dump_sglist(struct scb *scb);
1577 void ahd_dump_all_cards_state(void);
1578 void ahd_dump_card_state(struct ahd_softc *ahd);
1579 int ahd_print_register(ahd_reg_parse_entry_t *table,
1580 u_int num_entries,
1581 const char *name,
1582 u_int address,
1583 u_int value,
1584 u_int *cur_column,
1585 u_int wrap_point);
1586 void ahd_dump_scbs(struct ahd_softc *ahd);
1587 #endif /* _AIC79XX_H_ */
1588