1 /*- 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $ 43 */ 44 45 #ifndef _AIC79XX_H_ 46 #define _AIC79XX_H_ 47 48 /* Register Definitions */ 49 #include "aic79xx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahd_platform_data; 53 struct scb_platform_data; 54 55 /****************************** Useful Macros *********************************/ 56 #ifndef MAX 57 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58 #endif 59 60 #ifndef MIN 61 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62 #endif 63 64 #ifndef TRUE 65 #define TRUE 1 66 #endif 67 #ifndef FALSE 68 #define FALSE 0 69 #endif 70 71 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73 #define ALL_CHANNELS '\0' 74 #define ALL_TARGETS_MASK 0xFFFF 75 #define INITIATOR_WILDCARD (~0) 76 #define SCB_LIST_NULL 0xFF00 77 #define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 78 #define QOUTFIFO_ENTRY_VALID 0x80 79 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 80 81 #define SCSIID_TARGET(ahd, scsiid) \ 82 (((scsiid) & TID) >> TID_SHIFT) 83 #define SCSIID_OUR_ID(scsiid) \ 84 ((scsiid) & OID) 85 #define SCSIID_CHANNEL(ahd, scsiid) ('A') 86 #define SCB_IS_SCSIBUS_B(ahd, scb) (0) 87 #define SCB_GET_OUR_ID(scb) \ 88 SCSIID_OUR_ID((scb)->hscb->scsiid) 89 #define SCB_GET_TARGET(ahd, scb) \ 90 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 91 #define SCB_GET_CHANNEL(ahd, scb) \ 92 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 93 #define SCB_GET_LUN(scb) \ 94 ((scb)->hscb->lun) 95 #define SCB_GET_TARGET_OFFSET(ahd, scb) \ 96 SCB_GET_TARGET(ahd, scb) 97 #define SCB_GET_TARGET_MASK(ahd, scb) \ 98 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 99 #ifdef AHD_DEBUG 100 #define SCB_IS_SILENT(scb) \ 101 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 102 && (((scb)->flags & SCB_SILENT) != 0)) 103 #else 104 #define SCB_IS_SILENT(scb) \ 105 (((scb)->flags & SCB_SILENT) != 0) 106 #endif 107 /* 108 * TCLs have the following format: TTTTLLLLLLLL 109 */ 110 #define TCL_TARGET_OFFSET(tcl) \ 111 ((((tcl) >> 4) & TID) >> 4) 112 #define TCL_LUN(tcl) \ 113 (tcl & (AHD_NUM_LUNS - 1)) 114 #define BUILD_TCL(scsiid, lun) \ 115 ((lun) | (((scsiid) & TID) << 4)) 116 #define BUILD_TCL_RAW(target, channel, lun) \ 117 ((lun) | ((target) << 8)) 118 119 #define SCB_GET_TAG(scb) \ 120 aic_le16toh(scb->hscb->tag) 121 122 #ifndef AHD_TARGET_MODE 123 #undef AHD_TMODE_ENABLE 124 #define AHD_TMODE_ENABLE 0 125 #endif 126 127 #define AHD_BUILD_COL_IDX(target, lun) \ 128 (((lun) << 4) | target) 129 130 #define AHD_GET_SCB_COL_IDX(ahd, scb) \ 131 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 132 133 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 134 do { \ 135 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 136 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 137 } while (0) 138 139 #define AHD_COPY_SCB_COL_IDX(dst, src) \ 140 do { \ 141 dst->hscb->scsiid = src->hscb->scsiid; \ 142 dst->hscb->lun = src->hscb->lun; \ 143 } while (0) 144 145 #define AHD_NEVER_COL_IDX 0xFFFF 146 147 /**************************** Driver Constants ********************************/ 148 /* 149 * The maximum number of supported targets. 150 */ 151 #define AHD_NUM_TARGETS 16 152 153 /* 154 * The maximum number of supported luns. 155 * The identify message only supports 64 luns in non-packetized transfers. 156 * You can have 2^64 luns when information unit transfers are enabled, 157 * but until we see a need to support that many, we support 256. 158 */ 159 #define AHD_NUM_LUNS_NONPKT 64 160 #define AHD_NUM_LUNS 256 161 162 /* 163 * The maximum transfer per S/G segment. 164 */ 165 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 166 167 /* 168 * The maximum amount of SCB storage in hardware on a controller. 169 * This value represents an upper bound. Due to software design, 170 * we may not be able to use this number. 171 */ 172 #define AHD_SCB_MAX 512 173 174 /* 175 * The maximum number of concurrent transactions supported per driver instance. 176 * Sequencer Control Blocks (SCBs) store per-transaction information. 177 */ 178 #define AHD_MAX_QUEUE AHD_SCB_MAX 179 180 /* 181 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 182 * in size and accommodate as many transactions as can be queued concurrently. 183 */ 184 #define AHD_QIN_SIZE AHD_MAX_QUEUE 185 #define AHD_QOUT_SIZE AHD_MAX_QUEUE 186 187 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 188 /* 189 * The maximum amount of SCB storage we allocate in host memory. 190 */ 191 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 192 193 /* 194 * Ring Buffer of incoming target commands. 195 * We allocate 256 to simplify the logic in the sequencer 196 * by using the natural wrap point of an 8bit counter. 197 */ 198 #define AHD_TMODE_CMDS 256 199 200 /* Reset line assertion time in us */ 201 #define AHD_BUSRESET_DELAY 25 202 203 /******************* Chip Characteristics/Operating Settings *****************/ 204 extern uint32_t ahd_attach_to_HostRAID_controllers; 205 206 /* 207 * Chip Type 208 * The chip order is from least sophisticated to most sophisticated. 209 */ 210 typedef enum { 211 AHD_NONE = 0x0000, 212 AHD_CHIPID_MASK = 0x00FF, 213 AHD_AIC7901 = 0x0001, 214 AHD_AIC7902 = 0x0002, 215 AHD_AIC7901A = 0x0003, 216 AHD_PCI = 0x0100, /* Bus type PCI */ 217 AHD_PCIX = 0x0200, /* Bus type PCIX */ 218 AHD_BUS_MASK = 0x0F00 219 } ahd_chip; 220 221 /* 222 * Features available in each chip type. 223 */ 224 typedef enum { 225 AHD_FENONE = 0x00000, 226 AHD_WIDE = 0x00001,/* Wide Channel */ 227 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 228 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 229 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 230 AHD_RTI = 0x04000,/* Retained Training Support */ 231 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 232 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 233 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 234 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 235 AHD_AIC7901_FE = AHD_FENONE, 236 AHD_AIC7901A_FE = AHD_FENONE, 237 AHD_AIC7902_FE = AHD_MULTI_FUNC 238 } ahd_feature; 239 240 /* 241 * Bugs in the silicon that we work around in software. 242 */ 243 typedef enum { 244 AHD_BUGNONE = 0x0000, 245 /* 246 * Rev A hardware fails to update LAST/CURR/NEXTSCB 247 * correctly in certain packetized selection cases. 248 */ 249 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 250 /* The wrong SCB is accessed to check the abort pending bit. */ 251 AHD_ABORT_LQI_BUG = 0x0002, 252 /* Packetized bitbucket crosses packet boundaries. */ 253 AHD_PKT_BITBUCKET_BUG = 0x0004, 254 /* The selection timer runs twice as long as its setting. */ 255 AHD_LONG_SETIMO_BUG = 0x0008, 256 /* The Non-LQ CRC error status is delayed until phase change. */ 257 AHD_NLQICRC_DELAYED_BUG = 0x0010, 258 /* The chip must be reset for all outgoing bus resets. */ 259 AHD_SCSIRST_BUG = 0x0020, 260 /* Some PCIX fields must be saved and restored across chip reset. */ 261 AHD_PCIX_CHIPRST_BUG = 0x0040, 262 /* MMAPIO is not functional in PCI-X mode. */ 263 AHD_PCIX_MMAPIO_BUG = 0x0080, 264 /* Reads to SCBRAM fail to reset the discard timer. */ 265 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 266 /* Bug workarounds that can be disabled on non-PCIX busses. */ 267 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 268 | AHD_PCIX_MMAPIO_BUG 269 | AHD_PCIX_SCBRAM_RD_BUG, 270 /* 271 * LQOSTOP0 status set even for forced selections with ATN 272 * to perform non-packetized message delivery. 273 */ 274 AHD_LQO_ATNO_BUG = 0x0200, 275 /* FIFO auto-flush does not always trigger. */ 276 AHD_AUTOFLUSH_BUG = 0x0400, 277 /* The CLRLQO registers are not self-clearing. */ 278 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 279 /* The PACKETIZED status bit refers to the previous connection. */ 280 AHD_PKTIZED_STATUS_BUG = 0x1000, 281 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 282 AHD_PKT_LUN_BUG = 0x2000, 283 /* 284 * Only the FIFO allocated to the non-packetized connection may 285 * be in use during a non-packetzied connection. 286 */ 287 AHD_NONPACKFIFO_BUG = 0x4000, 288 /* 289 * Writing to a DFF SCBPTR register may fail if concurrent with 290 * a hardware write to the other DFF SCBPTR register. This is 291 * not currently a concern in our sequencer since all chips with 292 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 293 * occur in non-packetized connections. 294 */ 295 AHD_MDFF_WSCBPTR_BUG = 0x8000, 296 /* SGHADDR updates are slow. */ 297 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 298 /* 299 * Changing the MODE_PTR coincident with an interrupt that 300 * switches to a different mode will cause the interrupt to 301 * be in the mode written outside of interrupt context. 302 */ 303 AHD_SET_MODE_BUG = 0x20000, 304 /* Non-packetized busfree revision does not work. */ 305 AHD_BUSFREEREV_BUG = 0x40000, 306 /* 307 * Paced transfers are indicated with a non-standard PPR 308 * option bit in the neg table, 160MHz is indicated by 309 * sync factor 0x7, and the offset if off by a factor of 2. 310 */ 311 AHD_PACED_NEGTABLE_BUG = 0x80000, 312 /* LQOOVERRUN false positives. */ 313 AHD_LQOOVERRUN_BUG = 0x100000, 314 /* 315 * Controller write to INTSTAT will lose to a host 316 * write to CLRINT. 317 */ 318 AHD_INTCOLLISION_BUG = 0x200000, 319 /* 320 * The GEM318 violates the SCSI spec by not waiting 321 * the mandated bus settle delay between phase changes 322 * in some situations. Some aic79xx chip revs. are more 323 * strict in this regard and will treat REQ assertions 324 * that fall within the bus settle delay window as 325 * glitches. This flag tells the firmware to tolerate 326 * early REQ assertions. 327 */ 328 AHD_EARLY_REQ_BUG = 0x400000, 329 /* 330 * The LED does not stay on long enough in packetized modes. 331 */ 332 AHD_FAINT_LED_BUG = 0x800000 333 } ahd_bug; 334 335 /* 336 * Configuration specific settings. 337 * The driver determines these settings by probing the 338 * chip/controller's configuration. 339 */ 340 typedef enum { 341 AHD_FNONE = 0x00000, 342 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 343 AHD_USEDEFAULTS = 0x00004,/* 344 * For cards without an seeprom 345 * or a BIOS to initialize the chip's 346 * SRAM, we use the default target 347 * settings. 348 */ 349 AHD_SEQUENCER_DEBUG = 0x00008, 350 AHD_RESET_BUS_A = 0x00010, 351 AHD_EXTENDED_TRANS_A = 0x00020, 352 AHD_TERM_ENB_A = 0x00040, 353 AHD_SPCHK_ENB_A = 0x00080, 354 AHD_STPWLEVEL_A = 0x00100, 355 AHD_INITIATORROLE = 0x00200,/* 356 * Allow initiator operations on 357 * this controller. 358 */ 359 AHD_TARGETROLE = 0x00400,/* 360 * Allow target operations on this 361 * controller. 362 */ 363 AHD_RESOURCE_SHORTAGE = 0x00800, 364 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 365 AHD_INT50_SPEEDFLEX = 0x02000,/* 366 * Internal 50pin connector 367 * sits behind an aic3860 368 */ 369 AHD_BIOS_ENABLED = 0x04000, 370 AHD_ALL_INTERRUPTS = 0x08000, 371 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 372 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 373 AHD_CURRENT_SENSING = 0x40000, 374 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 375 AHD_HP_BOARD = 0x100000, 376 AHD_RESET_POLL_ACTIVE = 0x200000, 377 AHD_UPDATE_PEND_CMDS = 0x400000, 378 AHD_RUNNING_QOUTFIFO = 0x800000, 379 AHD_HAD_FIRST_SEL = 0x1000000, 380 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */ 381 AHD_HOSTRAID_BOARD = 0x4000000 382 } ahd_flag; 383 384 /************************* Hardware SCB Definition ***************************/ 385 386 /* 387 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 388 * consists of a "hardware SCB" mirroring the fields available on the card 389 * and additional information the kernel stores for each transaction. 390 * 391 * To minimize space utilization, a portion of the hardware scb stores 392 * different data during different portions of a SCSI transaction. 393 * As initialized by the host driver for the initiator role, this area 394 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 395 * the cdb has been presented to the target, this area serves to store 396 * residual transfer information and the SCSI status byte. 397 * For the target role, the contents of this area do not change, but 398 * still serve a different purpose than for the initiator role. See 399 * struct target_data for details. 400 */ 401 402 /* 403 * Status information embedded in the shared poriton of 404 * an SCB after passing the cdb to the target. The kernel 405 * driver will only read this data for transactions that 406 * complete abnormally. 407 */ 408 struct initiator_status { 409 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 410 uint32_t residual_sgptr; /* The next S/G for this transfer */ 411 uint8_t scsi_status; /* Standard SCSI status byte */ 412 }; 413 414 struct target_status { 415 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 416 uint32_t residual_sgptr; /* The next S/G for this transfer */ 417 uint8_t scsi_status; /* SCSI status to give to initiator */ 418 uint8_t target_phases; /* Bitmap of phases to execute */ 419 uint8_t data_phase; /* Data-In or Data-Out */ 420 uint8_t initiator_tag; /* Initiator's transaction tag */ 421 }; 422 423 /* 424 * Initiator mode SCB shared data area. 425 * If the embedded CDB is 12 bytes or less, we embed 426 * the sense buffer address in the SCB. This allows 427 * us to retrieve sense information without interrupting 428 * the host in packetized mode. 429 */ 430 typedef uint32_t sense_addr_t; 431 #define MAX_CDB_LEN 16 432 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 433 union initiator_data { 434 struct { 435 uint64_t cdbptr; 436 uint8_t cdblen; 437 } cdb_from_host; 438 uint8_t cdb[MAX_CDB_LEN]; 439 struct { 440 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 441 sense_addr_t sense_addr; 442 } cdb_plus_saddr; 443 }; 444 445 /* 446 * Target mode version of the shared data SCB segment. 447 */ 448 struct target_data { 449 uint32_t spare[2]; 450 uint8_t scsi_status; /* SCSI status to give to initiator */ 451 uint8_t target_phases; /* Bitmap of phases to execute */ 452 uint8_t data_phase; /* Data-In or Data-Out */ 453 uint8_t initiator_tag; /* Initiator's transaction tag */ 454 }; 455 456 struct hardware_scb { 457 /*0*/ union { 458 union initiator_data idata; 459 struct target_data tdata; 460 struct initiator_status istatus; 461 struct target_status tstatus; 462 } shared_data; 463 /* 464 * A word about residuals. 465 * The scb is presented to the sequencer with the dataptr and datacnt 466 * fields initialized to the contents of the first S/G element to 467 * transfer. The sgptr field is initialized to the bus address for 468 * the S/G element that follows the first in the in core S/G array 469 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 470 * S/G entry for this transfer (single S/G element transfer with the 471 * first elements address and length preloaded in the dataptr/datacnt 472 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 473 * The SG_FULL_RESID flag ensures that the residual will be correctly 474 * noted even if no data transfers occur. Once the data phase is entered, 475 * the residual sgptr and datacnt are loaded from the sgptr and the 476 * datacnt fields. After each S/G element's dataptr and length are 477 * loaded into the hardware, the residual sgptr is advanced. After 478 * each S/G element is expired, its datacnt field is checked to see 479 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 480 * residual sg ptr and the transfer is considered complete. If the 481 * sequencer determines that there is a residual in the transfer, or 482 * there is non-zero status, it will set the SG_STATUS_VALID flag in 483 * sgptr and dma the scb back into host memory. To sumarize: 484 * 485 * Sequencer: 486 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 487 * or residual_sgptr does not have SG_LIST_NULL set. 488 * 489 * o We are transferring the last segment if residual_datacnt has 490 * the SG_LAST_SEG flag set. 491 * 492 * Host: 493 * o A residual can only have occurred if a completed scb has the 494 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 495 * the residual_datacnt, and the residual_sgptr field will tell 496 * for sure. 497 * 498 * o residual_sgptr and sgptr refer to the "next" sg entry 499 * and so may point beyond the last valid sg entry for the 500 * transfer. 501 */ 502 #define SG_PTR_MASK 0xFFFFFFF8 503 /*16*/ uint16_t tag; /* Reused by Sequencer. */ 504 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 505 /*19*/ uint8_t scsiid; /* 506 * Selection out Id 507 * Our Id (bits 0-3) Their ID (bits 4-7) 508 */ 509 /*20*/ uint8_t lun; 510 /*21*/ uint8_t task_attribute; 511 /*22*/ uint8_t cdb_len; 512 /*23*/ uint8_t task_management; 513 /*24*/ uint64_t dataptr; 514 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 515 /*36*/ uint32_t sgptr; 516 /*40*/ uint32_t hscb_busaddr; 517 /*44*/ uint32_t next_hscb_busaddr; 518 /********** Long lun field only downloaded for full 8 byte lun support ********/ 519 /*48*/ uint8_t pkt_long_lun[8]; 520 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 521 /*56*/ uint8_t spare[8]; 522 }; 523 524 /************************ Kernel SCB Definitions ******************************/ 525 /* 526 * Some fields of the SCB are OS dependent. Here we collect the 527 * definitions for elements that all OS platforms need to include 528 * in there SCB definition. 529 */ 530 531 /* 532 * Definition of a scatter/gather element as transferred to the controller. 533 * The aic7xxx chips only support a 24bit length. We use the top byte of 534 * the length to store additional address bits and a flag to indicate 535 * that a given segment terminates the transfer. This gives us an 536 * addressable range of 512GB on machines with 64bit PCI or with chips 537 * that can support dual address cycles on 32bit PCI busses. 538 */ 539 struct ahd_dma_seg { 540 uint32_t addr; 541 uint32_t len; 542 #define AHD_DMA_LAST_SEG 0x80000000 543 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000 544 #define AHD_SG_LEN_MASK 0x00FFFFFF 545 }; 546 547 struct ahd_dma64_seg { 548 uint64_t addr; 549 uint32_t len; 550 uint32_t pad; 551 }; 552 553 struct map_node { 554 bus_dmamap_t dmamap; 555 bus_addr_t busaddr; 556 uint8_t *vaddr; 557 SLIST_ENTRY(map_node) links; 558 }; 559 560 /* 561 * The current state of this SCB. 562 */ 563 typedef enum { 564 SCB_FLAG_NONE = 0x00000, 565 SCB_TRANSMISSION_ERROR = 0x00001,/* 566 * We detected a parity or CRC 567 * error that has effected the 568 * payload of the command. This 569 * flag is checked when normal 570 * status is returned to catch 571 * the case of a target not 572 * responding to our attempt 573 * to report the error. 574 */ 575 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 576 * Another device was active 577 * during the first timeout for 578 * this SCB so we gave ourselves 579 * an additional timeout period 580 * in case it was hogging the 581 * bus. 582 */ 583 SCB_DEVICE_RESET = 0x00004, 584 SCB_SENSE = 0x00008, 585 SCB_CDB32_PTR = 0x00010, 586 SCB_RECOVERY_SCB = 0x00020, 587 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 588 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 589 SCB_ABORT = 0x00100, 590 SCB_ACTIVE = 0x00200, 591 SCB_TARGET_IMMEDIATE = 0x00400, 592 SCB_PACKETIZED = 0x00800, 593 SCB_EXPECT_PPR_BUSFREE = 0x01000, 594 SCB_PKT_SENSE = 0x02000, 595 SCB_CMDPHASE_ABORT = 0x04000, 596 SCB_ON_COL_LIST = 0x08000, 597 SCB_SILENT = 0x10000,/* 598 * Be quiet about transmission type 599 * errors. They are expected and we 600 * don't want to upset the user. This 601 * flag is typically used during DV. 602 */ 603 SCB_TIMEDOUT = 0x20000/* 604 * SCB has timed out and is on the 605 * timedout list. 606 */ 607 } scb_flag; 608 609 struct scb { 610 struct hardware_scb *hscb; 611 union { 612 SLIST_ENTRY(scb) sle; 613 LIST_ENTRY(scb) le; 614 TAILQ_ENTRY(scb) tqe; 615 } links; 616 union { 617 SLIST_ENTRY(scb) sle; 618 LIST_ENTRY(scb) le; 619 TAILQ_ENTRY(scb) tqe; 620 } links2; 621 #define pending_links links2.le 622 #define collision_links links2.le 623 LIST_ENTRY(scb) timedout_links; 624 struct scb *col_scb; 625 aic_io_ctx_t io_ctx; 626 struct ahd_softc *ahd_softc; 627 scb_flag flags; 628 #ifndef __linux__ 629 bus_dmamap_t dmamap; 630 #endif 631 struct scb_platform_data *platform_data; 632 struct map_node *hscb_map; 633 struct map_node *sg_map; 634 struct map_node *sense_map; 635 void *sg_list; 636 uint8_t *sense_data; 637 bus_addr_t sg_list_busaddr; 638 bus_addr_t sense_busaddr; 639 u_int sg_count;/* How full ahd_dma_seg is */ 640 #define AHD_MAX_LQ_CRC_ERRORS 5 641 u_int crc_retry_count; 642 aic_timer_t io_timer; 643 }; 644 645 TAILQ_HEAD(scb_tailq, scb); 646 LIST_HEAD(scb_list, scb); 647 648 struct scb_data { 649 /* 650 * TAILQ of lists of free SCBs grouped by device 651 * collision domains. 652 */ 653 struct scb_tailq free_scbs; 654 655 /* 656 * Per-device lists of SCBs whose tag ID would collide 657 * with an already active tag on the device. 658 */ 659 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 660 661 /* 662 * SCBs that will not collide with any active device. 663 */ 664 struct scb_list any_dev_free_scb_list; 665 666 /* 667 * Mapping from tag to SCB. 668 */ 669 struct scb *scbindex[AHD_SCB_MAX]; 670 671 u_int recovery_scbs; /* Transactions currently in recovery */ 672 673 /* 674 * "Bus" addresses of our data structures. 675 */ 676 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 677 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 678 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 679 680 SLIST_HEAD(, map_node) hscb_maps; 681 SLIST_HEAD(, map_node) sg_maps; 682 SLIST_HEAD(, map_node) sense_maps; 683 int scbs_left; /* unallocated scbs in head map_node */ 684 int sgs_left; /* unallocated sgs in head map_node */ 685 int sense_left; /* unallocated sense in head map_node */ 686 uint16_t numscbs; 687 uint16_t maxhscbs; /* Number of SCBs on the card */ 688 uint8_t init_level; /* 689 * How far we've initialized 690 * this structure. 691 */ 692 }; 693 694 /************************ Target Mode Definitions *****************************/ 695 696 /* 697 * Connection descriptor for select-in requests in target mode. 698 */ 699 struct target_cmd { 700 uint8_t scsiid; /* Our ID and the initiator's ID */ 701 uint8_t identify; /* Identify message */ 702 uint8_t bytes[22]; /* 703 * Bytes contains any additional message 704 * bytes terminated by 0xFF. The remainder 705 * is the cdb to execute. 706 */ 707 uint8_t cmd_valid; /* 708 * When a command is complete, the firmware 709 * will set cmd_valid to all bits set. 710 * After the host has seen the command, 711 * the bits are cleared. This allows us 712 * to just peek at host memory to determine 713 * if more work is complete. cmd_valid is on 714 * an 8 byte boundary to simplify setting 715 * it on aic7880 hardware which only has 716 * limited direct access to the DMA FIFO. 717 */ 718 uint8_t pad[7]; 719 }; 720 721 /* 722 * Number of events we can buffer up if we run out 723 * of immediate notify ccbs. 724 */ 725 #define AHD_TMODE_EVENT_BUFFER_SIZE 8 726 struct ahd_tmode_event { 727 uint8_t initiator_id; 728 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 729 #define EVENT_TYPE_BUS_RESET 0xFF 730 uint8_t event_arg; 731 }; 732 733 /* 734 * Per enabled lun target mode state. 735 * As this state is directly influenced by the host OS'es target mode 736 * environment, we let the OS module define it. Forward declare the 737 * structure here so we can store arrays of them, etc. in OS neutral 738 * data structures. 739 */ 740 #ifdef AHD_TARGET_MODE 741 struct ahd_tmode_lstate { 742 struct cam_path *path; 743 struct ccb_hdr_slist accept_tios; 744 struct ccb_hdr_slist immed_notifies; 745 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 746 uint8_t event_r_idx; 747 uint8_t event_w_idx; 748 }; 749 #else 750 struct ahd_tmode_lstate; 751 #endif 752 753 /******************** Transfer Negotiation Datastructures *********************/ 754 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 755 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 756 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 757 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 758 #define AHD_PERIOD_10MHz 0x19 759 760 #define AHD_WIDTH_UNKNOWN 0xFF 761 #define AHD_PERIOD_UNKNOWN 0xFF 762 #define AHD_OFFSET_UNKNOWN 0xFF 763 #define AHD_PPR_OPTS_UNKNOWN 0xFF 764 765 /* 766 * Transfer Negotiation Information. 767 */ 768 struct ahd_transinfo { 769 uint8_t protocol_version; /* SCSI Revision level */ 770 uint8_t transport_version; /* SPI Revision level */ 771 uint8_t width; /* Bus width */ 772 uint8_t period; /* Sync rate factor */ 773 uint8_t offset; /* Sync offset */ 774 uint8_t ppr_options; /* Parallel Protocol Request options */ 775 }; 776 777 /* 778 * Per-initiator current, goal and user transfer negotiation information. */ 779 struct ahd_initiator_tinfo { 780 struct ahd_transinfo curr; 781 struct ahd_transinfo goal; 782 struct ahd_transinfo user; 783 }; 784 785 /* 786 * Per enabled target ID state. 787 * Pointers to lun target state as well as sync/wide negotiation information 788 * for each initiator<->target mapping. For the initiator role we pretend 789 * that we are the target and the targets are the initiators since the 790 * negotiation is the same regardless of role. 791 */ 792 struct ahd_tmode_tstate { 793 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 794 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 795 796 /* 797 * Per initiator state bitmasks. 798 */ 799 uint16_t auto_negotiate;/* Auto Negotiation Required */ 800 uint16_t discenable; /* Disconnection allowed */ 801 uint16_t tagenable; /* Tagged Queuing allowed */ 802 }; 803 804 /* 805 * Points of interest along the negotiated transfer scale. 806 */ 807 #define AHD_SYNCRATE_160 0x8 808 #define AHD_SYNCRATE_PACED 0x8 809 #define AHD_SYNCRATE_DT 0x9 810 #define AHD_SYNCRATE_ULTRA2 0xa 811 #define AHD_SYNCRATE_ULTRA 0xc 812 #define AHD_SYNCRATE_FAST 0x19 813 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 814 #define AHD_SYNCRATE_SYNC 0x32 815 #define AHD_SYNCRATE_MIN 0x60 816 #define AHD_SYNCRATE_ASYNC 0xFF 817 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 818 819 /* Safe and valid period for async negotiations. */ 820 #define AHD_ASYNC_XFER_PERIOD 0x44 821 822 /* 823 * In RevA, the synctable uses a 120MHz rate for the period 824 * factor 8 and 160MHz for the period factor 7. The 120MHz 825 * rate never made it into the official SCSI spec, so we must 826 * compensate when setting the negotiation table for Rev A 827 * parts. 828 */ 829 #define AHD_SYNCRATE_REVA_120 0x8 830 #define AHD_SYNCRATE_REVA_160 0x7 831 832 /***************************** Lookup Tables **********************************/ 833 /* 834 * Phase -> name and message out response 835 * to parity errors in each phase table. 836 */ 837 struct ahd_phase_table_entry { 838 uint8_t phase; 839 uint8_t mesg_out; /* Message response to parity errors */ 840 char *phasemsg; 841 }; 842 843 /************************** Serial EEPROM Format ******************************/ 844 845 struct seeprom_config { 846 /* 847 * Per SCSI ID Configuration Flags 848 */ 849 uint16_t device_flags[16]; /* words 0-15 */ 850 #define CFXFER 0x003F /* synchronous transfer rate */ 851 #define CFXFER_ASYNC 0x3F 852 #define CFQAS 0x0040 /* Negotiate QAS */ 853 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 854 #define CFSTART 0x0100 /* send start unit SCSI command */ 855 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 856 #define CFDISC 0x0400 /* enable disconnection */ 857 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 858 #define CFWIDEB 0x1000 /* wide bus device */ 859 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 860 861 /* 862 * BIOS Control Bits 863 */ 864 uint16_t bios_control; /* word 16 */ 865 #define CFSUPREM 0x0001 /* support all removeable drives */ 866 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 867 #define CFBIOSSTATE 0x000C /* BIOS Action State */ 868 #define CFBS_DISABLED 0x00 869 #define CFBS_ENABLED 0x04 870 #define CFBS_DISABLED_SCAN 0x08 871 #define CFENABLEDV 0x0010 /* Perform Domain Validation */ 872 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 873 #define CFSPARITY 0x0040 /* SCSI parity */ 874 #define CFEXTEND 0x0080 /* extended translation enabled */ 875 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 876 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 877 #define CFMSG_VERBOSE 0x0000 878 #define CFMSG_SILENT 0x0200 879 #define CFMSG_DIAG 0x0400 880 #define CFRESETB 0x0800 /* reset SCSI bus at boot */ 881 /* UNUSED 0xf000 */ 882 883 /* 884 * Host Adapter Control Bits 885 */ 886 uint16_t adapter_control; /* word 17 */ 887 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 888 #define CFSTERM 0x0002 /* SCSI low byte termination */ 889 #define CFWSTERM 0x0004 /* SCSI high byte termination */ 890 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 891 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 892 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 893 #define CFSTPWLEVEL 0x0040 /* Termination level control */ 894 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 895 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 896 #define CFCLUSTERENB 0x8000 /* Cluster Enable */ 897 898 /* 899 * Bus Release Time, Host Adapter ID 900 */ 901 uint16_t brtime_id; /* word 18 */ 902 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 903 /* UNUSED 0x00f0 */ 904 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 905 906 /* 907 * Maximum targets 908 */ 909 uint16_t max_targets; /* word 19 */ 910 #define CFMAXTARG 0x00ff /* maximum targets */ 911 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 912 #define CFBOOTID 0xf000 /* Target to boot from */ 913 uint16_t res_1[10]; /* words 20-29 */ 914 uint16_t signature; /* BIOS Signature */ 915 #define CFSIGNATURE 0x400 916 uint16_t checksum; /* word 31 */ 917 }; 918 919 /* 920 * Vital Product Data used during POST and by the BIOS. 921 */ 922 struct vpd_config { 923 uint8_t bios_flags; 924 #define VPDMASTERBIOS 0x0001 925 #define VPDBOOTHOST 0x0002 926 uint8_t reserved_1[21]; 927 uint8_t resource_type; 928 uint8_t resource_len[2]; 929 uint8_t resource_data[8]; 930 uint8_t vpd_tag; 931 uint16_t vpd_len; 932 uint8_t vpd_keyword[2]; 933 uint8_t length; 934 uint8_t revision; 935 uint8_t device_flags; 936 uint8_t termnation_menus[2]; 937 uint8_t fifo_threshold; 938 uint8_t end_tag; 939 uint8_t vpd_checksum; 940 uint16_t default_target_flags; 941 uint16_t default_bios_flags; 942 uint16_t default_ctrl_flags; 943 uint8_t default_irq; 944 uint8_t pci_lattime; 945 uint8_t max_target; 946 uint8_t boot_lun; 947 uint16_t signature; 948 uint8_t reserved_2; 949 uint8_t checksum; 950 uint8_t reserved_3[4]; 951 }; 952 953 /****************************** Flexport Logic ********************************/ 954 #define FLXADDR_TERMCTL 0x0 955 #define FLX_TERMCTL_ENSECHIGH 0x8 956 #define FLX_TERMCTL_ENSECLOW 0x4 957 #define FLX_TERMCTL_ENPRIHIGH 0x2 958 #define FLX_TERMCTL_ENPRILOW 0x1 959 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1 960 #define FLX_ROMSTAT_SEECFG 0xF0 961 #define FLX_ROMSTAT_EECFG 0x0F 962 #define FLX_ROMSTAT_SEE_93C66 0x00 963 #define FLX_ROMSTAT_SEE_NONE 0xF0 964 #define FLX_ROMSTAT_EE_512x8 0x0 965 #define FLX_ROMSTAT_EE_1MBx8 0x1 966 #define FLX_ROMSTAT_EE_2MBx8 0x2 967 #define FLX_ROMSTAT_EE_4MBx8 0x3 968 #define FLX_ROMSTAT_EE_16MBx8 0x4 969 #define CURSENSE_ENB 0x1 970 #define FLXADDR_FLEXSTAT 0x2 971 #define FLX_FSTAT_BUSY 0x1 972 #define FLXADDR_CURRENT_STAT 0x4 973 #define FLX_CSTAT_SEC_HIGH 0xC0 974 #define FLX_CSTAT_SEC_LOW 0x30 975 #define FLX_CSTAT_PRI_HIGH 0x0C 976 #define FLX_CSTAT_PRI_LOW 0x03 977 #define FLX_CSTAT_MASK 0x03 978 #define FLX_CSTAT_SHIFT 2 979 #define FLX_CSTAT_OKAY 0x0 980 #define FLX_CSTAT_OVER 0x1 981 #define FLX_CSTAT_UNDER 0x2 982 #define FLX_CSTAT_INVALID 0x3 983 984 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 985 u_int start_addr, u_int count, int bstream); 986 987 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 988 u_int start_addr, u_int count); 989 int ahd_wait_seeprom(struct ahd_softc *ahd); 990 int ahd_verify_vpd_cksum(struct vpd_config *vpd); 991 int ahd_verify_cksum(struct seeprom_config *sc); 992 int ahd_acquire_seeprom(struct ahd_softc *ahd); 993 void ahd_release_seeprom(struct ahd_softc *ahd); 994 995 /**************************** Message Buffer *********************************/ 996 typedef enum { 997 MSG_FLAG_NONE = 0x00, 998 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 999 MSG_FLAG_IU_REQ_CHANGED = 0x02, 1000 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 1001 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 1002 MSG_FLAG_PACKETIZED = 0x10 1003 } ahd_msg_flags; 1004 1005 typedef enum { 1006 MSG_TYPE_NONE = 0x00, 1007 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 1008 MSG_TYPE_INITIATOR_MSGIN = 0x02, 1009 MSG_TYPE_TARGET_MSGOUT = 0x03, 1010 MSG_TYPE_TARGET_MSGIN = 0x04 1011 } ahd_msg_type; 1012 1013 typedef enum { 1014 MSGLOOP_IN_PROG, 1015 MSGLOOP_MSGCOMPLETE, 1016 MSGLOOP_TERMINATED 1017 } msg_loop_stat; 1018 1019 /*********************** Software Configuration Structure *********************/ 1020 struct ahd_suspend_channel_state { 1021 uint8_t scsiseq; 1022 uint8_t sxfrctl0; 1023 uint8_t sxfrctl1; 1024 uint8_t simode0; 1025 uint8_t simode1; 1026 uint8_t seltimer; 1027 uint8_t seqctl; 1028 }; 1029 1030 struct ahd_suspend_state { 1031 struct ahd_suspend_channel_state channel[2]; 1032 uint8_t optionmode; 1033 uint8_t dscommand0; 1034 uint8_t dspcistatus; 1035 /* hsmailbox */ 1036 uint8_t crccontrol1; 1037 uint8_t scbbaddr; 1038 /* Host and sequencer SCB counts */ 1039 uint8_t dff_thrsh; 1040 uint8_t *scratch_ram; 1041 uint8_t *btt; 1042 }; 1043 1044 typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1045 1046 typedef enum { 1047 AHD_MODE_DFF0, 1048 AHD_MODE_DFF1, 1049 AHD_MODE_CCHAN, 1050 AHD_MODE_SCSI, 1051 AHD_MODE_CFG, 1052 AHD_MODE_UNKNOWN 1053 } ahd_mode; 1054 1055 #define AHD_MK_MSK(x) (0x01 << (x)) 1056 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1057 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1058 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1059 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1060 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1061 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1062 #define AHD_MODE_ANY_MSK (~0) 1063 1064 typedef enum { 1065 AHD_SYSCTL_ROOT, 1066 AHD_SYSCTL_SUMMARY, 1067 AHD_SYSCTL_DEBUG, 1068 AHD_SYSCTL_NUMBER 1069 } ahd_sysctl_types_t; 1070 1071 typedef enum { 1072 AHD_ERRORS_CORRECTABLE, 1073 AHD_ERRORS_UNCORRECTABLE, 1074 AHD_ERRORS_FATAL, 1075 AHD_ERRORS_NUMBER 1076 } ahd_sysctl_errors_t; 1077 1078 #define AHD_CORRECTABLE_ERROR(sc) \ 1079 (((sc)->summerr[AHD_ERRORS_CORRECTABLE])++) 1080 #define AHD_UNCORRECTABLE_ERROR(sc) \ 1081 (((sc)->summerr[AHD_ERRORS_UNCORRECTABLE])++) 1082 #define AHD_FATAL_ERROR(sc) \ 1083 (((sc)->summerr[AHD_ERRORS_FATAL])++) 1084 1085 typedef uint8_t ahd_mode_state; 1086 1087 typedef void ahd_callback_t (void *); 1088 1089 struct ahd_completion 1090 { 1091 uint16_t tag; 1092 uint8_t sg_status; 1093 uint8_t valid_tag; 1094 }; 1095 1096 #define AIC_SCB_DATA(softc) (&(softc)->scb_data) 1097 1098 struct ahd_softc { 1099 bus_space_tag_t tags[2]; 1100 bus_space_handle_t bshs[2]; 1101 #ifndef __linux__ 1102 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1103 #endif 1104 struct scb_data scb_data; 1105 1106 struct hardware_scb *next_queued_hscb; 1107 struct map_node *next_queued_hscb_map; 1108 1109 /* 1110 * SCBs that have been sent to the controller 1111 */ 1112 LIST_HEAD(, scb) pending_scbs; 1113 1114 /* 1115 * SCBs whose timeout routine has been called. 1116 */ 1117 LIST_HEAD(, scb) timedout_scbs; 1118 1119 /* 1120 * Current register window mode information. 1121 */ 1122 ahd_mode dst_mode; 1123 ahd_mode src_mode; 1124 1125 /* 1126 * Saved register window mode information 1127 * used for restore on next unpause. 1128 */ 1129 ahd_mode saved_dst_mode; 1130 ahd_mode saved_src_mode; 1131 1132 /* 1133 * Platform specific data. 1134 */ 1135 struct ahd_platform_data *platform_data; 1136 1137 /* 1138 * Platform specific device information. 1139 */ 1140 aic_dev_softc_t dev_softc; 1141 1142 /* 1143 * Bus specific device information. 1144 */ 1145 ahd_bus_intr_t bus_intr; 1146 1147 /* 1148 * Target mode related state kept on a per enabled lun basis. 1149 * Targets that are not enabled will have null entries. 1150 * As an initiator, we keep one target entry for our initiator 1151 * ID to store our sync/wide transfer settings. 1152 */ 1153 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1154 1155 /* 1156 * The black hole device responsible for handling requests for 1157 * disabled luns on enabled targets. 1158 */ 1159 struct ahd_tmode_lstate *black_hole; 1160 1161 /* 1162 * Device instance currently on the bus awaiting a continue TIO 1163 * for a command that was not given the disconnect priveledge. 1164 */ 1165 struct ahd_tmode_lstate *pending_device; 1166 1167 /* 1168 * Timer handles for timer driven callbacks. 1169 */ 1170 aic_timer_t reset_timer; 1171 aic_timer_t stat_timer; 1172 1173 /* 1174 * Statistics. 1175 */ 1176 #define AHD_STAT_UPDATE_MS 250 1177 #define AHD_STAT_BUCKETS 4 1178 u_int cmdcmplt_bucket; 1179 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1180 uint32_t cmdcmplt_total; 1181 1182 /* 1183 * Errors statistics and printouts. 1184 */ 1185 struct sysctl_ctx_list sysctl_ctx[AHD_SYSCTL_NUMBER]; 1186 struct sysctl_oid *sysctl_tree[AHD_SYSCTL_NUMBER]; 1187 u_int summerr[AHD_ERRORS_NUMBER]; 1188 1189 /* 1190 * Card characteristics 1191 */ 1192 ahd_chip chip; 1193 ahd_feature features; 1194 ahd_bug bugs; 1195 ahd_flag flags; 1196 struct seeprom_config *seep_config; 1197 1198 /* Command Queues */ 1199 struct ahd_completion *qoutfifo; 1200 uint16_t qoutfifonext; 1201 uint16_t qoutfifonext_valid_tag; 1202 uint16_t qinfifonext; 1203 uint16_t qinfifo[AHD_SCB_MAX]; 1204 1205 /* 1206 * Our qfreeze count. The sequencer compares 1207 * this value with its own counter to determine 1208 * whether to allow selections to occur. 1209 */ 1210 uint16_t qfreeze_cnt; 1211 1212 /* Values to store in the SEQCTL register for pause and unpause */ 1213 uint8_t unpause; 1214 uint8_t pause; 1215 1216 /* Critical Section Data */ 1217 struct cs *critical_sections; 1218 u_int num_critical_sections; 1219 1220 /* Buffer for handling packetized bitbucket. */ 1221 uint8_t *overrun_buf; 1222 1223 /* Links for chaining softcs */ 1224 TAILQ_ENTRY(ahd_softc) links; 1225 1226 /* Channel Names ('A', 'B', etc.) */ 1227 char channel; 1228 1229 /* Initiator Bus ID */ 1230 uint8_t our_id; 1231 1232 /* 1233 * Target incoming command FIFO. 1234 */ 1235 struct target_cmd *targetcmds; 1236 uint8_t tqinfifonext; 1237 1238 /* 1239 * Cached verson of the hs_mailbox so we can avoid 1240 * pausing the sequencer during mailbox updates. 1241 */ 1242 uint8_t hs_mailbox; 1243 1244 /* 1245 * Incoming and outgoing message handling. 1246 */ 1247 uint8_t send_msg_perror; 1248 ahd_msg_flags msg_flags; 1249 ahd_msg_type msg_type; 1250 uint8_t msgout_buf[12];/* Message we are sending */ 1251 uint8_t msgin_buf[12];/* Message we are receiving */ 1252 u_int msgout_len; /* Length of message to send */ 1253 u_int msgout_index; /* Current index in msgout */ 1254 u_int msgin_index; /* Current index in msgin */ 1255 1256 /* 1257 * Mapping information for data structures shared 1258 * between the sequencer and kernel. 1259 */ 1260 bus_dma_tag_t parent_dmat; 1261 bus_dma_tag_t shared_data_dmat; 1262 struct map_node shared_data_map; 1263 1264 /* Information saved through suspend/resume cycles */ 1265 struct ahd_suspend_state suspend_state; 1266 1267 /* Number of enabled target mode device on this card */ 1268 u_int enabled_luns; 1269 1270 /* Initialization level of this data structure */ 1271 u_int init_level; 1272 1273 /* PCI cacheline size. */ 1274 u_int pci_cachesize; 1275 1276 /* PCI-X capability offset. */ 1277 int pcix_ptr; 1278 1279 /* IO Cell Parameters */ 1280 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1281 1282 u_int stack_size; 1283 uint16_t *saved_stack; 1284 1285 /* Per-Unit descriptive information */ 1286 const char *description; 1287 const char *bus_description; 1288 char *name; 1289 int unit; 1290 1291 /* Selection Timer settings */ 1292 int seltime; 1293 1294 /* 1295 * Interrupt coalescing settings. 1296 */ 1297 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1298 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1299 #define AHD_INT_COALESCING_MAXCMDS_MAX 127 1300 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1301 #define AHD_INT_COALESCING_MINCMDS_MAX 127 1302 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1303 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1304 u_int int_coalescing_timer; 1305 u_int int_coalescing_maxcmds; 1306 u_int int_coalescing_mincmds; 1307 u_int int_coalescing_threshold; 1308 u_int int_coalescing_stop_threshold; 1309 1310 uint16_t user_discenable;/* Disconnection allowed */ 1311 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1312 }; 1313 1314 TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1315 extern struct ahd_softc_tailq ahd_tailq; 1316 1317 /*************************** IO Cell Configuration ****************************/ 1318 #define AHD_PRECOMP_SLEW_INDEX \ 1319 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1320 1321 #define AHD_AMPLITUDE_INDEX \ 1322 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1323 1324 #define AHD_SET_SLEWRATE(ahd, new_slew) \ 1325 do { \ 1326 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1327 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1328 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1329 } while (0) 1330 1331 #define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1332 do { \ 1333 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1334 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1335 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1336 } while (0) 1337 1338 #define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1339 do { \ 1340 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1341 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1342 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1343 } while (0) 1344 1345 /************************ Active Device Information ***************************/ 1346 typedef enum { 1347 ROLE_UNKNOWN, 1348 ROLE_INITIATOR, 1349 ROLE_TARGET 1350 } role_t; 1351 1352 struct ahd_devinfo { 1353 int our_scsiid; 1354 int target_offset; 1355 uint16_t target_mask; 1356 u_int target; 1357 u_int lun; 1358 char channel; 1359 role_t role; /* 1360 * Only guaranteed to be correct if not 1361 * in the busfree state. 1362 */ 1363 }; 1364 1365 /****************************** PCI Structures ********************************/ 1366 #define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1367 #define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1368 #define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1369 1370 typedef int (ahd_device_setup_t)(struct ahd_softc *); 1371 1372 struct ahd_pci_identity { 1373 uint64_t full_id; 1374 uint64_t id_mask; 1375 char *name; 1376 ahd_device_setup_t *setup; 1377 }; 1378 extern struct ahd_pci_identity ahd_pci_ident_table []; 1379 extern const u_int ahd_num_pci_devs; 1380 1381 /*************************** Function Declarations ****************************/ 1382 /******************************************************************************/ 1383 void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1384 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1385 void ahd_busy_tcl(struct ahd_softc *ahd, 1386 u_int tcl, u_int busyid); 1387 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1388 static __inline void 1389 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1390 { 1391 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1392 } 1393 1394 /***************************** PCI Front End *********************************/ 1395 struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t); 1396 int ahd_pci_config(struct ahd_softc *, 1397 struct ahd_pci_identity *); 1398 int ahd_pci_test_register_access(struct ahd_softc *); 1399 1400 /************************** SCB and SCB queue management **********************/ 1401 int ahd_probe_scbs(struct ahd_softc *); 1402 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1403 struct scb *scb); 1404 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1405 int target, char channel, int lun, 1406 u_int tag, role_t role); 1407 1408 /****************************** Initialization ********************************/ 1409 struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1410 int ahd_softc_init(struct ahd_softc *); 1411 void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1412 int ahd_init(struct ahd_softc *ahd); 1413 int ahd_default_config(struct ahd_softc *ahd); 1414 int ahd_parse_vpddata(struct ahd_softc *ahd, 1415 struct vpd_config *vpd); 1416 int ahd_parse_cfgdata(struct ahd_softc *ahd, 1417 struct seeprom_config *sc); 1418 void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1419 void ahd_update_coalescing_values(struct ahd_softc *ahd, 1420 u_int timer, 1421 u_int maxcmds, 1422 u_int mincmds); 1423 void ahd_enable_coalescing(struct ahd_softc *ahd, 1424 int enable); 1425 void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1426 int ahd_suspend(struct ahd_softc *ahd); 1427 int ahd_resume(struct ahd_softc *ahd); 1428 void ahd_softc_insert(struct ahd_softc *); 1429 void ahd_set_unit(struct ahd_softc *, int); 1430 void ahd_set_name(struct ahd_softc *, char *); 1431 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1432 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1433 int ahd_alloc_scbs(struct ahd_softc *ahd); 1434 void ahd_free(struct ahd_softc *ahd); 1435 int ahd_reset(struct ahd_softc *ahd, int reinit); 1436 void ahd_shutdown(void *arg); 1437 int ahd_write_flexport(struct ahd_softc *ahd, 1438 u_int addr, u_int value); 1439 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1440 uint8_t *value); 1441 int ahd_wait_flexport(struct ahd_softc *ahd); 1442 1443 /*************************** Interrupt Services *******************************/ 1444 void ahd_pci_intr(struct ahd_softc *ahd); 1445 void ahd_clear_intstat(struct ahd_softc *ahd); 1446 void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1447 void ahd_run_qoutfifo(struct ahd_softc *ahd); 1448 #ifdef AHD_TARGET_MODE 1449 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1450 #endif 1451 void ahd_handle_hwerrint(struct ahd_softc *ahd); 1452 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1453 void ahd_handle_scsiint(struct ahd_softc *ahd, 1454 u_int intstat); 1455 void ahd_clear_critical_section(struct ahd_softc *ahd); 1456 1457 /***************************** Error Recovery *********************************/ 1458 typedef enum { 1459 SEARCH_COMPLETE, 1460 SEARCH_COUNT, 1461 SEARCH_REMOVE, 1462 SEARCH_PRINT 1463 } ahd_search_action; 1464 void ahd_done_with_status(struct ahd_softc *ahd, 1465 struct scb *scb, uint32_t status); 1466 int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1467 char channel, int lun, u_int tag, 1468 role_t role, uint32_t status, 1469 ahd_search_action action); 1470 int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1471 char channel, int lun, u_int tag, 1472 int stop_on_first, int remove, 1473 int save_state); 1474 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1475 int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1476 int initiate_reset); 1477 int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1478 char channel, int lun, u_int tag, 1479 role_t role, uint32_t status); 1480 void ahd_restart(struct ahd_softc *ahd); 1481 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1482 void ahd_handle_scb_status(struct ahd_softc *ahd, 1483 struct scb *scb); 1484 void ahd_handle_scsi_status(struct ahd_softc *ahd, 1485 struct scb *scb); 1486 void ahd_calc_residual(struct ahd_softc *ahd, 1487 struct scb *scb); 1488 void ahd_timeout(struct scb *scb); 1489 void ahd_recover_commands(struct ahd_softc *ahd); 1490 /*************************** Utility Functions ********************************/ 1491 struct ahd_phase_table_entry* 1492 ahd_lookup_phase_entry(int phase); 1493 void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1494 u_int our_id, u_int target, 1495 u_int lun, char channel, 1496 role_t role); 1497 /************************** Transfer Negotiation ******************************/ 1498 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1499 u_int *ppr_options, u_int maxsync); 1500 void ahd_validate_offset(struct ahd_softc *ahd, 1501 struct ahd_initiator_tinfo *tinfo, 1502 u_int period, u_int *offset, 1503 int wide, role_t role); 1504 void ahd_validate_width(struct ahd_softc *ahd, 1505 struct ahd_initiator_tinfo *tinfo, 1506 u_int *bus_width, 1507 role_t role); 1508 /* 1509 * Negotiation types. These are used to qualify if we should renegotiate 1510 * even if our goal and current transport parameters are identical. 1511 */ 1512 typedef enum { 1513 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1514 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1515 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1516 } ahd_neg_type; 1517 int ahd_update_neg_request(struct ahd_softc*, 1518 struct ahd_devinfo*, 1519 struct ahd_tmode_tstate*, 1520 struct ahd_initiator_tinfo*, 1521 ahd_neg_type); 1522 void ahd_set_width(struct ahd_softc *ahd, 1523 struct ahd_devinfo *devinfo, 1524 u_int width, u_int type, int paused); 1525 void ahd_set_syncrate(struct ahd_softc *ahd, 1526 struct ahd_devinfo *devinfo, 1527 u_int period, u_int offset, 1528 u_int ppr_options, 1529 u_int type, int paused); 1530 typedef enum { 1531 AHD_QUEUE_NONE, 1532 AHD_QUEUE_BASIC, 1533 AHD_QUEUE_TAGGED 1534 } ahd_queue_alg; 1535 1536 void ahd_set_tags(struct ahd_softc *ahd, 1537 struct ahd_devinfo *devinfo, 1538 ahd_queue_alg alg); 1539 1540 /**************************** Target Mode *************************************/ 1541 #ifdef AHD_TARGET_MODE 1542 void ahd_send_lstate_events(struct ahd_softc *, 1543 struct ahd_tmode_lstate *); 1544 void ahd_handle_en_lun(struct ahd_softc *ahd, 1545 struct cam_sim *sim, union ccb *ccb); 1546 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1547 struct cam_sim *sim, union ccb *ccb, 1548 struct ahd_tmode_tstate **tstate, 1549 struct ahd_tmode_lstate **lstate, 1550 int notfound_failure); 1551 #ifndef AHD_TMODE_ENABLE 1552 #define AHD_TMODE_ENABLE 0 1553 #endif 1554 #endif 1555 /******************************* Debug ***************************************/ 1556 #ifdef AHD_DEBUG 1557 extern uint32_t ahd_debug; 1558 #define AHD_SHOW_MISC 0x00001 1559 #define AHD_SHOW_SENSE 0x00002 1560 #define AHD_SHOW_RECOVERY 0x00004 1561 #define AHD_DUMP_SEEPROM 0x00008 1562 #define AHD_SHOW_TERMCTL 0x00010 1563 #define AHD_SHOW_MEMORY 0x00020 1564 #define AHD_SHOW_MESSAGES 0x00040 1565 #define AHD_SHOW_MODEPTR 0x00080 1566 #define AHD_SHOW_SELTO 0x00100 1567 #define AHD_SHOW_FIFOS 0x00200 1568 #define AHD_SHOW_QFULL 0x00400 1569 #define AHD_SHOW_DV 0x00800 1570 #define AHD_SHOW_MASKED_ERRORS 0x01000 1571 #define AHD_SHOW_QUEUE 0x02000 1572 #define AHD_SHOW_TQIN 0x04000 1573 #define AHD_SHOW_SG 0x08000 1574 #define AHD_SHOW_INT_COALESCING 0x10000 1575 #define AHD_DEBUG_SEQUENCER 0x20000 1576 #endif 1577 void ahd_print_scb(struct scb *scb); 1578 void ahd_print_devinfo(struct ahd_softc *ahd, 1579 struct ahd_devinfo *devinfo); 1580 void ahd_dump_sglist(struct scb *scb); 1581 void ahd_dump_all_cards_state(void); 1582 void ahd_dump_card_state(struct ahd_softc *ahd); 1583 int ahd_print_register(ahd_reg_parse_entry_t *table, 1584 u_int num_entries, 1585 const char *name, 1586 u_int address, 1587 u_int value, 1588 u_int *cur_column, 1589 u_int wrap_point); 1590 void ahd_dump_scbs(struct ahd_softc *ahd); 1591 #endif /* _AIC79XX_H_ */ 1592