1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Robert N. M. Watson 5 * All rights reserved. 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 9 * ("CTSRD"), as part of the DARPA CRASH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/cons.h> 39 #include <sys/endian.h> 40 #include <sys/kdb.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/reboot.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 #include <sys/tty.h> 48 49 #include <ddb/ddb.h> 50 51 #include <dev/altera/jtag_uart/altera_jtag_uart.h> 52 53 devclass_t altera_jtag_uart_devclass; 54 55 static SYSCTL_NODE(_hw, OID_AUTO, altera_jtag_uart, CTLFLAG_RW, 0, 56 "Altera JTAG UART configuration knobs"); 57 58 /* 59 * One-byte buffer as we can't check whether the UART is readable without 60 * actually reading from it, synchronised by a spinlock; this lock also 61 * synchronises access to the I/O ports for non-atomic sequences. These 62 * symbols are public so that the TTY layer can use them when working on an 63 * instance of the UART that is also a low-level console. 64 */ 65 char aju_cons_buffer_data; 66 int aju_cons_buffer_valid; 67 int aju_cons_jtag_present; 68 u_int aju_cons_jtag_missed; 69 struct mtx aju_cons_lock; 70 71 /* 72 * Low-level console driver functions. 73 */ 74 static cn_probe_t aju_cnprobe; 75 static cn_init_t aju_cninit; 76 static cn_term_t aju_cnterm; 77 static cn_getc_t aju_cngetc; 78 static cn_putc_t aju_cnputc; 79 static cn_grab_t aju_cngrab; 80 static cn_ungrab_t aju_cnungrab; 81 82 /* 83 * JTAG sets the ALTERA_JTAG_UART_CONTROL_AC bit whenever it accesses the 84 * FIFO. This allows us to (sort of) tell when JTAG is present, so that we 85 * can adopt lossy, rather than blocking, behaviour when JTAG isn't there. 86 * When it is present, we do full flow control. This delay is how long we 87 * wait to see if JTAG has really disappeared when finding a full buffer and 88 * no AC bit set. 89 */ 90 #define ALTERA_JTAG_UART_AC_POLL_DELAY 10000 91 static u_int altera_jtag_uart_ac_poll_delay = 92 ALTERA_JTAG_UART_AC_POLL_DELAY; 93 SYSCTL_UINT(_hw_altera_jtag_uart, OID_AUTO, ac_poll_delay, 94 CTLFLAG_RW, &altera_jtag_uart_ac_poll_delay, 0, 95 "Maximum delay waiting for JTAG present flag when buffer is full"); 96 97 /* 98 * I/O routines lifted from Deimos. This is not only MIPS-specific, but also 99 * BERI-specific, as we're hard coding the address at which we expect to 100 * find the Altera JTAG UART and using it unconditionally. We use these 101 * low-level routines so that we can perform console I/O long before newbus 102 * has initialised and devices have attached. The TTY layer of the driver 103 * knows about this, and uses the console-layer spinlock instead of the 104 * TTY-layer lock to avoid confusion between layers for the console UART. 105 * 106 * XXXRW: The only place this inter-layer behaviour breaks down is if the 107 * low-level console is used for polled read while the TTY driver is also 108 * looking for input. Probably we should also share buffers between layers. 109 */ 110 #define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000 111 112 typedef uint64_t paddr_t; 113 typedef uint64_t vaddr_t; 114 115 static inline vaddr_t 116 mips_phys_to_uncached(paddr_t phys) 117 { 118 119 return (phys | MIPS_XKPHYS_UNCACHED_BASE); 120 } 121 122 static inline uint32_t 123 mips_ioread_uint32(vaddr_t vaddr) 124 { 125 uint32_t v; 126 127 __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 128 return (v); 129 } 130 131 static inline void 132 mips_iowrite_uint32(vaddr_t vaddr, uint32_t v) 133 { 134 135 __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr)); 136 } 137 138 /* 139 * Little-endian versions of 32-bit I/O routines. 140 */ 141 static inline uint32_t 142 mips_ioread_uint32le(vaddr_t vaddr) 143 { 144 145 return (le32toh(mips_ioread_uint32(vaddr))); 146 } 147 148 static inline void 149 mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v) 150 { 151 152 mips_iowrite_uint32(vaddr, htole32(v)); 153 } 154 155 /* 156 * Low-level read and write register routines; the Altera UART is little 157 * endian, so we byte swap 32-bit reads and writes. 158 */ 159 static inline uint32_t 160 aju_cons_data_read(void) 161 { 162 163 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 164 ALTERA_JTAG_UART_DATA_OFF))); 165 } 166 167 static inline void 168 aju_cons_data_write(uint32_t v) 169 { 170 171 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 172 ALTERA_JTAG_UART_DATA_OFF), v); 173 } 174 175 static inline uint32_t 176 aju_cons_control_read(void) 177 { 178 179 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 180 ALTERA_JTAG_UART_CONTROL_OFF))); 181 } 182 183 static inline void 184 aju_cons_control_write(uint32_t v) 185 { 186 187 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 188 ALTERA_JTAG_UART_CONTROL_OFF), v); 189 } 190 191 /* 192 * Slightly higher-level routines aware of buffering and flow control. 193 */ 194 static int 195 aju_cons_readable(void) 196 { 197 uint32_t v; 198 199 AJU_CONSOLE_LOCK_ASSERT(); 200 201 if (aju_cons_buffer_valid) 202 return (1); 203 v = aju_cons_data_read(); 204 if ((v & ALTERA_JTAG_UART_DATA_RVALID) != 0) { 205 aju_cons_buffer_valid = 1; 206 aju_cons_buffer_data = (v & ALTERA_JTAG_UART_DATA_DATA); 207 return (1); 208 } 209 return (0); 210 } 211 212 static void 213 aju_cons_write(char ch) 214 { 215 uint32_t v; 216 217 AJU_CONSOLE_LOCK_ASSERT(); 218 219 /* 220 * The flow control logic here is somewhat subtle: we want to wait for 221 * write buffer space only while JTAG is present. However, we can't 222 * directly ask if JTAG is present -- just whether it's been seen 223 * since we last cleared the ALTERA_JTAG_UART_CONTROL_AC bit. As 224 * such, implement a polling loop in which we both wait for space and 225 * try to decide whether JTAG has disappeared on us. We will have to 226 * wait one complete polling delay to detect that JTAG has gone away, 227 * but otherwise shouldn't wait any further once it has gone. And we 228 * had to wait for buffer space anyway, if it was there. 229 * 230 * If JTAG is spotted, reset the TTY-layer miss counter so console- 231 * layer clearing of the bit doesn't trigger a TTY-layer 232 * disconnection. 233 * 234 * XXXRW: Notice the inherent race with hardware: in clearing the 235 * bit, we may race with hardware setting the same bit. This can 236 * cause real-world reliability problems due to lost output on the 237 * console. 238 */ 239 v = aju_cons_control_read(); 240 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 241 aju_cons_jtag_present = 1; 242 aju_cons_jtag_missed = 0; 243 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 244 aju_cons_control_write(v); 245 } 246 while ((v & ALTERA_JTAG_UART_CONTROL_WSPACE) == 0) { 247 if (!aju_cons_jtag_present) 248 return; 249 DELAY(altera_jtag_uart_ac_poll_delay); 250 v = aju_cons_control_read(); 251 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 252 aju_cons_jtag_present = 1; 253 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 254 aju_cons_control_write(v); 255 } else 256 aju_cons_jtag_present = 0; 257 } 258 aju_cons_data_write(ch); 259 } 260 261 static char 262 aju_cons_read(void) 263 { 264 265 AJU_CONSOLE_LOCK_ASSERT(); 266 267 while (!aju_cons_readable()); 268 aju_cons_buffer_valid = 0; 269 return (aju_cons_buffer_data); 270 } 271 272 /* 273 * Implementation of a FreeBSD low-level, polled console driver. 274 */ 275 static void 276 aju_cnprobe(struct consdev *cp) 277 { 278 279 sprintf(cp->cn_name, "%s%d", AJU_TTYNAME, 0); 280 cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL; 281 } 282 283 static void 284 aju_cninit(struct consdev *cp) 285 { 286 uint32_t v; 287 288 AJU_CONSOLE_LOCK_INIT(); 289 290 AJU_CONSOLE_LOCK(); 291 v = aju_cons_control_read(); 292 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 293 aju_cons_control_write(v); 294 AJU_CONSOLE_UNLOCK(); 295 } 296 297 static void 298 aju_cnterm(struct consdev *cp) 299 { 300 301 } 302 303 static int 304 aju_cngetc(struct consdev *cp) 305 { 306 int ret; 307 308 AJU_CONSOLE_LOCK(); 309 ret = aju_cons_read(); 310 AJU_CONSOLE_UNLOCK(); 311 return (ret); 312 } 313 314 static void 315 aju_cnputc(struct consdev *cp, int c) 316 { 317 318 AJU_CONSOLE_LOCK(); 319 aju_cons_write(c); 320 AJU_CONSOLE_UNLOCK(); 321 } 322 323 static void 324 aju_cngrab(struct consdev *cp) 325 { 326 327 } 328 329 static void 330 aju_cnungrab(struct consdev *cp) 331 { 332 333 } 334 335 CONSOLE_DRIVER(aju); 336